Search Results - acm: d.: software/d.3: programming languages/d.3.4: (processes OR process)

Adapting Application Mapping to Systematic Within-Die Process Variations on Chip Multiprocessors

Authors: Ding, Yang Kandemir, Mahmut Irwin, Mary Jane et al.

Contributors: Ding, Yang Kandemir, Mahmut Irwin, Mary Jane et al.

Source: HiPEAC 2009 - High Performance and Embedded Architectures and Compilers ; https://hal.inria.fr/inria-00446018 ; HiPEAC 2009 - High Performance and Embedded Architectures and Compilers, Jan 2009, Paphos, Cyprus. ⟨10.1007/978-3-540-92990-1_18⟩

Subject Terms: ACM: B.: Hardware/B.2: ARITHMETIC AND LOGIC STRUCTURES, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES, ACM: D.: Software/D.3: PROGRAMMING LANGUAGES/D.3.4: Processors, [INFO.INFO-OH]Computer Science [cs]/Other [cs.OH], [INFO.INFO-ES]Computer Science [cs]/Embedded Systems

Subject Geographic: Paphos, Cyprus

Relation: inria-00446018; https://hal.inria.fr/inria-00446018

Availability: https://hal.inria.fr/inria-00446018
https://doi.org/10.1007/978-3-540-92990-1_18

Partial Evaluation of Dense Code on Sparse Structures ; Évaluation partielle de codes denses sur des structures creuses

Authors: Dehame, Gabriel Alias, Christophe Sadler, Alec et al.

Contributors: Dehame, Gabriel Alias, Christophe Sadler, Alec et al.

Source: https://inria.hal.science/hal-04358187 ; RR-9534, INRIA Lyon; CNRS; ENS de Lyon; Université de Lyon. 2023, pp.16.

Subject Terms: Code optimization, Sparse code, Specialization, JEL: C - Mathematical and Quantitative Methods/C.C6 - Mathematical Methods • Programming Models • Mathematical and Simulation Modeling/C.C6.C61 - Optimization Techniques • Programming Models • Dynamic Analysis, ACM: D.: Software/D.3: PROGRAMMING LANGUAGES/D.3.4: Processors/D.3.4.6: Optimization, [INFO.INFO-DC]Computer Science [cs]/Distributed, Parallel, and Cluster Computing [cs.DC], [INFO.INFO-SC]Computer Science [cs]/Symbolic Computation [cs.SC]

Availability: https://inria.hal.science/hal-04358187
https://inria.hal.science/hal-04358187v1/document
https://inria.hal.science/hal-04358187v1/file/RR-9534.pdf

Towards Trace-Based Array Contraction

Authors: Thievenaz, Hugo Kimura, Keiji Alias, Christophe et al.

Contributors: Thievenaz, Hugo Kimura, Keiji Alias, Christophe et al.

Source: https://inria.hal.science/hal-03482055 ; [Research Report] RR-9442, Inria; Waseda University. 2021, pp.20.

Subject Terms: Compilation, array contraction, polyhedral model, dynamic analysis, contraction de tableaux, modèle polyédrique, analyse dynamique, ACM: D.: Software/D.3: PROGRAMMING LANGUAGES/D.3.4: Processors/D.3.4.1: Compilers, [INFO.INFO-DC]Computer Science [cs]/Distributed, Parallel, and Cluster Computing [cs.DC], [INFO.INFO-PL]Computer Science [cs]/Programming Languages [cs.PL]

Availability: https://inria.hal.science/hal-03482055
https://inria.hal.science/hal-03482055v1/document
https://inria.hal.science/hal-03482055v1/file/RR-9442.pdf

Hardware-Accelerated Dynamic Binary Translation

Authors: Rokicki, Simon Rohou, Erven Derrien, Steven et al.

Contributors: Rokicki, Simon Rohou, Erven Derrien, Steven et al.

Source: IEEE/ACM Design, Automation & Test in Europe Conference & Exhibition (DATE) ; https://inria.hal.science/hal-01423639 ; IEEE/ACM Design, Automation & Test in Europe Conference & Exhibition (DATE), Mar 2017, Lausanne, Switzerland ; https://www.date-conference.com/

Subject Terms: ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.3: Other Architecture Styles/C.1.3.5: Heterogeneous (hybrid) systems, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.3: Other Architecture Styles/C.1.3.0: Adaptable architectures, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.2: Multiple Data Stream Architectures (Multiprocessors)/C.1.2.4: Multiple-instruction-stream, multiple-data-stream processors (MIMD), ACM: D.: Software/D.3: PROGRAMMING LANGUAGES/D.3.4: Processors/D.3.4.0: Code generation, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [INFO.INFO-ES]Computer Science [cs]/Embedded Systems

Subject Geographic: Lausanne, Switzerland

Availability: https://inria.hal.science/hal-01423639
https://inria.hal.science/hal-01423639v1/document
https://inria.hal.science/hal-01423639v1/file/rokicki_DATE_cr.pdf

EUGENE: a STEP-based framework to build Application Generators

Authors: Plantec, Alain Ribaud, Vincent Lab-STICC_UBO_CACS_MOCS et al.

Contributors: Plantec, Alain Ribaud, Vincent Lab-STICC_UBO_CACS_MOCS et al.

Source: CSIRO-Macquarie University ; 1st Australian Workshop on Constructing Software Engineering Tools ; https://hal.univ-brest.fr/hal-01078451 ; 1st Australian Workshop on Constructing Software Engineering Tools, CSIRO-Macquarie University, Nov 1998, Adelaide, Australia

Subject Terms: meta-model, application generator, ACM: D.: Software/D.3: PROGRAMMING LANGUAGES/D.3.4: Processors/D.3.4.0: Code generation, ACM: D.: Software/D.2: SOFTWARE ENGINEERING/D.2.3: Coding Tools and Techniques, [INFO.INFO-SE]Computer Science [cs]/Software Engineering [cs.SE]

Subject Geographic: Adelaide, Australia

Availability: https://hal.univ-brest.fr/hal-01078451
https://hal.univ-brest.fr/hal-01078451v1/document
https://hal.univ-brest.fr/hal-01078451v1/file/AWCSET98.pdf

The next 700 Krivine machines

Authors: Douence, Rémi Fradet, Pascal Objects, aspects and components (OBASCO) et al.

Contributors: Douence, Rémi Fradet, Pascal Objects, aspects and components (OBASCO) et al.

Source: Higher-Order and Symbolic Computation. 20:237-255

Subject Terms: program transformation, [INFO.INFO-PL]Computer Science [cs]/Programming Languages [cs.PL], Krivine machine, Functional Programming, 0102 computer and information sciences, 02 engineering and technology, 01 natural sciences, [INFO.INFO-PL] Computer Science [cs]/Programming Languages [cs.PL], ACM: D.: Software/D.3: PROGRAMMING LANGUAGES/D.3.4: Processors/D.3.4.1: Compilers, compilation, 0202 electrical engineering, electronic engineering, information engineering, abstract machines, ACM: D.: Software/D.1: PROGRAMMING TECHNIQUES/D.1.1: Applicative (Functional) Programming, functional language implementations

File Description: application/pdf

Access URL: https://hal.inria.fr/inria-00000940/file/HOSC06.pdf
https://inria.hal.science/inria-00000940v1
https://inria.hal.science/inria-00000940v1/document
https://doi.org/10.1007/s10990-007-9016-y

Processor Virtualization and Split Compilation for Heterogeneous Multicore Embedded Systems

Authors: Cohen, Albert Rohou, Erven Architectures, Languages and Compilers to Harness the End of Moore Years (ALCHEMY) et al.

Contributors: Cohen, Albert Rohou, Erven Architectures, Languages and Compilers to Harness the End of Moore Years (ALCHEMY) et al.

Source: 47th Annual Design Automation Conference
https://inria.hal.science/inria-00472274
47th Annual Design Automation Conference, Jun 2010, Anaheim, CA, United States

Subject Terms: Heterogeneous multicore, virtualization, bytecode language, annotations, split compilation, portable performance, specialization, vectorization, back-end optimization, ACM: D.: Software/D.3: PROGRAMMING LANGUAGES/D.3.4: Processors/D.3.4.1: Compilers, [INFO.INFO-OH]Computer Science [cs]/Other [cs.OH]

Subject Geographic: Anaheim, CA, United States

Availability: https://inria.hal.science/inria-00472274
https://inria.hal.science/inria-00472274/document
https://inria.hal.science/inria-00472274/file/DAC_2010.pdf

Schedule-Sensitive Register Pressure Reduction in Innermost Loops, Basic Blocks and Super-Blocks

Authors: Briais, Sébastien Touati, Sid Parallélisme, Réseaux, Systèmes, Modélisation (PRISM) et al.

Contributors: Briais, Sébastien Touati, Sid Parallélisme, Réseaux, Systèmes, Modélisation (PRISM) et al.

Source: https://inria.hal.science/inria-00436348 ; [Research Report] 2009, pp.53.

Subject Terms: Compilation, Code optimisation, Register pressure, Instruction level parallelism, ACM: D.: Software/D.3: PROGRAMMING LANGUAGES/D.3.4: Processors/D.3.4.1: Compilers, ACM: D.: Software/D.3: PROGRAMMING LANGUAGES/D.3.4: Processors/D.3.4.6: Optimization, ACM: D.: Software/D.3: PROGRAMMING LANGUAGES/D.3.4: Processors/D.3.4.0: Code generation, [INFO.INFO-OH]Computer Science [cs]/Other [cs.OH]

Availability: https://inria.hal.science/inria-00436348
https://inria.hal.science/inria-00436348v1/document
https://inria.hal.science/inria-00436348v1/file/main_siralina_report.pdf

Accomodating Diversity in CMPs with Heterogeneous Frequencies

Authors: Bhadauria, Major Weaver, Vince Mckee, Sally A. et al.

Contributors: Bhadauria, Major Weaver, Vince Mckee, Sally A. et al.

Source: HiPEAC 2009 - High Performance and Embedded Architectures and Compilers ; https://hal.inria.fr/inria-00446283 ; HiPEAC 2009 - High Performance and Embedded Architectures and Compilers, Jan 2009, Paphos, Cyprus. ⟨10.1007/978-3-540-92990-1_19⟩

Subject Terms: ACM: B.: Hardware/B.2: ARITHMETIC AND LOGIC STRUCTURES, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES, ACM: D.: Software/D.3: PROGRAMMING LANGUAGES/D.3.4: Processors, [INFO.INFO-OH]Computer Science [cs]/Other [cs.OH], [INFO.INFO-ES]Computer Science [cs]/Embedded Systems

Subject Geographic: Paphos, Cyprus

Relation: inria-00446283; https://hal.inria.fr/inria-00446283

Availability: https://hal.inria.fr/inria-00446283
https://doi.org/10.1007/978-3-540-92990-1_19