Search Results - acm: c.: computer systems organization/c.1: processor architectures/c.1.4: parallel architektury*

Proceedings of the 1989 ACM symposium on parallel algorithms and architectures

Source: Conference: Association for Computing Machinery (ACM) symposium on parallel algorithms and architectures, Santa Fe, NM (United States), 18-21 Jun 1989

File Description: Medium: X; Size: Pages: (434 p)

Access URL: http://www.osti.gov/scitech/biblio/5015495

Multi-core and Single-core Raspberry Pi Microprocessor's.

Alternate Title: Wielordzeniowe i jednordzeniowe mikroprocesory Raspberry Pi. (Polish)

Authors: SAINUDDIN, Nurulidayu MOHD SULTAN, Juwita AZUANI, Mohamed

Source: Przegląd Elektrotechniczny; 2023, Vol. 99 Issue 1, p38-43, 6p

Subject Terms: RASPBERRY Pi, CENTRAL processing units, MICROPROCESSORS, COMPUTER performance, COMPUTER multitasking, MULTICORE processors

Proceedings of the 2nd annual ACM symposium on parallel algorithms and architectures

Source: Conference: SPAA '90: 2nd annual Association for Computing Machinery (ACM) symposium on parallel algorithms and architectures, Island of Crete (Greece), 2-6 Jul 1990

File Description: Medium: X; Size: Pages: (417 p)

Access URL: http://www.osti.gov/scitech/biblio/5015823

A Massively Parallel Adaptive Fast-Multipole Method on Heterogeneous Architectures

Contributors: Biros, George [University of Texas, Austin]

Source: Conference: ACM/IEEE Supercomputing, Portland, OR, USA, 20091114, 20091114

File Description: Medium: X

Access URL: http://www.osti.gov/scitech/biblio/1033545

Peephole optimalizátor pro konfigurovatelné architektury procesorů ; Peephole Optimizer for Configurable Processor Architectures

Authors: Ministr, Martin Masařík, Karel Křoustek, Jakub

Contributors: Ministr, Martin Masařík, Karel Křoustek, Jakub

Subject Terms: peephole optimalizátor, peephole optimalizace, LLVM, backend, překladač, mikroprocesorová architektura, popis architektury, peephole optimizer, peephole optimization, compiler, microprocessor architecture, architecture description

File Description: text/html

Relation: MINISTR, M. Peephole optimalizátor pro konfigurovatelné architektury procesorů [online]. Brno: Vysoké učení technické v Brně. Fakulta informačních technologií. 2012.; 79137; http://hdl.handle.net/11012/52891

Availability: http://hdl.handle.net/11012/52891

Analysis of FPGA accelerator architecture for Fast Statistical Convolutional Neural Network in real time Emotional Recognition System.

Alternate Title: Analiza architektury akceleratora FPGA dla szybkiej statystycznej sieci splotowej w systemie rozpoznawania emocji w czasie rzeczywistym. (Polish)

Authors: Samson Immanuel, J. Manoj, G. Prince, Shajin et al.

Source: Przegląd Elektrotechniczny; 2021, Vol. 97 Issue 7, p132-134, 3p

Subject Terms: DEEP learning, CONVOLUTIONAL neural networks, ARTIFICIAL intelligence, APPLICATION-specific integrated circuits, FIELD programmable gate arrays, ALGORITHMS

TALL—a list processor for the Philco 2000 computer

Authors: Feldman, Julian

Source: Communications of the ACM. 5(9)

Subject Terms: Information and Computing Sciences, Information Systems, Information and computing sciences

File Description: application/pdf

Access URL: https://escholarship.org/uc/item/6qk36727
https://escholarship.org/content/qt6qk36727/qt6qk36727.pdf

Każda reprezentacja jest interpretacją -- w stronę hermeneutycznej koncepcji architektury informacji. (Polish)

Alternate Title: Every Representation is an Interpretation: A Hermeneutic Approach to Information Architecture. (English)

Authors: Roszkowski, Marcin

Source: Zagadnienia Informacji Naukowej; 2019, Vol. 114 Issue 2, p61-79, 19p

Architektura macierzy stosów do przetwarzania równoległego z wykorzystaniem odwrotnej notacji polskiej. (Polish)

Alternate Title: Stack matrix architecture for parallel processing using reverse Polish notation. (English)

Authors: GOŁKA, Łukasz SUSZYŃSKI, Robert POCZEKAJŁO, Paweł

Source: Przegląd Elektrotechniczny; 2025, Issue 10, p82-89, 8p

Subject Terms: PARALLEL processing, SIMD (Computer architecture), CENTRAL processing units, MATHEMATICAL notation

The Study of the Influence of Architecture on Effectiveness of Deep Neural Networks Training.

Alternate Title: Badania wpływu architektury na skuteczność uczenia głębokich sieci neuronowych. (Polish)

Authors: Kolbusz, Janusz Różycki, Paweł Bartczak, Tomasz

Source: Zeszyty Naukowe Uczelni Vistula/ Vistula University Working Papers; 2018, Vol. 59 Issue 2, p60-71, 12p

Subject Terms: NEURAL circuitry, DEEP learning, COMPUTER network architectures, INFORMATION technology industry, COMPUTER training

PROPOSAL FOR NEW AUTOMATION ARCHITECTURE SOLUTIONS FOR INDUSTRY 4.0.

Alternate Title: EIN VORSCHLAG FÜR DIE ARCHITEKTUR AUTOMATISCHER TECHNOLOGIE-LÖSUNGEN FÜR INDUSTRY 4.0. (German)
PROPOZYCJA ARCHITEKTURY ROZWIĄZAŃ AUTOMATYCZNYCH DLA INDUSTRY 4.0. (Polish)

Authors: Saturno, Maicon Pertel, Vinicius M. Deschamps, Fernando et al.

Source: LogForum; 2018, Vol. 14 Issue 2, p185-195, 11p

Subject Terms: AUTOMATION, MANUFACTURING processes, INTERNATIONAL business enterprises, INDUSTRIAL productivity, ORGANIZATIONAL performance

Advanced Computer Architectures.

Authors: Fox, Geoffrey C. Messina, Paul C.

Source: Scientific American. Oct 1987 257(4):66-74.

Peer Reviewed: N

Page Count: 9

Descriptors: Computer Software, Computers, Efficiency, Information Technology, Input Output, Input Output Devices, Problem Solving, Programing, Programing Languages, Science and Society, Systems Approach, Technological Advancement, Technology

Journal Code: CIJJAN1988

MATHEMATICAL MODEL AND STRUCTURE OF A NEURAL NETWORK FOR DETECTION OF CYBER ATTACKS ON INFORMATION AND COMMUNICATION SYSTEMS.

Alternate Title: MODEL MATEMATYCZNY I STRUKTURA SIECI NEURONOWEJ DO WYKRYWANIA CYBERATAKÓW NA SYSTEMY TELEINFORMATYCZNE I KOMUNIKACYJNE. (Polish)

Authors: Zahoruiko, Lubov Martianova, Tetiana Al-Hiari, Mohammad et al.

Source: Informatics Control Measurement in Economy & Environment Protection / Informatyka, Automatyka, Pomiary w Gospodarce i Ochronie Środowiska; 2024, Vol. 14 Issue 3, p49-55, 7p

Subject Terms: COMPUTER network traffic, ARTIFICIAL neural networks, COMPUTER networks, COMPUTER systems, TELECOMMUNICATION systems

IMPACT OF FRAME ARCHITECTURE ON ROAD TRAFFIC SAFETY MANAGEMENT.

Alternate Title: WPŁYW ZASTOSOWANIA ARCHITEKTURY FRAME NA ZARZĄDZANIE BEZPIECZEŃSTWEM RUCHU DROGOWEGO. (Polish)

Authors: Szewczyk, Sylwia Siergiejczyk, Mirosław Krzykowska, Karolina

Source: Journal of Konbin; Oct2017, Vol. 43 Issue 1, p343-352, 10p

Subject Terms: TRAFFIC engineering & the environment, KNOWLEDGE transfer, TRAFFIC safety, COMPUTER network architectures, INTELLIGENT transportation systems

Novel Methodology for Automated Generation of Flexible Hardware Architectures.

Alternate Title: Nowa metoda automatycznego generowania elastycznej architektury sprzętowej. (Polish)

Authors: PEDRINO, Emerson Carlos GALLON, Igor Felipe VALENTE, Fredy João et al.

Source: Przegląd Elektrotechniczny; 2018, Vol. 94 Issue 4, p17-21, 5p

Subject Terms: GENETIC programming, FIELD programmable gate arrays, VERILOG (Computer hardware description language), HIGH-Level Data Link Control (Computer network protocol), EVOLUTIONARY algorithms

A Massively Parallel Adaptive Fast Multipole Method on Heterogeneous Architectures

Contributors: Biros, George [University of Texas, Austin]

Source: Communications of the ACM; 55; 5

File Description: Medium: X; Size: 101

Access URL: http://www.osti.gov/scitech/biblio/1039644

Neighborhood - Adaptable Processor for Multi - Processing ; Hardware Architectures for Morphological Filters with Large Structuring Elements ; Číslicové architektury pro morfologické filtry s velkými strukturujícími elementy

Authors: Bartovský, Jan Georgiev, Vjačeslav

Contributors: Bartovský, Jan Georgiev, Vjačeslav

Subject Terms: matematická morfologie, morfologický filtr, obvodová implementace, algoritmus, FPGA, mathematical morphology, morphological filter, hardware implementation, algorithm

File Description: 157 s.; application/pdf

Relation: 36922; http://hdl.handle.net/11025/5152

Availability: http://hdl.handle.net/11025/5152

An Evaluation of Global Address Space Languages: Co-Array Fortran and Unified Parallel C

Contributors: Chavarría-Miranda, Daniel

Source: Conference: Proceedings of the tenth ACM SIGPLAN symposium on principles and practice of parallel programming, PPoPP’05, June 15–17, 2005, Chicago, Illinois, 36-47

File Description: Medium: X

Access URL: http://www.osti.gov/scitech/biblio/881945

Implementace generického procesoru v FPGA

Authors: Mikušek, Petr Martínek, Tomáš Kořenek, Jan

Contributors: Mikušek, Petr Martínek, Tomáš Kořenek, Jan

Subject Terms: Virtex-II Pro, transport triggered architectures, processor architectures, VLIW, přenosem spouštěné architektury, VHDL, COMBO6X, FPGA, architektury procesorů

File Description: application/pdf; text/html

Access URL: http://hdl.handle.net/11012/54028

Návrh pokročilé architektury procesoru v jazyce VHDL

Authors: Slavík, Daniel Straka, Martin Šimek, Václav

Contributors: Slavík, Daniel Straka, Martin Šimek, Václav

Subject Terms: scalar, RAM, superscalar, návrh, design, procesor, cache, subscalar, VHDL, superskalární, processor, subskalární, skalární

File Description: application/pdf; text/html

Access URL: http://hdl.handle.net/11012/54277