Search Results - acm: c.: computer systems organization/c.1: processor architecture*

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  1. 1

    Novel Architecture of Smart FFT Processor

    Authors: Teymourzadeh, Rozita University of California San Francisco (UC San Francisco) University of California (UC)

    Contributors: Teymourzadeh, Rozita University of California San Francisco (UC San Francisco) University of California (UC)

    Source: https://hal.archives-ouvertes.fr/hal-01802071 ; 2014.

    Subject Terms: FFT, Digital Design, Processor, VLSI, Novel Architecture, Radix, Harmonic, ACM: D.: Software, ACM: B.: Hardware, ACM: C.: Computer Systems Organization, ACM: I.: Computing Methodologies, ACM: B.: Hardware/B.6: LOGIC DESIGN, ACM: B.: Hardware/B.5: REGISTER-TRANSFER-LEVEL IMPLEMENTATION, ACM: D.: Software/D.3: PROGRAMMING LANGUAGES, [INFO]Computer Science [cs], [INFO.INFO-AO]Computer Science [cs]/Computer Arithmetic, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [INFO.INFO-ES]Computer Science [cs]/Embedded Systems, [INFO.INFO-TS]Computer Science [cs]/Signal and Image Processing, [SPI]Engineering Sciences [physics], [SPI.SIGNAL]Engineering Sciences [physics]/Signal and Image processing, [SPI.TRON]Engineering Sciences [physics]/Electronics

    Relation: hal-01802071; https://hal.archives-ouvertes.fr/hal-01802071; https://hal.archives-ouvertes.fr/hal-01802071/document; https://hal.archives-ouvertes.fr/hal-01802071/file/Novel%20Architecture%20of%20Smart%20FFT%20Processor_Draft.pdf

    Availability: https://hal.archives-ouvertes.fr/hal-01802071
    https://hal.archives-ouvertes.fr/hal-01802071/document
    https://hal.archives-ouvertes.fr/hal-01802071/file/Novel%20Architecture%20of%20Smart%20FFT%20Processor_Draft.pdf

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  2. 2

    Towards a New Processor Architecture. ; Vers une nouvelle Architecture de Processeurs

    Authors: Vincent, Pierre Landru, Jacques Ecole nationale supérieure Mines-Télécom Lille Douai (IMT Nord Europe) et al.

    Contributors: Vincent, Pierre Landru, Jacques Ecole nationale supérieure Mines-Télécom Lille Douai (IMT Nord Europe) et al.

    Source: https://hal.science/hal-05117313 ; 2025.

    Subject Terms: silicon, parallel, serial, RISC, photonics, computer, optronics, optics, processor, fiber, laser, digital, silicium, parallèle, série, processeur, photonique, ordinateur, optronique, optique, numérique, fibre, ACM: B.: Hardware, ACM: C.: Computer Systems Organization, [INFO]Computer Science [cs], [PHYS]Physics [physics]

    Availability: https://hal.science/hal-05117313
    https://hal.science/hal-05117313v2/document
    https://hal.science/hal-05117313v2/file/frParalSerieRiscV1.pdf

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  3. 3

    Introduction à l'architecture des ordinateurs

    Authors: Anceau, François Etiemble, Daniel Circuits Intégrés Numériques et Analogiques (CIAN) et al.

    Contributors: Anceau, François Etiemble, Daniel Circuits Intégrés Numériques et Analogiques (CIAN) et al.

    Source: ISSN: 1776-0860 ; Techniques de l'Ingénieur ; https://hal.science/hal-01794102 ; 2010.

    Subject Terms: Architecture des ordinateurs, ACM: C.: Computer Systems Organization, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES, [INFO]Computer Science [cs], [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

    Availability: https://hal.science/hal-01794102

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  4. 4

    Evolution de l'architecture des ordinateurs

    Authors: Etiemble, Daniel Laboratoire de Recherche en Informatique (LRI) Université Paris-Sud - Paris 11 (UP11)-CentraleSupélec-Centre National de la Recherche Scientifique (CNRS)

    Contributors: Etiemble, Daniel Laboratoire de Recherche en Informatique (LRI) Université Paris-Sud - Paris 11 (UP11)-CentraleSupélec-Centre National de la Recherche Scientifique (CNRS)

    Source: ISSN: 1776-0860 ; Techniques de l'Ingénieur ; https://hal.science/hal-01793615 ; 2016.

    Subject Terms: mur de la chaleur, mur mémoire, technologie CMOS, GPU, multi-cœur, CPU, ACM: C.: Computer Systems Organization, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES, [INFO]Computer Science [cs], [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

    Availability: https://hal.science/hal-01793615

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  5. 5

    Exploring branch predictability limits with the MTAGE+SC predictor *

    Authors: Seznec, André Pushing Architecture and Compilation for Application Performance (PACAP) Inria Rennes – Bretagne Atlantique et al.

    Contributors: Seznec, André Pushing Architecture and Compilation for Application Performance (PACAP) Inria Rennes – Bretagne Atlantique et al.

    Source: 5th JILP Workshop on Computer Architecture Competitions (JWAC-5): Championship Branch Prediction (CBP-5)
    https://inria.hal.science/hal-01354251
    5th JILP Workshop on Computer Architecture Competitions (JWAC-5): Championship Branch Prediction (CBP-5), Jun 2016, Seoul, South Korea. pp.4
    http://www.jilp.org/cbp2016/

    Subject Terms: ACM: C.: Computer Systems Organization, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.1: Single Data Stream Architectures/C.1.1.1: Pipeline processors, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

    Subject Geographic: Seoul, South Korea

    Availability: https://inria.hal.science/hal-01354251
    https://inria.hal.science/hal-01354251v1/document
    https://inria.hal.science/hal-01354251v1/file/MutiTage-SC.pdf

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  6. 6

    Digital Systems Design

    Authors: Sameni, Reza Shiraz University (Shiraz University)

    Contributors: Sameni, Reza Shiraz University (Shiraz University)

    Source: https://hal.science/cel-01815308 ; Engineering school. Iran. 2018.

    Subject Terms: ACM: C.: Computer Systems Organization, ACM: B.: Hardware, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES, ACM: B.: Hardware/B.5: REGISTER-TRANSFER-LEVEL IMPLEMENTATION, ACM: B.: Hardware/B.5: REGISTER-TRANSFER-LEVEL IMPLEMENTATION/B.5.1: Design, [SPI.SIGNAL]Engineering Sciences [physics]/Signal and Image processing, [INFO.INFO-AO]Computer Science [cs]/Computer Arithmetic, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [INFO.INFO-LO]Computer Science [cs]/Logic in Computer Science [cs.LO]

    Availability: https://hal.science/cel-01815308
    https://hal.science/cel-01815308v1/document
    https://hal.science/cel-01815308v1/file/CourseSlides2018.pdf

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  7. 7

    TAGE-SC-L Branch Predictors Again

    Authors: Seznec, André Pushing Architecture and Compilation for Application Performance (PACAP) Inria Rennes – Bretagne Atlantique et al.

    Contributors: Seznec, André Pushing Architecture and Compilation for Application Performance (PACAP) Inria Rennes – Bretagne Atlantique et al.

    Source: 5th JILP Workshop on Computer Architecture Competitions (JWAC-5): Championship Branch Prediction (CBP-5)
    https://inria.hal.science/hal-01354253
    5th JILP Workshop on Computer Architecture Competitions (JWAC-5): Championship Branch Prediction (CBP-5), Jun 2016, Seoul, South Korea
    http://www.jilp.org/cbp2016/

    Subject Terms: ACM: C.: Computer Systems Organization, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.1: Single Data Stream Architectures/C.1.1.1: Pipeline processors, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

    Subject Geographic: Seoul, South Korea

    Availability: https://inria.hal.science/hal-01354253
    https://inria.hal.science/hal-01354253v1/document
    https://inria.hal.science/hal-01354253v1/file/CBP2016-TAGE-SC-L%20.pdf

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  8. 8

    Skewed Compressed Cache

    Authors: Sardashti, Somayeh Seznec, André Wood, David A. et al.

    Contributors: Sardashti, Somayeh Seznec, André Wood, David A. et al.

    Source: Proceeding of the 47th Annual IEEE/ACM International Symposium on Microarchitecture ; MICRO - 47th Annual IEEE/ACM International Symposium on Microarchitecture ; https://inria.hal.science/hal-01088050 ; MICRO - 47th Annual IEEE/ACM International Symposium on Microarchitecture, Dec 2014, Cambridge, United Kingdom

    Subject Terms: component, cache design, compression, performance, energy, ACM: C.: Computer Systems Organization, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

    Subject Geographic: Cambridge, United Kingdom

    Relation: info:eu-repo/grantAgreement//267175/EU/Defying Amdahl\'s Law/DAL

    Availability: https://inria.hal.science/hal-01088050
    https://inria.hal.science/hal-01088050/document
    https://inria.hal.science/hal-01088050/file/scc%20october%202%20%281%29.pdf

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  9. 9

    Yet Another Compressed Cache: a Low Cost Yet Effective Compressed Cache

    Authors: Sardashti, Somayeh Seznec, André Wood, David A. et al.

    Contributors: Sardashti, Somayeh Seznec, André Wood, David A. et al.

    Source: ISSN: 1544-3566.

    Subject Terms: ACM: C.: Computer Systems Organization, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.2: Multiple Data Stream Architectures (Multiprocessors), [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

    Relation: info:eu-repo/grantAgreement//267175/EU/Defying Amdahl\'s Law/DAL

    Availability: https://inria.hal.science/hal-01354248
    https://inria.hal.science/hal-01354248v1/document
    https://inria.hal.science/hal-01354248v1/file/yacc-taco-july%2022-final.pdf
    https://doi.org/10.1145/2976740

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  10. 10

    Reconstruction of switching thresholds in piecewise-affine models of genetic regulatory networks

    Authors: Drulhe, Samuel Ferrari-Trecate, Giancarlo de Jong, Hidde et al.

    Contributors: Drulhe, Samuel Ferrari-Trecate, Giancarlo de Jong, Hidde et al.

    Source: Hybrid Systems: Computation and Control, HSCC 2006 ; https://inria.hal.science/inria-00001225 ; Hybrid Systems: Computation and Control, HSCC 2006, Mar 2006, Santa Barbara, CA, USA, pp.184 - 199, ⟨10.1007/11730637⟩

    Subject Terms: Hybrid system, Genetic regulatory network, system identification, switching thresholds reconstruction, ACM: C.: Computer Systems Organization, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.3: Other Architecture Styles/C.1.3.5: Heterogeneous (hybrid) systems, ACM: I.: Computing Methodologies/I.6: SIMULATION AND MODELING/I.6.1: Simulation Theory/I.6.1.1: Systems theory, [SDV.OT]Life Sciences [q-bio]/Other [q-bio.OT]

    Availability: https://inria.hal.science/inria-00001225
    https://inria.hal.science/inria-00001225v1/document
    https://inria.hal.science/inria-00001225v1/file/LNCS_HSCC06.pdf
    https://doi.org/10.1007/11730637

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  11. 11

    TAGE-SC-L Branch Predictors

    Authors: Seznec, André Amdahl's Law is Forever (ALF) Inria Rennes – Bretagne Atlantique et al.

    Contributors: Seznec, André Amdahl's Law is Forever (ALF) Inria Rennes – Bretagne Atlantique et al.

    Source: Proceedings of the 4th Championship Branch Prediction ; JILP - Championship Branch Prediction ; https://inria.hal.science/hal-01086920 ; JILP - Championship Branch Prediction, Jun 2014, Minneapolis, United States ; http://www.jilp.org/cbp2014/

    Subject Terms: ACM: C.: Computer Systems Organization, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

    Subject Geographic: Minneapolis, United States

    Relation: info:eu-repo/grantAgreement//267175/EU/Defying Amdahl\'s Law/DAL

    Availability: https://inria.hal.science/hal-01086920
    https://inria.hal.science/hal-01086920/document
    https://inria.hal.science/hal-01086920/file/CBP4-TAGE-SC-L.pdf

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  12. 12

    Processeurs VLIW

    Authors: Etiemble, Daniel Laboratoire de Recherche en Informatique (LRI) Université Paris-Sud - Paris 11 (UP11)-CentraleSupélec-Centre National de la Recherche Scientifique (CNRS)

    Contributors: Etiemble, Daniel Laboratoire de Recherche en Informatique (LRI) Université Paris-Sud - Paris 11 (UP11)-CentraleSupélec-Centre National de la Recherche Scientifique (CNRS)

    Source: ISSN: 1776-0860 ; Techniques de l'Ingénieur ; https://hal.science/hal-01793958 ; 2015.

    Subject Terms: Parallélisme d'instructions, VLIW, pipeline logiciel, traitement du signal, ACM: C.: Computer Systems Organization, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES, [INFO]Computer Science [cs], [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

    Availability: https://hal.science/hal-01793958

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  13. 13

    Extensions SIMD des jeux d'instructions

    Authors: Etiemble, Daniel Lacassagne, Lionel Laboratoire de Recherche en Informatique (LRI) et al.

    Contributors: Etiemble, Daniel Lacassagne, Lionel Laboratoire de Recherche en Informatique (LRI) et al.

    Source: ISSN: 1776-0860 ; Techniques de l'Ingénieur ; https://hal.science/hal-01793974 ; Techniques de l'Ingénieur, 2015.

    Subject Terms: Instructions SIMD, SSE, intrinsèque, vectorisation, Altivec, Neon, AVX, ACM: C.: Computer Systems Organization, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES, [INFO]Computer Science [cs], [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

    Availability: https://hal.science/hal-01793974

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  14. 14

    Introduction au parallélisme et aux architectures parallèles

    Authors: Etiemble, Daniel Cappello, Franck Laboratoire de Recherche en Informatique (LRI) et al.

    Contributors: Etiemble, Daniel Cappello, Franck Laboratoire de Recherche en Informatique (LRI) et al.

    Source: ISSN: 1776-0860 ; Techniques de l'Ingénieur ; https://hal.science/hal-01793592 ; 2017.

    Subject Terms: pThreads, loi d'Amdhal, modèle Roofline, mémoires partagées et distribuées, parallélisme de données et de contrôle, modèles d'exécution, classification de Flynn, extensions SIMD, OpenMP, modèles de programmation, MPI, ACM: C.: Computer Systems Organization, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES, [INFO]Computer Science [cs], [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

    Availability: https://hal.science/hal-01793592

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  15. 15

    Jeux d'instructions des processeurs

    Authors: Etiemble, Daniel Laboratoire de Recherche en Informatique (LRI) Université Paris-Sud - Paris 11 (UP11)-CentraleSupélec-Centre National de la Recherche Scientifique (CNRS)

    Contributors: Etiemble, Daniel Laboratoire de Recherche en Informatique (LRI) Université Paris-Sud - Paris 11 (UP11)-CentraleSupélec-Centre National de la Recherche Scientifique (CNRS)

    Source: https://hal.science/hal-01794009 ; 2016.

    Subject Terms: CISC, format d'instructions, type d'instructions, RISC, interface matériel-logiciel, jeu d'instructions, ACM: C.: Computer Systems Organization, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES, [INFO]Computer Science [cs], [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

    Availability: https://hal.science/hal-01794009

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  16. 16

    Processeurs superscalaires 'flots de données'

    Authors: Anceau, François Etiemble, Daniel Circuits Intégrés Numériques et Analogiques (CIAN) et al.

    Contributors: Anceau, François Etiemble, Daniel Circuits Intégrés Numériques et Analogiques (CIAN) et al.

    Source: https://hal.science/hal-01793606 ; 2018.

    Subject Terms: superscalaire, parpallélisme d’instruction, flot de données, renommage de registres, stations de réservation, tampon de réordonnancement, ACM: C.: Computer Systems Organization, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES, [INFO]Computer Science [cs], [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

    Availability: https://hal.science/hal-01793606

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  17. 17

    Processeurs superscalaires multi-pipelines

    Authors: Etiemble, Daniel Anceau, François Laboratoire de Recherche en Informatique (LRI) et al.

    Contributors: Etiemble, Daniel Anceau, François Laboratoire de Recherche en Informatique (LRI) et al.

    Source: ISSN: 1776-0860 ; Techniques de l'Ingénieur ; https://hal.science/hal-01793667 ; 2015.

    Subject Terms: superscalaire, multi-pipeline, lancement des instructions, parallélisme d'instructions, ACM: C.: Computer Systems Organization, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES, [INFO]Computer Science [cs], [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

    Availability: https://hal.science/hal-01793667

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  18. 18

    Processeurs : exécution pipeline des instructions

    Authors: Etiemble, Daniel Anceau, François Laboratoire de Recherche en Informatique (LRI) et al.

    Contributors: Etiemble, Daniel Anceau, François Laboratoire de Recherche en Informatique (LRI) et al.

    Source: ISSN: 1776-0860 ; Techniques de l'Ingénieur ; https://hal.science/hal-01793994 ; 2013.

    Subject Terms: Pipeline, superpipeline, renommage de registres, ACM: C.: Computer Systems Organization, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES, [INFO]Computer Science [cs], [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

    Availability: https://hal.science/hal-01793994

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  19. 19

    Hiérarchie mémoire : les caches

    Authors: Etiemble, Daniel Anceau, François Laboratoire de Recherche en Informatique (LRI) et al.

    Contributors: Etiemble, Daniel Anceau, François Laboratoire de Recherche en Informatique (LRI) et al.

    Source: ISSN: 1776-0860 ; Techniques de l'Ingénieur ; https://hal.science/hal-01794025 ; 2012.

    Subject Terms: fonctionnement des caches, cohérence des caches, caches multiprocesseurs et multicoeurs, optimisations logicielles, ACM: C.: Computer Systems Organization, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES, [INFO]Computer Science [cs], [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

    Availability: https://hal.science/hal-01794025

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  20. 20

    Hiérarchie mémoire : mémoire virtuelle

    Authors: Etiemble, Daniel Anceau, François Laboratoire de Recherche en Informatique (LRI) et al.

    Contributors: Etiemble, Daniel Anceau, François Laboratoire de Recherche en Informatique (LRI) et al.

    Source: ISSN: 1776-0860 ; Techniques de l'Ingénieur ; https://hal.science/hal-01794041 ; 2014.

    Subject Terms: traduction d'adresse, systèmes d'exploitation, algorithmes de remplacement, TLB, table des pages, pagination, segmentation, adresse logique, adresse virtuelle, mémoire physique, mémoire virtuelle, ACM: C.: Computer Systems Organization, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES, [INFO]Computer Science [cs], [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

    Availability: https://hal.science/hal-01794041

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