Search Results - acm: c.: computer systems organization/c.1: processor architectural

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  1. 1

    Micro-architectural simulation of embedded core heterogeneity with gem5 and McPAT

    Authors: Endo, F.A. Couroussé, Damien Charles, H.-P. et al.

    Contributors: Endo, F.A. Couroussé, Damien Charles, H.-P. et al.

    Source: RAPIDO '15 Proceedings of the 2015 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools ; https://cea.hal.science/cea-01818887 ; RAPIDO '15 Proceedings of the 2015 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools, Jan 2015, Amsterdam, Netherlands. ⟨10.1145/2693433.2693440⟩

    Subject Terms: ACM: I.: Computing Methodologies/I.6: SIMULATION AND MODELING/I.6.7: Simulation Support Systems, ACM: I.: Computing Methodologies/I.6: SIMULATION AND MODELING/I.6.7: Simulation Support Systems/I.6.7.0: Environments, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.1: Single Data Stream Architectures, [INFO]Computer Science [cs]

    Subject Geographic: Amsterdam, Netherlands

    Availability: https://cea.hal.science/cea-01818887
    https://doi.org/10.1145/2693433.2693440

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  2. 2

    Design and Implementation of a MicroBlaze-Based Warp Processor.

    Authors: LYSECKY, ROMAN VAHID, FRANK

    Source: ACM Transactions on Embedded Computing Systems; Apr2009, Vol. 8 Issue 3, p22-22-22, 22p, 4 Diagrams, 2 Charts, 6 Graphs

    Subject Terms: SYSTEMS design, NETWORK processors, FIELD programmable gate arrays, GATE array circuits, ELECTRIC power consumption, COMPUTER organization, EMBEDDED computer systems

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  3. 3

    Hardware Architectural Support for Control Systems and Sensor Processing.

    Authors: VYAS, SUDHANSHU GUPTE, ADWAIT GILL, CHRISTOPHER D. et al.

    Source: ACM Transactions on Embedded Computing Systems; Sep2013, Vol. 13 Issue 2, p1-25, 25p

    Subject Terms: COMPUTER input-output equipment, COMPUTER architecture, AUTOMATIC control systems, SENSOR networks, DIGITAL signal processing, ALGORITHMS, PID controllers

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  4. 4

    Towards a New Processor Architecture. ; Vers une nouvelle Architecture de Processeurs

    Authors: Vincent, Pierre Landru, Jacques Ecole nationale supérieure Mines-Télécom Lille Douai (IMT Nord Europe) et al.

    Contributors: Vincent, Pierre Landru, Jacques Ecole nationale supérieure Mines-Télécom Lille Douai (IMT Nord Europe) et al.

    Source: https://hal.science/hal-05117313 ; 2025.

    Subject Terms: silicon, parallel, serial, RISC, photonics, computer, optronics, optics, processor, fiber, laser, digital, silicium, parallèle, série, processeur, photonique, ordinateur, optronique, optique, numérique, fibre, ACM: B.: Hardware, ACM: C.: Computer Systems Organization, [INFO]Computer Science [cs], [PHYS]Physics [physics]

    Availability: https://hal.science/hal-05117313
    https://hal.science/hal-05117313v2/document
    https://hal.science/hal-05117313v2/file/frParalSerieRiscV1.pdf

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  5. 5

    Novel Architecture of Smart FFT Processor

    Authors: Teymourzadeh, Rozita University of California San Francisco (UC San Francisco) University of California (UC)

    Contributors: Teymourzadeh, Rozita University of California San Francisco (UC San Francisco) University of California (UC)

    Source: https://hal.archives-ouvertes.fr/hal-01802071 ; 2014.

    Subject Terms: FFT, Digital Design, Processor, VLSI, Novel Architecture, Radix, Harmonic, ACM: D.: Software, ACM: B.: Hardware, ACM: C.: Computer Systems Organization, ACM: I.: Computing Methodologies, ACM: B.: Hardware/B.6: LOGIC DESIGN, ACM: B.: Hardware/B.5: REGISTER-TRANSFER-LEVEL IMPLEMENTATION, ACM: D.: Software/D.3: PROGRAMMING LANGUAGES, [INFO]Computer Science [cs], [INFO.INFO-AO]Computer Science [cs]/Computer Arithmetic, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [INFO.INFO-ES]Computer Science [cs]/Embedded Systems, [INFO.INFO-TS]Computer Science [cs]/Signal and Image Processing, [SPI]Engineering Sciences [physics], [SPI.SIGNAL]Engineering Sciences [physics]/Signal and Image processing, [SPI.TRON]Engineering Sciences [physics]/Electronics

    Relation: hal-01802071; https://hal.archives-ouvertes.fr/hal-01802071; https://hal.archives-ouvertes.fr/hal-01802071/document; https://hal.archives-ouvertes.fr/hal-01802071/file/Novel%20Architecture%20of%20Smart%20FFT%20Processor_Draft.pdf

    Availability: https://hal.archives-ouvertes.fr/hal-01802071
    https://hal.archives-ouvertes.fr/hal-01802071/document
    https://hal.archives-ouvertes.fr/hal-01802071/file/Novel%20Architecture%20of%20Smart%20FFT%20Processor_Draft.pdf

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  6. 6

    Processor Design for Soft Errors: Challenges and State of the Art.

    Authors: LI, TUO AMBROSE, JUDE ANGELO RAGEL, ROSHAN et al.

    Source: ACM Computing Surveys; Dec2016, Vol. 49 Issue 3, p1-44, 44p, 3 Diagrams, 4 Charts, 1 Graph

    Subject Terms: SOFT errors, MICROPROCESSOR design & construction, ERROR rates, COMPUTER architecture, DATA, ERROR detection (Information theory)

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  7. 7

    Digital Systems Design

    Authors: Sameni, Reza Shiraz University (Shiraz University)

    Contributors: Sameni, Reza Shiraz University (Shiraz University)

    Source: https://hal.science/cel-01815308 ; Engineering school. Iran. 2018.

    Subject Terms: ACM: C.: Computer Systems Organization, ACM: B.: Hardware, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES, ACM: B.: Hardware/B.5: REGISTER-TRANSFER-LEVEL IMPLEMENTATION, ACM: B.: Hardware/B.5: REGISTER-TRANSFER-LEVEL IMPLEMENTATION/B.5.1: Design, [SPI.SIGNAL]Engineering Sciences [physics]/Signal and Image processing, [INFO.INFO-AO]Computer Science [cs]/Computer Arithmetic, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [INFO.INFO-LO]Computer Science [cs]/Logic in Computer Science [cs.LO]

    Availability: https://hal.science/cel-01815308
    https://hal.science/cel-01815308v1/document
    https://hal.science/cel-01815308v1/file/CourseSlides2018.pdf

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  8. 8

    Probabilistic System-on-a-Chip Architectures

    Authors: Lakshmi N. Chakrapani Pinar Korkmaz Bilge E. S. Akgul et al.

    Contributors: Lakshmi N. Chakrapani Pinar Korkmaz Bilge E. S. Akgul et al.

    Source: http://www.crest.gatech.edu/palempbitscurrent/a29-chakrapani.pdf.

    Subject Terms: Categories and Subject Descriptors, C.3 [Computer Systems Organization, Special-Purpose and Application-Based Systems, C.1.3 [Processor Architectures, Other Architecture Styles General Terms, Performance, Design, Reliability Additional Key Words and Phrases, Embedded systems, probabilistic computing ACM Reference Format

    File Description: application/pdf

    Relation: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.91.430

    Availability: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.91.430
    http://www.crest.gatech.edu/palempbitscurrent/a29-chakrapani.pdf

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  9. 9

    A simultaneous multithreading processor architecture with predictable timing behavior.

    Authors: Siqueira, Hadley Magno Kreutz, Marcio Eduardo

    Source: Design Automation for Embedded Systems; Mar2020, Vol. 24 Issue 1, p45-62, 18p

    Subject Terms: SIMULTANEOUS multithreading processors, COMPUTER systems, CYBER physical systems, DETERMINISTIC algorithms, ARCHITECTURAL design, SYSTEMS engineering

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  10. 10

    Synchronous byzantine agreement with nearly a cubic number of communication bits

    Authors: Kowalski, Dariusz R. Mostefaoui, Achour Department of Computer Science Liverpool et al.

    Contributors: Kowalski, Dariusz R. Mostefaoui, Achour Department of Computer Science Liverpool et al.

    Source: ACM symposium on Principles of distributed computing (PODC'13) ; https://hal.science/hal-01151136 ; ACM symposium on Principles of distributed computing (PODC'13), Jul 2013, New-York, United States. pp.84-91, ⟨10.1145/2484239.2484271⟩

    Subject Terms: Agreement problem, Synchronous distributed system, Byzantine process, Message-passing model, Round-based protocol, EIG, Consensus, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.4: Parallel Architectures/C.1.4.0: Distributed architectures, ACM: C.: Computer Systems Organization/C.2: COMPUTER-COMMUNICATION NETWORKS/C.2.4: Distributed Systems, ACM: D.: Software/D.4: OPERATING SYSTEMS/D.4.7: Organization and Design/D.4.7.1: Distributed systems, ACM: D.: Software/D.4: OPERATING SYSTEMS/D.4.5: Reliability/D.4.5.2: Fault-tolerance, ACM: D.: Software/D.4: OPERATING SYSTEMS/D.4.1: Process Management/D.4.1.0: Concurrency, ACM: D.: Software/D.4: OPERATING SYSTEMS/D.4.1: Process Management/D.4.1.5: Synchronization, [INFO]Computer Science [cs], [INFO.INFO-DC]Computer Science [cs]/Distributed, Parallel, and Cluster Computing [cs.DC], [INFO.INFO-DS]Computer Science [cs]/Data Structures and Algorithms [cs.DS]

    Subject Geographic: New-York, United States

    Availability: https://hal.science/hal-01151136
    https://hal.science/hal-01151136v1/document
    https://hal.science/hal-01151136v1/file/podc%20final.pdf
    https://doi.org/10.1145/2484239.2484271

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  11. 11

    HARS: A Hardware-Assisted Runtime Software for embedded many-core architectures

    Authors: Lhuillier, Y. Ojail, M. Guerre, A. et al.

    Contributors: Lhuillier, Y. Ojail, M. Guerre, A. et al.

    Source: ISSN: 1539-9087.

    Subject Terms: B.5.0 [Register-Transfer-Level Implementation]: General, ACM: D.: Software/D.4: OPERATING SYSTEMS/D.4.7: Organization and Design/D.4.7.4: Real-time systems and embedded systems, ACM: D.: Software/D.4: OPERATING SYSTEMS/D.4.1: Process Management, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.4: Parallel Architectures, ACM: B.: Hardware/B.5: REGISTER-TRANSFER-LEVEL IMPLEMENTATION, [INFO]Computer Science [cs]

    Availability: https://cea.hal.science/cea-01818892
    https://doi.org/10.1145/2517311

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  12. 12

    Skewed Compressed Cache

    Authors: Sardashti, Somayeh Seznec, André Wood, David A. et al.

    Contributors: Sardashti, Somayeh Seznec, André Wood, David A. et al.

    Source: Proceeding of the 47th Annual IEEE/ACM International Symposium on Microarchitecture ; MICRO - 47th Annual IEEE/ACM International Symposium on Microarchitecture ; https://inria.hal.science/hal-01088050 ; MICRO - 47th Annual IEEE/ACM International Symposium on Microarchitecture, Dec 2014, Cambridge, United Kingdom

    Subject Terms: component, cache design, compression, performance, energy, ACM: C.: Computer Systems Organization, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

    Subject Geographic: Cambridge, United Kingdom

    Relation: info:eu-repo/grantAgreement//267175/EU/Defying Amdahl\'s Law/DAL

    Availability: https://inria.hal.science/hal-01088050
    https://inria.hal.science/hal-01088050/document
    https://inria.hal.science/hal-01088050/file/scc%20october%202%20%281%29.pdf

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  13. 13

    Exploring branch predictability limits with the MTAGE+SC predictor *

    Authors: Seznec, André Pushing Architecture and Compilation for Application Performance (PACAP) Inria Rennes – Bretagne Atlantique et al.

    Contributors: Seznec, André Pushing Architecture and Compilation for Application Performance (PACAP) Inria Rennes – Bretagne Atlantique et al.

    Source: 5th JILP Workshop on Computer Architecture Competitions (JWAC-5): Championship Branch Prediction (CBP-5)
    https://inria.hal.science/hal-01354251
    5th JILP Workshop on Computer Architecture Competitions (JWAC-5): Championship Branch Prediction (CBP-5), Jun 2016, Seoul, South Korea. pp.4
    http://www.jilp.org/cbp2016/

    Subject Terms: ACM: C.: Computer Systems Organization, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.1: Single Data Stream Architectures/C.1.1.1: Pipeline processors, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

    Subject Geographic: Seoul, South Korea

    Availability: https://inria.hal.science/hal-01354251
    https://inria.hal.science/hal-01354251v1/document
    https://inria.hal.science/hal-01354251v1/file/MutiTage-SC.pdf

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  14. 14

    Reconstruction of switching thresholds in piecewise-affine models of genetic regulatory networks

    Authors: Drulhe, Samuel Ferrari-Trecate, Giancarlo de Jong, Hidde et al.

    Contributors: Drulhe, Samuel Ferrari-Trecate, Giancarlo de Jong, Hidde et al.

    Source: Hybrid Systems: Computation and Control, HSCC 2006 ; https://inria.hal.science/inria-00001225 ; Hybrid Systems: Computation and Control, HSCC 2006, Mar 2006, Santa Barbara, CA, USA, pp.184 - 199, ⟨10.1007/11730637⟩

    Subject Terms: Hybrid system, Genetic regulatory network, system identification, switching thresholds reconstruction, ACM: C.: Computer Systems Organization, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.3: Other Architecture Styles/C.1.3.5: Heterogeneous (hybrid) systems, ACM: I.: Computing Methodologies/I.6: SIMULATION AND MODELING/I.6.1: Simulation Theory/I.6.1.1: Systems theory, [SDV.OT]Life Sciences [q-bio]/Other [q-bio.OT]

    Availability: https://inria.hal.science/inria-00001225
    https://inria.hal.science/inria-00001225v1/document
    https://inria.hal.science/inria-00001225v1/file/LNCS_HSCC06.pdf
    https://doi.org/10.1007/11730637

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  15. 15

    TAGE-SC-L Branch Predictors Again

    Authors: Seznec, André Pushing Architecture and Compilation for Application Performance (PACAP) Inria Rennes – Bretagne Atlantique et al.

    Contributors: Seznec, André Pushing Architecture and Compilation for Application Performance (PACAP) Inria Rennes – Bretagne Atlantique et al.

    Source: 5th JILP Workshop on Computer Architecture Competitions (JWAC-5): Championship Branch Prediction (CBP-5)
    https://inria.hal.science/hal-01354253
    5th JILP Workshop on Computer Architecture Competitions (JWAC-5): Championship Branch Prediction (CBP-5), Jun 2016, Seoul, South Korea
    http://www.jilp.org/cbp2016/

    Subject Terms: ACM: C.: Computer Systems Organization, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.1: Single Data Stream Architectures/C.1.1.1: Pipeline processors, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

    Subject Geographic: Seoul, South Korea

    Availability: https://inria.hal.science/hal-01354253
    https://inria.hal.science/hal-01354253v1/document
    https://inria.hal.science/hal-01354253v1/file/CBP2016-TAGE-SC-L%20.pdf

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  16. 16

    Embedded Runtime for Reconfigurable Dataflow Graphs on Manycore Architectures

    Authors: Miomandre, Hugo Hascoët, Julien Desnos, Karol et al.

    Contributors: Miomandre, Hugo Hascoët, Julien Desnos, Karol et al.

    Source: PARMA-DITAM ; https://hal.science/hal-01704702 ; PARMA-DITAM, Jan 2018, Manchester, United Kingdom. ⟨10.1145/3183767.3183780⟩

    Subject Terms: ACM: C.: Computer Systems Organization, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.4: Parallel Architectures, [INFO.INFO-ES]Computer Science [cs]/Embedded Systems

    Subject Geographic: Manchester, United Kingdom

    Availability: https://hal.science/hal-01704702
    https://hal.science/hal-01704702v1/document
    https://hal.science/hal-01704702v1/file/parma-ditam18.pdf
    https://doi.org/10.1145/3183767.3183780

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  17. 17

    Yet Another Compressed Cache: a Low Cost Yet Effective Compressed Cache

    Authors: Sardashti, Somayeh Seznec, André Wood, David A. et al.

    Contributors: Sardashti, Somayeh Seznec, André Wood, David A. et al.

    Source: ISSN: 1544-3566.

    Subject Terms: ACM: C.: Computer Systems Organization, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.2: Multiple Data Stream Architectures (Multiprocessors), [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

    Relation: info:eu-repo/grantAgreement//267175/EU/Defying Amdahl\'s Law/DAL

    Availability: https://inria.hal.science/hal-01354248
    https://inria.hal.science/hal-01354248v1/document
    https://inria.hal.science/hal-01354248v1/file/yacc-taco-july%2022-final.pdf
    https://doi.org/10.1145/2976740

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  18. 18

    ASPLOS-IV proceedings : fourth international conference on architectural support for programming languages and operating systems : Santa Clara, California, April 8-11, 1991 / spons. by ACM in coop. with the IEEE Computer Society.

    Authors: International Conference on Architectural Support for Programming Languages and Operating Systems (4 ; 1991 ; Santa Clara). Association for Computing Machinery. Institute of Electrical and Electronics Engineers. Computer Society.

    Contributors: International Conference on Architectural Support for Programming Languages and Operating Systems (4 ; 1991 ; Santa Clara). Association for Computing Machinery. Institute of Electrical and Electronics Engineers. Computer Society.

    Source: Bibliogr. przy rozdz.
    Index.

    Subject Terms: Sieci komputerowe, Komputery -- konferencje

    Access URL: http://katalog.nukat.edu.pl/lib/item?id=chamo:1759164&theme=nukat

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  19. 19

    Extensions SIMD des jeux d'instructions

    Authors: Etiemble, Daniel Lacassagne, Lionel Laboratoire de Recherche en Informatique (LRI) et al.

    Contributors: Etiemble, Daniel Lacassagne, Lionel Laboratoire de Recherche en Informatique (LRI) et al.

    Source: ISSN: 1776-0860 ; Techniques de l'Ingénieur ; https://hal.science/hal-01793974 ; Techniques de l'Ingénieur, 2015.

    Subject Terms: Instructions SIMD, SSE, intrinsèque, vectorisation, Altivec, Neon, AVX, ACM: C.: Computer Systems Organization, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES, [INFO]Computer Science [cs], [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

    Availability: https://hal.science/hal-01793974

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  20. 20

    Introduction au parallélisme et aux architectures parallèles

    Authors: Etiemble, Daniel Cappello, Franck Laboratoire de Recherche en Informatique (LRI) et al.

    Contributors: Etiemble, Daniel Cappello, Franck Laboratoire de Recherche en Informatique (LRI) et al.

    Source: ISSN: 1776-0860 ; Techniques de l'Ingénieur ; https://hal.science/hal-01793592 ; 2017.

    Subject Terms: pThreads, loi d'Amdhal, modèle Roofline, mémoires partagées et distribuées, parallélisme de données et de contrôle, modèles d'exécution, classification de Flynn, extensions SIMD, OpenMP, modèles de programmation, MPI, ACM: C.: Computer Systems Organization, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES, [INFO]Computer Science [cs], [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

    Availability: https://hal.science/hal-01793592

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