Search Results - acm: c.: computer systems organization/c.1: processor architectural/c.1.4: parallel architecture*

Towards a New Processor Architecture. ; Vers une nouvelle Architecture de Processeurs

Authors: Vincent, Pierre Landru, Jacques Ecole nationale supérieure Mines-Télécom Lille Douai (IMT Nord Europe) et al.

Contributors: Vincent, Pierre Landru, Jacques Ecole nationale supérieure Mines-Télécom Lille Douai (IMT Nord Europe) et al.

Source: https://hal.science/hal-05117313 ; 2025.

Subject Terms: silicon, parallel, serial, RISC, photonics, computer, optronics, optics, processor, fiber, laser, digital, silicium, parallèle, série, processeur, photonique, ordinateur, optronique, optique, numérique, fibre, ACM: B.: Hardware, ACM: C.: Computer Systems Organization, [INFO]Computer Science [cs], [PHYS]Physics [physics]

Availability: https://hal.science/hal-05117313
https://hal.science/hal-05117313v2/document
https://hal.science/hal-05117313v2/file/frParalSerieRiscV1.pdf

Hardware Architectural Support for Control Systems and Sensor Processing.

Authors: VYAS, SUDHANSHU GUPTE, ADWAIT GILL, CHRISTOPHER D. et al.

Source: ACM Transactions on Embedded Computing Systems; Sep2013, Vol. 13 Issue 2, p1-25, 25p

Subject Terms: COMPUTER input-output equipment, COMPUTER architecture, AUTOMATIC control systems, SENSOR networks, DIGITAL signal processing, ALGORITHMS, PID controllers

A simultaneous multithreading processor architecture with predictable timing behavior.

Authors: Siqueira, Hadley Magno Kreutz, Marcio Eduardo

Source: Design Automation for Embedded Systems; Mar2020, Vol. 24 Issue 1, p45-62, 18p

Subject Terms: SIMULTANEOUS multithreading processors, COMPUTER systems, CYBER physical systems, DETERMINISTIC algorithms, ARCHITECTURAL design, SYSTEMS engineering

Processor Design for Soft Errors: Challenges and State of the Art.

Authors: LI, TUO AMBROSE, JUDE ANGELO RAGEL, ROSHAN et al.

Source: ACM Computing Surveys; Dec2016, Vol. 49 Issue 3, p1-44, 44p, 3 Diagrams, 4 Charts, 1 Graph

Subject Terms: SOFT errors, MICROPROCESSOR design & construction, ERROR rates, COMPUTER architecture, DATA, ERROR detection (Information theory)

PARALLEL ALGORITHMS FOR THE EXECUTION OF RELATIONAL DATABASE OPERATIONS REVISITED ON GRIDS.

Authors: Mach, Werner Schikuta, Erich

Source: International Journal of High Performance Computing Applications; May2009, Vol. 23 Issue 2, p152-170, 19p, 4 Diagrams, 4 Charts, 19 Graphs

Subject Terms: PARALLEL algorithms, GRID computing, RELATIONAL databases, DATA transmission systems, GRIDS (Cartography), COMPUTER architecture, GEOGRAPHICAL positions, DATABASE selection, DATABASES

A Survey on Memory-centric Computer Architectures.

Authors: GEBREGIORGIS, ANTENEH HOANG ANH DU NGUYEN JINTAO YU et al.

Source: ACM Journal on Emerging Technologies in Computing Systems; Oct2022, Vol. 18 Issue 4, p1-50, 50p

Subject Terms: COMPUTER architecture, INTERNET surveys, PARALLEL processing

An Efficient Data-Distribution Mechanism in a Processor-In-Memory (PIM) Architecture Applied to Motion Estimation.

Authors: Jung-Yup Kang Gupta, Sandeep Gaudiot, Jean-Luc

Source: IEEE Transactions on Computers; Mar2008, Vol. 57 Issue 3, p375-388, 14p, 1 Black and White Photograph, 1 Diagram, 1 Chart

Subject Terms: BANDWIDTHS, COMPUTER storage devices, MACRO processors, DATA transmission systems, MPEG (Video coding standard), DIGITAL video standards, INTEGRATED circuits, ALGORITHMS, DIGITAL communications, SPECTRUM allocation

Embedded Runtime for Reconfigurable Dataflow Graphs on Manycore Architectures

Authors: Miomandre, Hugo Hascoët, Julien Desnos, Karol et al.

Contributors: Miomandre, Hugo Hascoët, Julien Desnos, Karol et al.

Source: PARMA-DITAM ; https://hal.science/hal-01704702 ; PARMA-DITAM, Jan 2018, Manchester, United Kingdom. ⟨10.1145/3183767.3183780⟩

Subject Terms: ACM: C.: Computer Systems Organization, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.4: Parallel Architectures, [INFO.INFO-ES]Computer Science [cs]/Embedded Systems

Subject Geographic: Manchester, United Kingdom

Availability: https://hal.science/hal-01704702
https://hal.science/hal-01704702v1/document
https://hal.science/hal-01704702v1/file/parma-ditam18.pdf
https://doi.org/10.1145/3183767.3183780

Automatic Prefetch and Modulo Scheduling Transformations for the Cell BE Architecture.

Authors: Vujic, Nikola González, Marc Martorell, Xavier et al.

Source: IEEE Transactions on Parallel & Distributed Systems; Apr2010, Vol. 21 Issue 4, p494-505, 12p

Subject Terms: COMPUTER programming, MATHEMATICAL analysis, ALGORITHMS, ELECTRONIC systems, ARCHITECTURAL designs

Architectural differences of efficient sequential and parallel computers

Authors: Forsell, Martti

Source: Forsell, M 2002, 'Architectural differences of efficient sequential and parallel computers', Journal of Systems Architecture, vol. 47, no. 13, pp. 1017-1041. https://doi.org/10.1016/S1383-7621(02)00064-4

Subject Terms: Computer architecture, Sequential computation, Parallel computation, Processor architecture, Pipeline organization

Relation: info:eu-repo/semantics/altIdentifier/pissn/1383-7621; info:eu-repo/semantics/altIdentifier/eissn/1873-6165

Availability: https://cris.vtt.fi/en/publications/b0e3797f-7887-4232-b4aa-7ef852d4d8ed
https://doi.org/10.1016/S1383-7621(02)00064-4
https://www.scopus.com/pages/publications/0036642082

Prefabrication and Postfabrication Architecture Exploration for Partially Reconfigurable VLIW Processors.

Authors: Chattopadhyay, A. Ishebabi, H. Chen, X. et al.

Source: ACM Transactions on Embedded Computing Systems; Jul2008, Vol. 7 Issue 4, p40-40:31, 31p, 8 Diagrams, 13 Charts, 1 Graph

Subject Terms: APPLICATION-specific instruction-set processors, MICROPROCESSORS, ADAPTIVE computing systems, COMPUTER architecture, DATA pipelining

A Survey of Machine Learning for Computer Architecture and Systems.

Authors: NAN WU YUAN XIE

Source: ACM Computing Surveys; Apr2023, Vol. 55 Issue 3, p1-39, 39p

Subject Terms: COMPUTER architecture, COMPUTER systems, MACHINE learning, SYSTEMS design, COMPILERS (Computer programs), SERVER farms (Computer network management), ARCHITECTURAL design

Lightweight Chip Multi-Threading (LCMT): Maximizing Fine-Grained Parallelism On-Chip.

Authors: Li, Sheng Kuntz, Shannon Brockman, Jay et al.

Source: IEEE Transactions on Parallel & Distributed Systems; Jul2011, Vol. 22 Issue 7, p1178-1191, 0p

Subject Terms: INTEGRATED circuits, SIMULTANEOUS multithreading processors, PARALLEL algorithms, SIMULATION methods & models, PERFORMANCE evaluation, MULTICORE processors, SYNCHRONIZATION, COMPUTER software, COMPUTER architecture

Autonomous driving systems hardware and software architecture exploration: optimizing latency and cost under safety constraints.

Authors: Collin, Anne Siddiqi, Afreen Imanishi, Yuto et al.

Source: Systems Engineering; May2020, Vol. 23 Issue 3, p327-337, 11p

Subject Terms: SYSTEMS software, SOFTWARE architecture, COMPUTER vision, ARCHITECTURAL design, COST

Exploiting Timing Error Resilience in Processor Architecture.

Authors: SARTORI, JOHN KUMAR, RAKESH

Source: ACM Transactions on Embedded Computing Systems; May2013 Supplement 2, Vol. 12, p1-25, 25p

Subject Terms: COMPLEMENTARY metal oxide semiconductor design & construction, MACRO processors, COMPUTER architecture, ERROR rates, ERRORS, MOORE'S law, INDUSTRIAL costs

Dual-execution mode processor architecture.

Authors: Akanda, Md. Abderazek, Ben Sowa, Masahiro

Source: Journal of Supercomputing; May2008, Vol. 44 Issue 2, p103-125, 23p, 13 Diagrams, 4 Charts

Subject Terms: EMBEDDED computer systems, ARCHITECTURAL designs, COMPUTER programming, COMPUTER input-output equipment, BASES (Architecture), ARCHITECTURE, PROTOTYPES, FIELD programmable gate arrays

Top Picks in Computer Architecture from Conferences in 2018.

Authors: Dwarkadas, Sandhya

Source: IEEE Micro; May-Jun2019, Vol. 39 Issue 3, p6-10, 5p

Subject Terms: COMPUTER architecture, ORDER picking systems, MESSAGE authentication codes, PARALLEL computers, RANDOM access memory

Performance effects of architectural complexity in the intel 432

Authors: Robert P. Colwell Multiflow Computer Inc Edward F. Gehringer et al.

Contributors: Robert P. Colwell Multiflow Computer Inc Edward F. Gehringer et al.

Source: http://www.princeton.edu/~rblee/ELE572Papers/Fall04Readings/I432.pdf.

Subject Terms: parallel processors, C.1.3 [Processor Architectures, Other Architecture Styles-capability archi- tectures, high-level language architectures, stack-oriented processors, C.4 [Computer Systems Organization, Performance of Systems-design studies, D.3.2 [Programming Languages, Lan- guage Classifications, D.3.4 [Programming Languages, Processors-compikrs General Terms, Design, Measurement, Performance, Security Additional Key Words and Phrases, Ada, address translation, caches, capabilities, CISC, Intel 432, object-based, object-oriented, procedure calls

File Description: application/pdf

Relation: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.140.5969; http://www.princeton.edu/~rblee/ELE572Papers/Fall04Readings/I432.pdf

Availability: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.140.5969
http://www.princeton.edu/~rblee/ELE572Papers/Fall04Readings/I432.pdf

On-Chip Memory Architecture Exploration Framework for DSP Processor-Based Embedded System on Chip.

Authors: Kumar, T. S. Rajesh Govindarajan, R. Ravikumar, C. P.

Source: ACM Transactions on Embedded Computing Systems; Mar2012, Vol. 11 Issue 1, p1-25, 25p

Subject Terms: SYSTEMS on a chip, COMPUTER storage devices, COMPUTER architecture, DIGITAL signal processing, EMBEDDED computer systems, PERFORMANCE evaluation, PERSONAL computers

Novel Architecture of Smart FFT Processor

Authors: Teymourzadeh, Rozita University of California San Francisco (UC San Francisco) University of California (UC)

Contributors: Teymourzadeh, Rozita University of California San Francisco (UC San Francisco) University of California (UC)

Source: https://hal.archives-ouvertes.fr/hal-01802071 ; 2014.

Subject Terms: FFT, Digital Design, Processor, VLSI, Novel Architecture, Radix, Harmonic, ACM: D.: Software, ACM: B.: Hardware, ACM: C.: Computer Systems Organization, ACM: I.: Computing Methodologies, ACM: B.: Hardware/B.6: LOGIC DESIGN, ACM: B.: Hardware/B.5: REGISTER-TRANSFER-LEVEL IMPLEMENTATION, ACM: D.: Software/D.3: PROGRAMMING LANGUAGES, [INFO]Computer Science [cs], [INFO.INFO-AO]Computer Science [cs]/Computer Arithmetic, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [INFO.INFO-ES]Computer Science [cs]/Embedded Systems, [INFO.INFO-TS]Computer Science [cs]/Signal and Image Processing, [SPI]Engineering Sciences [physics], [SPI.SIGNAL]Engineering Sciences [physics]/Signal and Image processing, [SPI.TRON]Engineering Sciences [physics]/Electronics

Relation: hal-01802071; https://hal.archives-ouvertes.fr/hal-01802071; https://hal.archives-ouvertes.fr/hal-01802071/document; https://hal.archives-ouvertes.fr/hal-01802071/file/Novel%20Architecture%20of%20Smart%20FFT%20Processor_Draft.pdf

Availability: https://hal.archives-ouvertes.fr/hal-01802071
https://hal.archives-ouvertes.fr/hal-01802071/document
https://hal.archives-ouvertes.fr/hal-01802071/file/Novel%20Architecture%20of%20Smart%20FFT%20Processor_Draft.pdf