Výsledky vyhledávání - acm: c.: computer systems organization/c.1: processor (architectural* OR architektury*)

Towards a Time-predictable Dual-Issue Microprocessor: The Patmos Approach

Autoři: Schoeberl, Martin Schleuniger, Pascal Puffitsch, Wolfgang a další

Přispěvatelé: Schoeberl, Martin Schleuniger, Pascal Puffitsch, Wolfgang a další

Zdroj: Bringing Theory to Practice: Predictability and Performance in Embedded Systems ; https://inria.hal.science/inria-00585320 ; Bringing Theory to Practice: Predictability and Performance in Embedded Systems, Philipp Lucas, Lothar Thiele, Benoit Triquet, Theo Ungerer, and Reinhard Wilhelm, Mar 2011, Grenoble, France. pp.11-21, ⟨10.4230/OASIcs.PPES.2011.11⟩ ; http://drops.dagstuhl.de/opus/volltexte/2011/3077/pdf/2.pdf

Témata: WCET-aware Compilation, WCET Analysis, Time-predictable Architecture, ACM: C.: Computer Systems Organization/C.3: SPECIAL-PURPOSE AND APPLICATION-BASED SYSTEMS/C.3.2: Real-time and embedded systems, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.1: Single Data Stream Architectures/C.1.1.2: RISC/CISC, VLIW architectures, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [INFO.INFO-ES]Computer Science [cs]/Embedded Systems, [INFO.INFO-PF]Computer Science [cs]/Performance [cs.PF]

Geografické téma: Grenoble, France

Dostupnost: https://inria.hal.science/inria-00585320
https://inria.hal.science/inria-00585320v1/document
https://inria.hal.science/inria-00585320v1/file/schoeberl-ppes11.pdf
https://doi.org/10.4230/OASIcs.PPES.2011.11

Towards a Time-predictable Dual-Issue Microprocessor: The Patmos Approach

Autoři: Schoeberl, Martin Schleuniger, Pascal Puffitsch, Wolfgang a další

Přispěvatelé: Schoeberl, Martin Schleuniger, Pascal Puffitsch, Wolfgang a další

Zdroj: Bringing Theory to Practice: Predictability and Performance in Embedded Systems ; https://inria.hal.science/inria-00585320 ; Bringing Theory to Practice: Predictability and Performance in Embedded Systems, Philipp Lucas, Lothar Thiele, Benoit Triquet, Theo Ungerer, and Reinhard Wilhelm, Mar 2011, Grenoble, France. pp.11-21, ⟨10.4230/OASIcs.PPES.2011.11⟩ ; http://drops.dagstuhl.de/opus/volltexte/2011/3077/pdf/2.pdf

Témata: WCET-aware Compilation, WCET Analysis, Time-predictable Architecture, ACM: C.: Computer Systems Organization/C.3: SPECIAL-PURPOSE AND APPLICATION-BASED SYSTEMS/C.3.2: Real-time and embedded systems, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.1: Single Data Stream Architectures/C.1.1.2: RISC/CISC, VLIW architectures, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [INFO.INFO-ES]Computer Science [cs]/Embedded Systems, [INFO.INFO-PF]Computer Science [cs]/Performance [cs.PF]

Geografické téma: Grenoble, France

Dostupnost: https://inria.hal.science/inria-00585320
https://inria.hal.science/inria-00585320v1/document
https://inria.hal.science/inria-00585320v1/file/schoeberl-ppes11.pdf
https://doi.org/10.4230/OASIcs.PPES.2011.11

Towards a Time-predictable Dual-Issue Microprocessor: The Patmos Approach

Autoři: Schoeberl, Martin Schleuniger, Pascal Puffitsch, Wolfgang a další

Přispěvatelé: Schoeberl, Martin Schleuniger, Pascal Puffitsch, Wolfgang a další

Zdroj: Bringing Theory to Practice: Predictability and Performance in Embedded Systems ; https://hal.inria.fr/inria-00585320 ; Bringing Theory to Practice: Predictability and Performance in Embedded Systems, Philipp Lucas, Lothar Thiele, Benoit Triquet, Theo Ungerer, and Reinhard Wilhelm, Mar 2011, Grenoble, France. pp.11-21, ⟨10.4230/OASIcs.PPES.2011.11⟩ ; http://drops.dagstuhl.de/opus/volltexte/2011/3077/pdf/2.pdf

Témata: Time-predictable Architecture, WCET Analysis, WCET-aware Compilation, ACM: C.: Computer Systems Organization/C.3: SPECIAL-PURPOSE AND APPLICATION-BASED SYSTEMS/C.3.2: Real-time and embedded systems, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.1: Single Data Stream Architectures/C.1.1.2: RISC/CISC, VLIW architectures, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [INFO.INFO-ES]Computer Science [cs]/Embedded Systems, [INFO.INFO-PF]Computer Science [cs]/Performance [cs.PF]

Geografické téma: Grenoble, France

Relation: inria-00585320; https://hal.inria.fr/inria-00585320; https://hal.inria.fr/inria-00585320/document; https://hal.inria.fr/inria-00585320/file/schoeberl-ppes11.pdf

Dostupnost: https://hal.inria.fr/inria-00585320
https://hal.inria.fr/inria-00585320/document
https://hal.inria.fr/inria-00585320/file/schoeberl-ppes11.pdf
https://doi.org/10.4230/OASIcs.PPES.2011.11

Micro-architectural simulation of embedded core heterogeneity with gem5 and McPAT

Autoři: Endo, F.A. Couroussé, Damien Charles, H.-P. a další

Přispěvatelé: Endo, F.A. Couroussé, Damien Charles, H.-P. a další

Zdroj: RAPIDO '15 Proceedings of the 2015 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools ; https://cea.hal.science/cea-01818887 ; RAPIDO '15 Proceedings of the 2015 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools, Jan 2015, Amsterdam, Netherlands. ⟨10.1145/2693433.2693440⟩

Témata: ACM: I.: Computing Methodologies/I.6: SIMULATION AND MODELING/I.6.7: Simulation Support Systems, ACM: I.: Computing Methodologies/I.6: SIMULATION AND MODELING/I.6.7: Simulation Support Systems/I.6.7.0: Environments, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.1: Single Data Stream Architectures, [INFO]Computer Science [cs]

Geografické téma: Amsterdam, Netherlands

Dostupnost: https://cea.hal.science/cea-01818887
https://doi.org/10.1145/2693433.2693440

Micro-architectural simulation of embedded core heterogeneity with gem5 and McPAT

Autoři: Endo, F.A. Couroussé, Damien Charles, H.-P. a další

Přispěvatelé: Endo, F.A. Couroussé, Damien Charles, H.-P. a další

Zdroj: RAPIDO '15 Proceedings of the 2015 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools ; https://hal-cea.archives-ouvertes.fr/cea-01818887 ; RAPIDO '15 Proceedings of the 2015 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools, Jan 2015, Amsterdam, Netherlands. ⟨10.1145/2693433.2693440⟩

Témata: ACM: I.: Computing Methodologies/I.6: SIMULATION AND MODELING/I.6.7: Simulation Support Systems, ACM: I.: Computing Methodologies/I.6: SIMULATION AND MODELING/I.6.7: Simulation Support Systems/I.6.7.0: Environments, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.1: Single Data Stream Architectures, [INFO]Computer Science [cs]

Geografické téma: Amsterdam, Netherlands

Relation: cea-01818887; https://hal-cea.archives-ouvertes.fr/cea-01818887

Dostupnost: https://hal-cea.archives-ouvertes.fr/cea-01818887
https://doi.org/10.1145/2693433.2693440

Speculatively Vectorized Bytecode

Autoři: Rohou, Erven Dyshel, Sergei Nuzman, Dorit a další

Přispěvatelé: Rohou, Erven Dyshel, Sergei Nuzman, Dorit a další

Zdroj: International Conference on High-Performance and Embedded Architectures and Compilers ; https://inria.hal.science/inria-00525139 ; International Conference on High-Performance and Embedded Architectures and Compilers, Manolis Katevenis and Margaret Martonosi, Jan 2011, Heraklion, Greece

Témata: ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.2: Multiple Data Stream Architectures (Multiprocessors)/C.1.2.7: Single-instruction-stream, multiple-data-stream processors (SIMD), ACM: D.: Software/D.2: SOFTWARE ENGINEERING/D.2.13: Reusable Software, ACM: D.: Software/D.3: PROGRAMMING LANGUAGES/D.3.4: Processors/D.3.4.0: Code generation, ACM: D.: Software/D.3: PROGRAMMING LANGUAGES/D.3.4: Processors/D.3.4.1: Compilers, ACM: D.: Software/D.3: PROGRAMMING LANGUAGES/D.3.4: Processors/D.3.4.6: Optimization, [INFO.INFO-OH]Computer Science [cs]/Other [cs.OH]

Geografické téma: Heraklion, Greece

Relation: info:eu-repo/grantAgreement//26535/EU/High-Performance Embedded Architectures and Compilers/HIPEAC

Dostupnost: https://inria.hal.science/inria-00525139
https://inria.hal.science/inria-00525139/document
https://inria.hal.science/inria-00525139/file/Rohou-HiPEAC11.pdf

Speculatively Vectorized Bytecode

Autoři: Rohou, Erven Dyshel, Sergei Nuzman, Dorit a další

Přispěvatelé: Rohou, Erven Dyshel, Sergei Nuzman, Dorit a další

Zdroj: International Conference on High-Performance and Embedded Architectures and Compilers ; https://inria.hal.science/inria-00525139 ; International Conference on High-Performance and Embedded Architectures and Compilers, Manolis Katevenis and Margaret Martonosi, Jan 2011, Heraklion, Greece

Témata: ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.2: Multiple Data Stream Architectures (Multiprocessors)/C.1.2.7: Single-instruction-stream, multiple-data-stream processors (SIMD), ACM: D.: Software/D.2: SOFTWARE ENGINEERING/D.2.13: Reusable Software, ACM: D.: Software/D.3: PROGRAMMING LANGUAGES/D.3.4: Processors/D.3.4.0: Code generation, ACM: D.: Software/D.3: PROGRAMMING LANGUAGES/D.3.4: Processors/D.3.4.1: Compilers, ACM: D.: Software/D.3: PROGRAMMING LANGUAGES/D.3.4: Processors/D.3.4.6: Optimization, [INFO.INFO-OH]Computer Science [cs]/Other [cs.OH]

Geografické téma: Heraklion, Greece

Relation: info:eu-repo/grantAgreement//26535/EU/High-Performance Embedded Architectures and Compilers/HIPEAC

Dostupnost: https://inria.hal.science/inria-00525139
https://inria.hal.science/inria-00525139v1/document
https://inria.hal.science/inria-00525139v1/file/Rohou-HiPEAC11.pdf

Speculatively Vectorized Bytecode

Autoři: Rohou, Erven Dyshel, Sergei Nuzman, Dorit a další

Přispěvatelé: Rohou, Erven Dyshel, Sergei Nuzman, Dorit a další

Zdroj: International Conference on High-Performance and Embedded Architectures and Compilers ; https://inria.hal.science/inria-00525139 ; International Conference on High-Performance and Embedded Architectures and Compilers, Manolis Katevenis and Margaret Martonosi, Jan 2011, Heraklion, Greece

Témata: ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.2: Multiple Data Stream Architectures (Multiprocessors)/C.1.2.7: Single-instruction-stream, multiple-data-stream processors (SIMD), ACM: D.: Software/D.2: SOFTWARE ENGINEERING/D.2.13: Reusable Software, ACM: D.: Software/D.3: PROGRAMMING LANGUAGES/D.3.4: Processors/D.3.4.0: Code generation, ACM: D.: Software/D.3: PROGRAMMING LANGUAGES/D.3.4: Processors/D.3.4.1: Compilers, ACM: D.: Software/D.3: PROGRAMMING LANGUAGES/D.3.4: Processors/D.3.4.6: Optimization, [INFO.INFO-OH]Computer Science [cs]/Other [cs.OH]

Geografické téma: Heraklion, Greece

Relation: info:eu-repo/grantAgreement//26535/EU/High-Performance Embedded Architectures and Compilers/HIPEAC

Dostupnost: https://inria.hal.science/inria-00525139
https://inria.hal.science/inria-00525139v1/document
https://inria.hal.science/inria-00525139v1/file/Rohou-HiPEAC11.pdf

Speculatively Vectorized Bytecode

Autoři: Rohou, Erven Dyshel, Sergei Nuzman, Dorit a další

Přispěvatelé: Rohou, Erven Dyshel, Sergei Nuzman, Dorit a další

Zdroj: International Conference on High-Performance and Embedded Architectures and Compilers ; https://inria.hal.science/inria-00525139 ; International Conference on High-Performance and Embedded Architectures and Compilers, Manolis Katevenis and Margaret Martonosi, Jan 2011, Heraklion, Greece

Témata: ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.2: Multiple Data Stream Architectures (Multiprocessors)/C.1.2.7: Single-instruction-stream, multiple-data-stream processors (SIMD), ACM: D.: Software/D.2: SOFTWARE ENGINEERING/D.2.13: Reusable Software, ACM: D.: Software/D.3: PROGRAMMING LANGUAGES/D.3.4: Processors/D.3.4.0: Code generation, ACM: D.: Software/D.3: PROGRAMMING LANGUAGES/D.3.4: Processors/D.3.4.1: Compilers, ACM: D.: Software/D.3: PROGRAMMING LANGUAGES/D.3.4: Processors/D.3.4.6: Optimization, [INFO.INFO-OH]Computer Science [cs]/Other [cs.OH]

Geografické téma: Heraklion, Greece

Relation: info:eu-repo/grantAgreement//26535/EU/High-Performance Embedded Architectures and Compilers/HIPEAC

Dostupnost: https://inria.hal.science/inria-00525139
https://inria.hal.science/inria-00525139/document
https://inria.hal.science/inria-00525139/file/Rohou-HiPEAC11.pdf

Speculatively Vectorized Bytecode

Autoři: Rohou, Erven Dyshel, Sergei Nuzman, Dorit a další

Přispěvatelé: Rohou, Erven Dyshel, Sergei Nuzman, Dorit a další

Zdroj: International Conference on High-Performance and Embedded Architectures and Compilers ; https://hal.inria.fr/inria-00525139 ; International Conference on High-Performance and Embedded Architectures and Compilers, Manolis Katevenis and Margaret Martonosi, Jan 2011, Heraklion, Greece

Témata: ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.2: Multiple Data Stream Architectures (Multiprocessors)/C.1.2.7: Single-instruction-stream, multiple-data-stream processors (SIMD), ACM: D.: Software/D.2: SOFTWARE ENGINEERING/D.2.13: Reusable Software, ACM: D.: Software/D.3: PROGRAMMING LANGUAGES/D.3.4: Processors/D.3.4.0: Code generation, ACM: D.: Software/D.3: PROGRAMMING LANGUAGES/D.3.4: Processors/D.3.4.1: Compilers, ACM: D.: Software/D.3: PROGRAMMING LANGUAGES/D.3.4: Processors/D.3.4.6: Optimization, [INFO.INFO-OH]Computer Science [cs]/Other [cs.OH]

Geografické téma: Heraklion, Greece

Relation: info:eu-repo/grantAgreement//26535/EU/High-Performance Embedded Architectures and Compilers/HIPEAC; inria-00525139; https://hal.inria.fr/inria-00525139; https://hal.inria.fr/inria-00525139/document; https://hal.inria.fr/inria-00525139/file/Rohou-HiPEAC11.pdf

Dostupnost: https://hal.inria.fr/inria-00525139
https://hal.inria.fr/inria-00525139/document
https://hal.inria.fr/inria-00525139/file/Rohou-HiPEAC11.pdf

MPSoC Design Using Application-Specific Architecturally Visible Communication

Autoři: Kluter, Theo Brisk, Philip Charbon, Edoardo a další

Přispěvatelé: Kluter, Theo Brisk, Philip Charbon, Edoardo a další

Zdroj: HiPEAC 2009 - High Performance and Embedded Architectures and Compilers ; https://hal.inria.fr/inria-00445970 ; HiPEAC 2009 - High Performance and Embedded Architectures and Compilers, Jan 2009, Paphos, Cyprus. ⟨10.1007/978-3-540-92990-1_15⟩

Témata: ACM: B.: Hardware/B.2: ARITHMETIC AND LOGIC STRUCTURES, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES, ACM: D.: Software/D.3: PROGRAMMING LANGUAGES/D.3.4: Processors, [INFO.INFO-OH]Computer Science [cs]/Other [cs.OH], [INFO.INFO-ES]Computer Science [cs]/Embedded Systems

Geografické téma: Paphos, Cyprus

Relation: inria-00445970; https://hal.inria.fr/inria-00445970

Dostupnost: https://hal.inria.fr/inria-00445970
https://doi.org/10.1007/978-3-540-92990-1_15

Scheduling issues on thermally-constrained processors

Autoři: Michaud, Pierre Sazeides, Yiannakis Compilation, parallel architectures and system (CAPS) a další

Přispěvatelé: Michaud, Pierre Sazeides, Yiannakis Compilation, parallel architectures and system (CAPS) a další

Zdroj: https://inria.hal.science/inria-00110507 ; [Research Report] PI 1822, 2006, pp.19.

Témata: Multi-core processor, temperature, thread scheduling, time slice, activity migration, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

Relation: Report N°: PI 1822

Dostupnost: https://inria.hal.science/inria-00110507
https://inria.hal.science/inria-00110507/document
https://inria.hal.science/inria-00110507/file/PI-1822.pdf

Scheduling issues on thermally-constrained processors

Autoři: Michaud, Pierre Sazeides, Yiannakis Compilation, parallel architectures and system (CAPS) a další

Přispěvatelé: Michaud, Pierre Sazeides, Yiannakis Compilation, parallel architectures and system (CAPS) a další

Zdroj: https://inria.hal.science/inria-00110507 ; [Research Report] PI 1822, 2006, pp.19.

Témata: Multi-core processor, temperature, thread scheduling, time slice, activity migration, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

Relation: Report N°: PI 1822

Dostupnost: https://inria.hal.science/inria-00110507
https://inria.hal.science/inria-00110507v1/document
https://inria.hal.science/inria-00110507v1/file/PI-1822.pdf

Scheduling issues on thermally-constrained processors

Autoři: Michaud, Pierre Sazeides, Yiannakis Compilation, parallel architectures and system (CAPS) a další

Přispěvatelé: Michaud, Pierre Sazeides, Yiannakis Compilation, parallel architectures and system (CAPS) a další

Zdroj: https://inria.hal.science/inria-00110507 ; [Research Report] PI 1822, 2006, pp.19.

Témata: Multi-core processor, temperature, thread scheduling, time slice, activity migration, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

Relation: Report N°: PI 1822

Dostupnost: https://inria.hal.science/inria-00110507
https://inria.hal.science/inria-00110507/document
https://inria.hal.science/inria-00110507/file/PI-1822.pdf

Scheduling issues on thermally-constrained processors

Autoři: Michaud, Pierre Sazeides, Yiannakis Compilation, parallel architectures and system (CAPS) a další

Přispěvatelé: Michaud, Pierre Sazeides, Yiannakis Compilation, parallel architectures and system (CAPS) a další

Zdroj: https://hal.inria.fr/inria-00110507 ; [Research Report] PI 1822, 2006, pp.19.

Témata: Multi-core processor, temperature, thread scheduling, time slice, activity migration, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

Relation: Report N°: PI 1822; inria-00110507; https://hal.inria.fr/inria-00110507; https://hal.inria.fr/inria-00110507/document; https://hal.inria.fr/inria-00110507/file/PI-1822.pdf

Dostupnost: https://hal.inria.fr/inria-00110507
https://hal.inria.fr/inria-00110507/document
https://hal.inria.fr/inria-00110507/file/PI-1822.pdf

Periodic activity migration for fast sequential execution in future heterogeneous multicore processors

Autoři: Michaud, Pierre Compilation, parallel architectures and system (CAPS) Institut de Recherche en Informatique et Systèmes Aléatoires (IRISA) a další

Přispěvatelé: Michaud, Pierre Compilation, parallel architectures and system (CAPS) Institut de Recherche en Informatique et Systèmes Aléatoires (IRISA) a další

Zdroj: https://inria.hal.science/inria-00340566 ; [Research Report] PI 1909, 2008, pp.20.

Témata: Heterogeneous multicore processor, power consumption, heat flux, periodic activity migration, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

Relation: Report N°: PI 1909

Dostupnost: https://inria.hal.science/inria-00340566
https://inria.hal.science/inria-00340566/document
https://inria.hal.science/inria-00340566/file/PI-1909.pdf

Periodic activity migration for fast sequential execution in future heterogeneous multicore processors

Autoři: Michaud, Pierre Compilation, parallel architectures and system (CAPS) Institut de Recherche en Informatique et Systèmes Aléatoires (IRISA) a další

Přispěvatelé: Michaud, Pierre Compilation, parallel architectures and system (CAPS) Institut de Recherche en Informatique et Systèmes Aléatoires (IRISA) a další

Zdroj: https://inria.hal.science/inria-00340566 ; [Research Report] PI 1909, 2008, pp.20.

Témata: Heterogeneous multicore processor, power consumption, heat flux, periodic activity migration, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

Relation: Report N°: PI 1909

Dostupnost: https://inria.hal.science/inria-00340566
https://inria.hal.science/inria-00340566v1/document
https://inria.hal.science/inria-00340566v1/file/PI-1909.pdf

Periodic activity migration for fast sequential execution in future heterogeneous multicore processors

Autoři: Michaud, Pierre Compilation, parallel architectures and system (CAPS) Institut de Recherche en Informatique et Systèmes Aléatoires (IRISA) a další

Přispěvatelé: Michaud, Pierre Compilation, parallel architectures and system (CAPS) Institut de Recherche en Informatique et Systèmes Aléatoires (IRISA) a další

Zdroj: https://inria.hal.science/inria-00340566 ; [Research Report] PI 1909, 2008, pp.20.

Témata: Heterogeneous multicore processor, power consumption, heat flux, periodic activity migration, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

Relation: Report N°: PI 1909

Dostupnost: https://inria.hal.science/inria-00340566
https://inria.hal.science/inria-00340566/document
https://inria.hal.science/inria-00340566/file/PI-1909.pdf

Periodic activity migration for fast sequential execution in future heterogeneous multicore processors

Autoři: Michaud, Pierre Compilation, parallel architectures and system (CAPS) Institut de Recherche en Informatique et Systèmes Aléatoires (IRISA) a další

Přispěvatelé: Michaud, Pierre Compilation, parallel architectures and system (CAPS) Institut de Recherche en Informatique et Systèmes Aléatoires (IRISA) a další

Zdroj: https://hal.inria.fr/inria-00340566 ; [Research Report] PI 1909, 2008, pp.20.

Témata: Heterogeneous multicore processor, power consumption, heat flux, periodic activity migration, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

Relation: Report N°: PI 1909; inria-00340566; https://hal.inria.fr/inria-00340566; https://hal.inria.fr/inria-00340566/document; https://hal.inria.fr/inria-00340566/file/PI-1909.pdf

Dostupnost: https://hal.inria.fr/inria-00340566
https://hal.inria.fr/inria-00340566/document
https://hal.inria.fr/inria-00340566/file/PI-1909.pdf

Predictive Thermal Management for Chip Multiprocessors Using Co-designed Virtual Machines

Autoři: Khan, Omer Kundu, Sandip Department of Electrical and Computer Engineering - University of Massachusetts (ECE) a další

Přispěvatelé: Khan, Omer Kundu, Sandip Department of Electrical and Computer Engineering - University of Massachusetts (ECE) a další

Zdroj: HiPEAC 2009 - High Performance and Embedded Architectures and Compilers ; https://hal.inria.fr/inria-00446303 ; HiPEAC 2009 - High Performance and Embedded Architectures and Compilers, Jan 2009, Paphos, Cyprus. ⟨10.1007/978-3-540-92990-1_22⟩

Témata: ACM: B.: Hardware/B.2: ARITHMETIC AND LOGIC STRUCTURES, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES, ACM: D.: Software/D.3: PROGRAMMING LANGUAGES/D.3.4: Processors, [INFO.INFO-OH]Computer Science [cs]/Other [cs.OH], [INFO.INFO-ES]Computer Science [cs]/Embedded Systems

Geografické téma: Paphos, Cyprus

Relation: inria-00446303; https://hal.inria.fr/inria-00446303

Dostupnost: https://hal.inria.fr/inria-00446303
https://doi.org/10.1007/978-3-540-92990-1_22