Search Results - acm: c.: computer systems organizacion/c.1: processor architektura/c.1.4: parallel architektura~
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Authors: et al.
Contributors: et al.
Source: Bibliogr. przy rozdz.
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Alternate Title: Stack matrix architecture for parallel processing using reverse Polish notation. (English)
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Source: Przegląd Elektrotechniczny; 2025, Issue 10, p82-89, 8p
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Subject Terms: procesor, čipová sada, inovace, architektura, otázky, technologie, Moodle, processor, chipset, innovation, architecture, questions, technology
File Description: 4772132 bytes; application/pdf
Relation: OSD002; http://hdl.handle.net/10084/88411; S2723; KAP098_FS_B2341_3902R001_2011
Availability: http://hdl.handle.net/10084/88411
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Source: Bibliogr. przy poszczególnych referatach.
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Subject Terms: klasifikace procesorů, architektura procesorů, jazyk pro popis architektur, ADL, procesor, mikrokontrolér, MCS51, zřetězené zpracování, hazard, modelování, simulace, Codasip, CodAL, processor classification, processor architecture, architecture description languages, processor, microcontroller, pipeline, modeling, simulation
Time: 8051
File Description: application/pdf; text/html
Relation: KRŮPA, T. Vytvoření modelu procesoru 8051 [online]. Brno: Vysoké učení technické v Brně. Fakulta informačních technologií. 2014.; 79794; http://hdl.handle.net/11012/56513
Availability: http://hdl.handle.net/11012/56513
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Source: Bibliogr. s. 310-339. Indeks.
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Authors: By:VICTORIS
Source: Business Wire, March 11, 2004
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Subject Terms: TRIPS, Tera-op Reliable Intelligently Adaptive Processing System, EDGE, Explicit Data Graph Execution, procesorová architektura, paralelizmus, paralelní výpočty, polymorfní procesor, processor architecture, parallelism, parallel computation, polymorph processor
File Description: 1977663 bytes; application/pdf; application/octet-stream; text/plain; image/jpeg; downloadable_files_count: 5
Relation: OSD002; https://hdl.handle.net/10084/87594; S2724; KRU255_FEI_B2647_2612R025_2011
Availability: https://hdl.handle.net/10084/87594
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Source: Business Wire, November 15, 2005
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Source: Bibliogr. przy ref. Indeks.
Subject Terms: Architektura sieci komputerowych -- konferencje
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Authors: By:Harold Lundstrom, Chess Editor
Source: Deseret News, The (Salt Lake City, UT), June 23, 1995 Today Metro, 3pp
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Subject Terms: simulátor, emulátor, počítačový systém, procesor, instrukce, mikroinstrukce, mikroprocesor, architektura, simulator, emulator, computer system, processor, instruction, microinstruction, microprocessor, architecture
File Description: application/pdf; application/zip; text/html
Relation: FRIML, D. Výukový simulátor počítačového systému [online]. Brno: Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií. 2018.; 111121; http://hdl.handle.net/11012/81995
Availability: http://hdl.handle.net/11012/81995
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Alternate Title: Energooszczędna architektura sieci dla rozwoju inteligentnych miast. (Polish)
Authors: et al.
Source: Przegląd Elektrotechniczny; 2023, Vol. 2023 Issue 9, p135-140, 6p
Subject Terms: URBAN growth, 6G networks, SMART cities, MIXED integer linear programming, PROCESS capability, SOFTWARE architecture, COMPUTER networking equipment
Reviews & Products: SUSTAINABLE Development Goals (United Nations)
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Alternate Title: WYMAGANIA I ARCHITEKTURA SYSTEMU PŁATNOŚCI W INTERNECIE PRZYSZŁOŚCI. (Polish)
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Source: Business Informatics / Informatyka Ekonomiczna; 2012, Vol. 2 Issue 24, p91-103, 13p
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Authors: By:NGHIL
Source: Business Wire, July 1, 2004
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Subject Terms: diabetes, glukóza, monitorace, software, predikce, simulace, gluocse, monitoring, prediction, simulation
File Description: 8 s.; application/pdf
Relation: Procedia Computer Science; http://hdl.handle.net/11025/35979; 471261700035
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Subject Terms: Computer, Počítač, Procesor, Predikce skoků, Paměť cache, Architecture, Branch prediction, Pipelining, Architektura, Cache memory, Processor, Instruction, Instrukce
File Description: application/pdf; text/html
Access URL: http://hdl.handle.net/11012/187521
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Subject Terms: Architektura, Počítač, Procesor, Instrukce, Pipelining, Predikce skoků, Paměť cache, Architecture, Computer, Processor, Instruction, Branch prediction, Cache memory
File Description: application/pdf; text/html
Relation: ZLATOHLÁVKOVÁ, L. Návrh a implementace prostředků pro zvýšení výkonu procesoru [online]. Brno: Vysoké učení technické v Brně. Fakulta informačních technologií. .; 14878; http://hdl.handle.net/11012/187521
Availability: http://hdl.handle.net/11012/187521
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