Search Results - acm: c.: computer systems organizacion/c.1: processor architectures/c.1.4: parallel architekture*

Memory management and communication on homogeneous and heterogeneous parallel systems

Authors: Martins, Paula Ruano, M. Graça Cunha, J. C. E et al.

Contributors: Martins, Paula Ruano, M. Graça Cunha, J. C. E et al.

Subject Terms: Architectures, Digital signal processors, Parallel processing, Memory banks, Communication channels, Performance analysis

File Description: application/pdf

Relation: 0-08-043685-4; AUT: MRU00118

Availability: http://hdl.handle.net/10400.1/5870

Parallel ILP for distributed-memory architectures

Authors: Nuno A. Fonseca Ashwin Srinivasan Fernando Silva et al.

Subject Terms: Ciência de computadores, Ciências da computação e da informação, Computer science, Computer and information sciences

File Description: application/pdf

Relation: 0885-6125

Availability: https://hdl.handle.net/10216/91401

The AMPERE Project: A Model-driven development framework for highly Parallel and EneRgy-Efficient computation supporting multi-criteria optimization

Authors: Quiñones, Eduardo Royuela, Sara Scordino, Claudio et al.

Contributors: Quiñones, Eduardo Royuela, Sara Scordino, Claudio et al.

Subject Terms: Parallel programming models, Parallel and heterogeneous embedded processor architectures, Model-driven approaches, Safety-critical embedded systems

File Description: application/pdf

Relation: 2375-5261

Availability: http://hdl.handle.net/10400.22/16386

Memory management and its influence on the communication of homogeneous and heterogeneous parallel systems

Authors: Martins, Paula Ventura M G Ruano Cunha, José et al.

Contributors: Martins, Paula Ventura M G Ruano Cunha, José et al.

Subject Terms: Architectures, Digital signal processors, Parallel processing

File Description: application/pdf

Availability: http://hdl.handle.net/10400.1/12678

Analiza parametrów czasowych architektury potokowej specjalizowanych procesorów sprzętowychThe parameters analysis for pipeline architekture of specialised hardware processor

Authors: Wiatr, K.

Subject Terms: systemy czasu rzeczywistego, architektury systemów wieloprocesorowych, układy programowalne, image processing systems, architecture hardware processors

Access URL: http://yadda.icm.edu.pl/baztech/element/bwmeta1.element.baztech-article-BWA1-0001-0487

Parallel graphics and visualization

Authors: Santos, Luís Paulo Reiners, Dirk Favre, Jean et al.

Contributors: Santos, Luís Paulo Reiners, Dirk Favre, Jean et al.

Subject Terms: Editorial, Parallel graphics and visualization

File Description: application/pdf

Relation: 0097-8493

Availability: https://hdl.handle.net/1822/14616

A many-core co-processor for embedded parallel computing on FPGA

Authors: José, Wilson Neto, Horácio Véstias, Mário et al.

Contributors: José, Wilson Neto, Horácio Véstias, Mário et al.

Subject Terms: Many-core, FPGA, Matrix multiplication, Parallel processing, Reconfigurable computing

File Description: application/pdf

Relation: 978-1-4673-8035-5

Availability: http://hdl.handle.net/10400.21/6014

Towards an algorithmic skeleton framework for programming the Intel R Xeon PhiTM processor

Authors: Marques, Hélder de Almeida Paulino, Hervé RUN

Contributors: Marques, Hélder de Almeida Paulino, Hervé RUN

Subject Terms: Many integrated cores architectures, Intel R Xeon PhiTM, Parallel programming, Algorithmic skeletons

File Description: application/pdf

Availability: http://hdl.handle.net/10362/14394

Akcelerace algoritmů na architektuře Larrabee ; Algorithm Acceleration on Larrabee Platform

Authors: Veselý, Ivo Zemčík, Pavel Seeman, Michal

Contributors: Veselý, Ivo Zemčík, Pavel Seeman, Michal

Subject Terms: Larrabee, počítačová grafika, zpracování obrazu, více-jádrové počítání, paralelní počítání, SIMD, GPGPU, syntéza hologramu, optické pole, computer graphics, image processing, many-core computing, parallel computing, hologram synthesis, optical field

File Description: application/pdf; text/html

Relation: VESELÝ, I. Akcelerace algoritmů na architektuře Larrabee [online]. Brno: Vysoké učení technické v Brně. Fakulta informačních technologií. 2010.; 34936; http://hdl.handle.net/11012/52800

Availability: http://hdl.handle.net/11012/52800

An Agent-Based Approach to Service-Oriented Architectures

Authors: Konnerth, Thomas Albayrak, Sahin

Contributors: Konnerth, Thomas Albayrak, Sahin

Availability: http://data.europeana.eu/aggregation/europeana/2048441/item_UFDH56JQSGIBH42JB4NBBKGOLSTXH4DE
http://data.europeana.eu/item/2048441/item_UFDH56JQSGIBH42JB4NBBKGOLSTXH4DE

Memory Controllers for Mixed-Time-Criticality Systems

Architectures, Methodologies and Trade-offs

Authors: Goossens, Sven Chandrasekar, Karthik Åkesson, Benny et al.

Contributors: Goossens, Sven Chandrasekar, Karthik Åkesson, Benny et al.

Subject Terms: Circuits and Systems, Processor Architectures, Electronics and Microelectronics, Instrumentation

File Description: application/pdf

Relation: 978-3-319-32093-9 (Print); 978-3-319-32094-6 (Online)

Availability: http://hdl.handle.net/10400.22/9340

Real-time implementation of a Doppler signal spectral estimator using sequential and parallel processing techniques

Authors: Madeira, M. M. Tokhi, M. O. Ruano, M. Graça et al.

Contributors: Madeira, M. M. Tokhi, M. O. Ruano, M. Graça et al.

Subject Terms: Digital signal processing, Doppler signal spectral estimator, Heterogeneous architectures, High performance computing, Homogeneous architectures, Real-time signal processing, Sequential processing, Parallel processing, Spectral estimation

File Description: application/pdf

Relation: 0141-9331; AUT: MRU00118

Availability: http://hdl.handle.net/10400.1/5869

Návrh paralelního soft-procesoru ; Design of Parallel Soft-processor

Authors: Patera Adam Vítek Stanislav Veřtát Ivo

Contributors: Patera Adam Vítek Stanislav Veřtát Ivo

Subject Terms: Soft-mikroprocesor,CORDIC,UMA, Soft-microprocessor,CORDIC,UMA

Relation: http://hdl.handle.net/10467/73926

Availability: http://hdl.handle.net/10467/73926

Workload characterization: a survey.

Authors: Calzarossa, M. Serazzi, G.

Source: Proceedings of the IEEE; 1993, Vol. 81 Issue 8, p1136-1150, 15p

Comparative study of different Doppler spectrum estimator implementations

Authors: Madeira, M. M. Tokhi, M. O. Ruano, M. Graça et al.

Contributors: Madeira, M. M. Tokhi, M. O. Ruano, M. Graça et al.

Subject Terms: Autoregressive models, Biomedical systems, Digital signal processors, Heterogeneous architectures, Homogeneous architectures, Parallel processing, Performance analysis, Performance evaluation, Spectral estimation

File Description: application/pdf

Relation: 0-08-042930-0; AUT: MRU00118

Availability: http://hdl.handle.net/10400.1/5875

An Agent-Based Approach to Service-Oriented Architectures ; Ein agentenbasierter Ansatz für dienstorientierte Architekturen

Authors: Konnerth, Thomas Albayrak, Sahin Technische Universität Berlin, Fakultät IV - Elektrotechnik und Informatik

Contributors: Konnerth, Thomas Albayrak, Sahin Technische Universität Berlin, Fakultät IV - Elektrotechnik und Informatik

Subject Terms: 004 Datenverarbeitung, Informatik, Architektur, Mehragentensysteme, Serviceorientierte Architektur, Architecture, Multi-Agent Systems, Service-Oriented Architekture

File Description: application/pdf

Availability: https://depositonce.tu-berlin.de/handle/11303/3744
https://nbn-resolving.org/urn:nbn:de:kobv:83-opus-37906
https://doi.org/10.14279/depositonce-3447

Analýza kryptografických operací na různých architekturách procesoru ; Analysis of cryptographic operations on various processor architectures

Authors: Kubík, Hynek Lieskovan, Tomáš Gerlich, Tomáš

Contributors: Kubík, Hynek Lieskovan, Tomáš Gerlich, Tomáš

Subject Terms: Kryptografie, Procesory, Cluster, Analýza dat, Sběr dat, Bezpečnost, Cryptography, Processors, Data Analysis, Data Acquisition, Security

File Description: application/pdf; application/zip; text/html

Relation: KUBÍK, H. Analýza kryptografických operací na různých architekturách procesoru [online]. Brno: Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií. 2022.; 141342; http://hdl.handle.net/11012/205530

Availability: http://hdl.handle.net/11012/205530

Experiences on object tracking using a many-core embedded system

Authors: Minozzo, Laercio Rufino, José Lima, José et al.

Contributors: Minozzo, Laercio Rufino, José Lima, José et al.

Subject Terms: Visual tracking, Computer vision, Embedded systems, Heterogeneous systems, Parallel / hybrid programming

File Description: application/pdf

Relation: 978-989-8533-69-2

Availability: http://hdl.handle.net/10198/16259

Informace o architektuře pro optimalizace v překladači LLVM ; Architecture Information for LLVM Compiler Optimizations

Authors: Svoboda, Jan Hruška, Tomáš Dolíhal, Luděk

Contributors: Svoboda, Jan Hruška, Tomáš Dolíhal, Luděk

Subject Terms: překladač, optimalizace, cenový model, procesor, architektura, Codasip, CodAL, LLVM, compiler, optimization, cost model, processor, architecture

File Description: application/pdf; text/html

Relation: SVOBODA, J. Informace o architektuře pro optimalizace v překladači LLVM [online]. Brno: Vysoké učení technické v Brně. Fakulta informačních technologií. 2020.; 129281; http://hdl.handle.net/11012/192463

Availability: http://hdl.handle.net/11012/192463

Otrazhenie rimskogo mifa v russkoj architekture XVIII veka [Riflessi del mito di Roma nell'architettura russa del XVIII sec.]

Authors: GIULIANI, Rita C. DI MEO

Access URL: https://hdl.handle.net/11573/168174