Search Results - acm: c.: computer systems organizacion/c.1: processor architectural

Micro-architectural simulation of embedded core heterogeneity with gem5 and McPAT

Authors: Endo, F.A. Couroussé, Damien Charles, H.-P. et al.

Contributors: Endo, F.A. Couroussé, Damien Charles, H.-P. et al.

Source: RAPIDO '15 Proceedings of the 2015 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools ; https://cea.hal.science/cea-01818887 ; RAPIDO '15 Proceedings of the 2015 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools, Jan 2015, Amsterdam, Netherlands. ⟨10.1145/2693433.2693440⟩

Subject Terms: ACM: I.: Computing Methodologies/I.6: SIMULATION AND MODELING/I.6.7: Simulation Support Systems, ACM: I.: Computing Methodologies/I.6: SIMULATION AND MODELING/I.6.7: Simulation Support Systems/I.6.7.0: Environments, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.1: Single Data Stream Architectures, [INFO]Computer Science [cs]

Subject Geographic: Amsterdam, Netherlands

Availability: https://cea.hal.science/cea-01818887
https://doi.org/10.1145/2693433.2693440

Scheduling Analysis from Architectural Models of Embedded Multi-Processor Systems

Authors: Rubini, Stéphane Fotsing, Christian Singhoff, Frank et al.

Contributors: Rubini, Stéphane Fotsing, Christian Singhoff, Frank et al.

Source: ISSN: 1551-3688 ; ACM SIGBED Review ; https://hal.univ-brest.fr/hal-00983407 ; ACM SIGBED Review, 2014, 11 (1.

Subject Terms: [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [INFO.INFO-ES]Computer Science [cs]/Embedded Systems

Availability: https://hal.univ-brest.fr/hal-00983407
https://hal.univ-brest.fr/hal-00983407v1/document
https://hal.univ-brest.fr/hal-00983407v1/file/ewili.pdf

Towards a Time-predictable Dual-Issue Microprocessor: The Patmos Approach

Authors: Schoeberl, Martin Schleuniger, Pascal Puffitsch, Wolfgang et al.

Contributors: Schoeberl, Martin Schleuniger, Pascal Puffitsch, Wolfgang et al.

Source: Bringing Theory to Practice: Predictability and Performance in Embedded Systems ; https://inria.hal.science/inria-00585320 ; Bringing Theory to Practice: Predictability and Performance in Embedded Systems, Philipp Lucas, Lothar Thiele, Benoit Triquet, Theo Ungerer, and Reinhard Wilhelm, Mar 2011, Grenoble, France. pp.11-21, ⟨10.4230/OASIcs.PPES.2011.11⟩ ; http://drops.dagstuhl.de/opus/volltexte/2011/3077/pdf/2.pdf

Subject Terms: WCET-aware Compilation, WCET Analysis, Time-predictable Architecture, ACM: C.: Computer Systems Organization/C.3: SPECIAL-PURPOSE AND APPLICATION-BASED SYSTEMS/C.3.2: Real-time and embedded systems, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.1: Single Data Stream Architectures/C.1.1.2: RISC/CISC, VLIW architectures, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [INFO.INFO-ES]Computer Science [cs]/Embedded Systems, [INFO.INFO-PF]Computer Science [cs]/Performance [cs.PF]

Subject Geographic: Grenoble, France

Availability: https://inria.hal.science/inria-00585320
https://inria.hal.science/inria-00585320v1/document
https://inria.hal.science/inria-00585320v1/file/schoeberl-ppes11.pdf
https://doi.org/10.4230/OASIcs.PPES.2011.11

Architectural and Protocol Exploration for 3D Optical Network-on-Chip ; Exploration architecturale et protocolaire pour un réseaux 3D optique sur puce

Authors: Luo, Jiating Energy Efficient Computing ArchItectures with Embedded Reconfigurable Resources (CAIRN) Inria Rennes – Bretagne Atlantique et al.

Contributors: Luo, Jiating Energy Efficient Computing ArchItectures with Embedded Reconfigurable Resources (CAIRN) Inria Rennes – Bretagne Atlantique et al.

Source: https://inria.hal.science/tel-01956255 ; Hardware Architecture [cs.AR]. Université de Rennes 1 [UR1], 2018. English. ⟨NNT : ⟩.

Subject Terms: Network on chip NoC, Réseau sur puce NoC, ACM: C.: Computer Systems Organization/C.2: COMPUTER-COMMUNICATION NETWORKS/C.2.1: Network Architecture and Design, ACM: D.: Software/D.4: OPERATING SYSTEMS, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [INFO.INFO-ET]Computer Science [cs]/Emerging Technologies [cs.ET]

Availability: https://inria.hal.science/tel-01956255
https://inria.hal.science/tel-01956255v1/document
https://inria.hal.science/tel-01956255v1/file/These_Jiating_fin.pdf

Predictive Thermal Management for Chip Multiprocessors Using Co-designed Virtual Machines

Authors: Khan, Omer Kundu, Sandip Department of Electrical and Computer Engineering - University of Massachusetts (ECE) et al.

Contributors: Khan, Omer Kundu, Sandip Department of Electrical and Computer Engineering - University of Massachusetts (ECE) et al.

Source: HiPEAC 2009 - High Performance and Embedded Architectures and Compilers ; https://hal.inria.fr/inria-00446303 ; HiPEAC 2009 - High Performance and Embedded Architectures and Compilers, Jan 2009, Paphos, Cyprus. ⟨10.1007/978-3-540-92990-1_22⟩

Subject Terms: ACM: B.: Hardware/B.2: ARITHMETIC AND LOGIC STRUCTURES, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES, ACM: D.: Software/D.3: PROGRAMMING LANGUAGES/D.3.4: Processors, [INFO.INFO-OH]Computer Science [cs]/Other [cs.OH], [INFO.INFO-ES]Computer Science [cs]/Embedded Systems

Subject Geographic: Paphos, Cyprus

Relation: inria-00446303; https://hal.inria.fr/inria-00446303

Availability: https://hal.inria.fr/inria-00446303
https://doi.org/10.1007/978-3-540-92990-1_22

Periodic activity migration for fast sequential execution in future heterogeneous multicore processors

Authors: Michaud, Pierre Compilation, parallel architectures and system (CAPS) Institut de Recherche en Informatique et Systèmes Aléatoires (IRISA) et al.

Contributors: Michaud, Pierre Compilation, parallel architectures and system (CAPS) Institut de Recherche en Informatique et Systèmes Aléatoires (IRISA) et al.

Source: https://inria.hal.science/inria-00340566 ; [Research Report] PI 1909, 2008, pp.20.

Subject Terms: Heterogeneous multicore processor, power consumption, heat flux, periodic activity migration, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

Relation: Report N°: PI 1909

Availability: https://inria.hal.science/inria-00340566
https://inria.hal.science/inria-00340566/document
https://inria.hal.science/inria-00340566/file/PI-1909.pdf

Communication Based Proactive Link Power Management

Authors: Muralidhara, Sai Prashanth Kandemir, Mahmut Department of Computer Science and Engineering University Park et al.

Contributors: Muralidhara, Sai Prashanth Kandemir, Mahmut Department of Computer Science and Engineering University Park et al.

Source: HiPEAC 2009 - High Performance and Embedded Architectures and Compilers ; https://hal.inria.fr/inria-00445984 ; HiPEAC 2009 - High Performance and Embedded Architectures and Compilers, Jan 2009, Paphos, Cyprus. ⟨10.1007/978-3-540-92990-1_16⟩

Subject Terms: ACM: B.: Hardware/B.2: ARITHMETIC AND LOGIC STRUCTURES, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES, ACM: D.: Software/D.3: PROGRAMMING LANGUAGES/D.3.4: Processors, [INFO.INFO-OH]Computer Science [cs]/Other [cs.OH], [INFO.INFO-ES]Computer Science [cs]/Embedded Systems

Subject Geographic: Paphos, Cyprus

Relation: inria-00445984; https://hal.inria.fr/inria-00445984

Availability: https://hal.inria.fr/inria-00445984
https://doi.org/10.1007/978-3-540-92990-1_16

Speculatively Vectorized Bytecode

Authors: Rohou, Erven Dyshel, Sergei Nuzman, Dorit et al.

Contributors: Rohou, Erven Dyshel, Sergei Nuzman, Dorit et al.

Source: International Conference on High-Performance and Embedded Architectures and Compilers ; https://inria.hal.science/inria-00525139 ; International Conference on High-Performance and Embedded Architectures and Compilers, Manolis Katevenis and Margaret Martonosi, Jan 2011, Heraklion, Greece

Subject Terms: ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.2: Multiple Data Stream Architectures (Multiprocessors)/C.1.2.7: Single-instruction-stream, multiple-data-stream processors (SIMD), ACM: D.: Software/D.2: SOFTWARE ENGINEERING/D.2.13: Reusable Software, ACM: D.: Software/D.3: PROGRAMMING LANGUAGES/D.3.4: Processors/D.3.4.0: Code generation, ACM: D.: Software/D.3: PROGRAMMING LANGUAGES/D.3.4: Processors/D.3.4.1: Compilers, ACM: D.: Software/D.3: PROGRAMMING LANGUAGES/D.3.4: Processors/D.3.4.6: Optimization, [INFO.INFO-OH]Computer Science [cs]/Other [cs.OH]

Subject Geographic: Heraklion, Greece

Relation: info:eu-repo/grantAgreement//26535/EU/High-Performance Embedded Architectures and Compilers/HIPEAC

Availability: https://inria.hal.science/inria-00525139
https://inria.hal.science/inria-00525139/document
https://inria.hal.science/inria-00525139/file/Rohou-HiPEAC11.pdf

Scheduling issues on thermally-constrained processors

Authors: Michaud, Pierre Sazeides, Yiannakis Compilation, parallel architectures and system (CAPS) et al.

Contributors: Michaud, Pierre Sazeides, Yiannakis Compilation, parallel architectures and system (CAPS) et al.

Source: https://inria.hal.science/inria-00110507 ; [Research Report] PI 1822, 2006, pp.19.

Subject Terms: Multi-core processor, temperature, thread scheduling, time slice, activity migration, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

Relation: Report N°: PI 1822

Availability: https://inria.hal.science/inria-00110507
https://inria.hal.science/inria-00110507/document
https://inria.hal.science/inria-00110507/file/PI-1822.pdf

IPC Control for Multiple Real-Time Threads on an In-Order SMT Processor

Authors: Mische, Jörg Uhrig, Sascha Kluge, Florian et al.

Contributors: Mische, Jörg Uhrig, Sascha Kluge, Florian et al.

Source: HiPEAC 2009 - High Performance and Embedded Architectures and Compilers ; https://hal.inria.fr/inria-00445865 ; HiPEAC 2009 - High Performance and Embedded Architectures and Compilers, Jan 2009, Paphos, Cyprus. ⟨10.1007/978-3-540-92990-1_11⟩

Subject Terms: ACM: B.: Hardware/B.2: ARITHMETIC AND LOGIC STRUCTURES, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES, ACM: D.: Software/D.3: PROGRAMMING LANGUAGES, ACM: D.: Software/D.3: PROGRAMMING LANGUAGES/D.3.4: Processors, [INFO.INFO-OH]Computer Science [cs]/Other [cs.OH], [INFO.INFO-ES]Computer Science [cs]/Embedded Systems

Subject Geographic: Paphos, Cyprus

Relation: inria-00445865; https://hal.inria.fr/inria-00445865

Availability: https://hal.inria.fr/inria-00445865
https://doi.org/10.1007/978-3-540-92990-1_11

A Framework for Task Scheduling and Memory Partitioning for Multi-Processor System-on-Chip

Authors: Salamy, Hassan Ramanujam, J. Department of Electrical and Computer Engineering - Louisiana State University (ECE) et al.

Contributors: Salamy, Hassan Ramanujam, J. Department of Electrical and Computer Engineering - Louisiana State University (ECE) et al.

Source: HiPEAC 2009 - High Performance and Embedded Architectures and Compilers ; https://hal.inria.fr/inria-00446288 ; HiPEAC 2009 - High Performance and Embedded Architectures and Compilers, Jan 2009, Paphos, Cyprus. ⟨10.1007/978-3-540-92990-1_20⟩

Subject Terms: ACM: B.: Hardware/B.2: ARITHMETIC AND LOGIC STRUCTURES, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES, ACM: D.: Software/D.3: PROGRAMMING LANGUAGES/D.3.4: Processors, [INFO.INFO-OH]Computer Science [cs]/Other [cs.OH], [INFO.INFO-ES]Computer Science [cs]/Embedded Systems

Subject Geographic: Paphos, Cyprus

Relation: inria-00446288; https://hal.inria.fr/inria-00446288

Availability: https://hal.inria.fr/inria-00446288
https://doi.org/10.1007/978-3-540-92990-1_20

Towards a New Processor Architecture. ; Vers une nouvelle Architecture de Processeurs

Authors: Vincent, Pierre Landru, Jacques Ecole nationale supérieure Mines-Télécom Lille Douai (IMT Nord Europe) et al.

Contributors: Vincent, Pierre Landru, Jacques Ecole nationale supérieure Mines-Télécom Lille Douai (IMT Nord Europe) et al.

Source: https://hal.science/hal-05117313 ; 2025.

Subject Terms: silicon, parallel, serial, RISC, photonics, computer, optronics, optics, processor, fiber, laser, digital, silicium, parallèle, série, processeur, photonique, ordinateur, optronique, optique, numérique, fibre, ACM: B.: Hardware, ACM: C.: Computer Systems Organization, [INFO]Computer Science [cs], [PHYS]Physics [physics]

Availability: https://hal.science/hal-05117313
https://hal.science/hal-05117313v2/document
https://hal.science/hal-05117313v2/file/frParalSerieRiscV1.pdf

Novel Architecture of Smart FFT Processor

Authors: Teymourzadeh, Rozita University of California San Francisco (UC San Francisco) University of California (UC)

Contributors: Teymourzadeh, Rozita University of California San Francisco (UC San Francisco) University of California (UC)

Source: https://hal.archives-ouvertes.fr/hal-01802071 ; 2014.

Subject Terms: FFT, Digital Design, Processor, VLSI, Novel Architecture, Radix, Harmonic, ACM: D.: Software, ACM: B.: Hardware, ACM: C.: Computer Systems Organization, ACM: I.: Computing Methodologies, ACM: B.: Hardware/B.6: LOGIC DESIGN, ACM: B.: Hardware/B.5: REGISTER-TRANSFER-LEVEL IMPLEMENTATION, ACM: D.: Software/D.3: PROGRAMMING LANGUAGES, [INFO]Computer Science [cs], [INFO.INFO-AO]Computer Science [cs]/Computer Arithmetic, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [INFO.INFO-ES]Computer Science [cs]/Embedded Systems, [INFO.INFO-TS]Computer Science [cs]/Signal and Image Processing, [SPI]Engineering Sciences [physics], [SPI.SIGNAL]Engineering Sciences [physics]/Signal and Image processing, [SPI.TRON]Engineering Sciences [physics]/Electronics

Relation: hal-01802071; https://hal.archives-ouvertes.fr/hal-01802071; https://hal.archives-ouvertes.fr/hal-01802071/document; https://hal.archives-ouvertes.fr/hal-01802071/file/Novel%20Architecture%20of%20Smart%20FFT%20Processor_Draft.pdf

Availability: https://hal.archives-ouvertes.fr/hal-01802071
https://hal.archives-ouvertes.fr/hal-01802071/document
https://hal.archives-ouvertes.fr/hal-01802071/file/Novel%20Architecture%20of%20Smart%20FFT%20Processor_Draft.pdf

MLP-Aware Runahead Threads in a Simultaneous Multithreading Processor

Authors: Van Craeynest, Kenzo Eyerman, Stijn Eeckhout, Lieven et al.

Contributors: Van Craeynest, Kenzo Eyerman, Stijn Eeckhout, Lieven et al.

Source: HiPEAC 2009 - High Performance and Embedded Architectures and Compilers ; https://hal.inria.fr/inria-00445500 ; HiPEAC 2009 - High Performance and Embedded Architectures and Compilers, Jan 2009, Paphos, Cyprus. ⟨10.1007/978-3-540-92990-1_10⟩

Subject Terms: ACM: B.: Hardware/B.2: ARITHMETIC AND LOGIC STRUCTURES, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES, ACM: D.: Software/D.3: PROGRAMMING LANGUAGES/D.3.4: Processors, [INFO.INFO-OH]Computer Science [cs]/Other [cs.OH], [INFO.INFO-ES]Computer Science [cs]/Embedded Systems

Subject Geographic: Paphos, Cyprus

Relation: inria-00445500; https://hal.inria.fr/inria-00445500

Availability: https://hal.inria.fr/inria-00445500
https://doi.org/10.1007/978-3-540-92990-1_10

Batch Processor Sharing with Hyper-Exponential Service Time

Authors: Osipova, Natalia Models for the performance analysis and the control of networks (MAESTRO) Centre Inria d'Université Côte d'Azur et al.

Contributors: Osipova, Natalia Models for the performance analysis and the control of networks (MAESTRO) Centre Inria d'Université Côte d'Azur et al.

Source: https://inria.hal.science/inria-00144389 ; [Research Report] RR-6180, INRIA. 2007, pp.21.

Subject Terms: Cauchy matrices, Batch Processor Sharing, Two Level Processor sharing, Hyper-Exponential distribution, Laplace transform, Communication Systems, ACM: C.: Computer Systems Organization/C.2: COMPUTER-COMMUNICATION NETWORKS/C.2.2: Network Protocols, [INFO.INFO-NI]Computer Science [cs]/Networking and Internet Architecture [cs.NI], [INFO.INFO-WB]Computer Science [cs]/Web

Relation: info:eu-repo/semantics/altIdentifier/arxiv/0705.0425; ARXIV: 0705.0425

Availability: https://inria.hal.science/inria-00144389
https://inria.hal.science/inria-00144389v4/document
https://inria.hal.science/inria-00144389v4/file/rr-6180.pdf

Parallel LDPC Decoding on the Cell/B.E. Processor

Authors: Falcão, Gabriel Sousa, Leonel Silva, Vitor et al.

Contributors: Falcão, Gabriel Sousa, Leonel Silva, Vitor et al.

Source: HiPEAC 2009 - High Performance and Embedded Architectures and Compilers ; https://hal.inria.fr/inria-00446368 ; HiPEAC 2009 - High Performance and Embedded Architectures and Compilers, Jan 2009, Paphos, Cyprus. ⟨10.1007/978-3-540-92990-1_28⟩

Subject Terms: ACM: B.: Hardware/B.2: ARITHMETIC AND LOGIC STRUCTURES, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES, ACM: D.: Software/D.3: PROGRAMMING LANGUAGES/D.3.4: Processors, [INFO.INFO-OH]Computer Science [cs]/Other [cs.OH], [INFO.INFO-ES]Computer Science [cs]/Embedded Systems

Subject Geographic: Paphos, Cyprus

Relation: inria-00446368; https://hal.inria.fr/inria-00446368

Availability: https://hal.inria.fr/inria-00446368
https://doi.org/10.1007/978-3-540-92990-1_28

ACM: An Efficient Approach for Managing Shared Caches in Chip Multiprocessors

Authors: Hammoud, Mohammad Cho, Sangyeun Melhem, Rami et al.

Contributors: Hammoud, Mohammad Cho, Sangyeun Melhem, Rami et al.

Source: HiPEAC 2009 - High Performance and Embedded Architectures and Compilers ; https://hal.inria.fr/inria-00446343 ; HiPEAC 2009 - High Performance and Embedded Architectures and Compilers, Jan 2009, Paphos, Cyprus. ⟨10.1007/978-3-540-92990-1_26⟩

Subject Terms: ACM: B.: Hardware/B.2: ARITHMETIC AND LOGIC STRUCTURES, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES, ACM: D.: Software/D.3: PROGRAMMING LANGUAGES/D.3.4: Processors, [INFO.INFO-OH]Computer Science [cs]/Other [cs.OH], [INFO.INFO-ES]Computer Science [cs]/Embedded Systems, manag, lang

Subject Geographic: Paphos, Cyprus

Relation: https://hal.inria.fr/inria-00446343

Availability: https://hal.inria.fr/inria-00446343

Comparison of the Discriminatory Processor Sharing Policies

Authors: Osipova, Natalia Models for the performance analysis and the control of networks (MAESTRO) Centre Inria d'Université Côte d'Azur et al.

Contributors: Osipova, Natalia Models for the performance analysis and the control of networks (MAESTRO) Centre Inria d'Université Côte d'Azur et al.

Source: https://inria.hal.science/inria-00264111 ; [Research Report] RR-6475, INRIA. 2008, pp.19.

Subject Terms: ACM: C.: Computer Systems Organization/C.2: COMPUTER-COMMUNICATION NETWORKS/C.2.2: Network Protocols, ACM: G.: Mathematics of Computing/G.3: PROBABILITY AND STATISTICS/G.3.8: Queueing theory, [INFO.INFO-MO]Computer Science [cs]/Modeling and Simulation, [INFO.INFO-NI]Computer Science [cs]/Networking and Internet Architecture [cs.NI]

Relation: info:eu-repo/semantics/altIdentifier/arxiv/0803.2129; ARXIV: 0803.2129

Availability: https://inria.hal.science/inria-00264111
https://inria.hal.science/inria-00264111v4/document
https://inria.hal.science/inria-00264111v4/file/rr_6475_dps.pdf

FLPA: A New Methodology for Processor Power Characterization

Authors: Laurent, Johann Lab-STICC_UBS_CACS_MOCS Laboratoire des sciences et techniques de l'information, de la communication et de la connaissance (Lab-STICC) et al.

Contributors: Laurent, Johann Lab-STICC_UBS_CACS_MOCS Laboratoire des sciences et techniques de l'information, de la communication et de la connaissance (Lab-STICC) et al.

Source: Design Automation Conference ; https://hal.science/hal-00077558 ; 2002, pp100

Subject Terms: FLPA, Power characterization, C code, Energy, Estimation, DSP VLIW, IEEE, ACM, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

Availability: https://hal.science/hal-00077558

High Level Transforms for SIMD and Low-Level Computer Vision Algorithms

Authors: Lacassagne, Lionel Etiemble, Daniel Zahraee, Hassan et al.

Contributors: Lacassagne, Lionel Etiemble, Daniel Zahraee, Hassan et al.

Source: Symposium on Principles and Practice of Parallel Programming / WPMVP ; https://inria.hal.science/hal-01094906 ; Symposium on Principles and Practice of Parallel Programming / WPMVP, Feb 2014, Orlando, Florida, United States. pp.8, ⟨10.1145/2568058.2568067⟩ ; https://sites.google.com/site/ppopp2014/

Subject Terms: Intel SSE & XeonPhi, SIMD, High Level Transforms, ARM Neon, IBM Altivec, code optimization, 2D stencil, low-level computer vision and image processing algorithms, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.1: Single Data Stream Architectures, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.4: Parallel Architectures, ACM: D.: Software/D.1: PROGRAMMING TECHNIQUES/D.1.3: Concurrent Programming/D.1.3.1: Parallel programming, ACM: D.: Software/D.3: PROGRAMMING LANGUAGES/D.3.4: Processors/D.3.4.1: Compilers, ACM: D.: Software/D.3: PROGRAMMING LANGUAGES/D.3.4: Processors/D.3.4.6: Optimization, ACM: I.: Computing Methodologies/I.4: IMAGE PROCESSING AND COMPUTER VISION/I.4.7: Feature Measurement, [INFO.INFO-DS]Computer Science [cs]/Data Structures and Algorithms [cs.DS], [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [INFO.INFO-SE]Computer Science [cs]/Software Engineering [cs.SE], [INFO.INFO-DM]Computer Science [cs]/Discrete Mathematics [cs.DM], [INFO.INFO-RB]Computer Science [cs]/Robotics [cs.RO], [INFO.INFO-TI]Computer Science [cs]/Image Processing [eess.IV], [INFO.INFO-TS]Computer Science [cs]/Signal and Image Processing, [INFO.INFO-CV]Computer Science [cs]/Computer Vision and Pattern Recognition [cs.CV], [SPI.AUTO]Engineering Sciences [physics]/Automatic, [SPI.SIGNAL]Engineering Sciences [physics]/Signal and Image processing, [INFO.INFO-AO]Computer Science [cs]/Computer Arithmetic, [INFO.INFO-DC]Computer Science [cs]/Distributed, Parallel, and Cluster Computing [cs.DC]

Subject Geographic: Orlando, Florida, United States

Availability: https://inria.hal.science/hal-01094906
https://inria.hal.science/hal-01094906v1/document
https://inria.hal.science/hal-01094906v1/file/simd-140122.pdf
https://doi.org/10.1145/2568058.2568067