Search Results - acm: c.: computer systems organizacia/c.1: procesov architecture/c.1.4: parallel architecture*

See the Future Through the Fifth Generation Computer Systems Project as Seen from Abroad(The Fifth Generation Computer Systems Project and the Future of AI) / 海外から見た第五世代コンピュータプロジェクトとそこから見える未来(<特集>第五世代コンピュータと人工知能の未来)

Authors: Fuyuko MATSUMURA Susumu TAMAGAWA 松村 冬子 et al.

Source: 人工知能 / Journal of the Japanese Society for Artificial Intelligence. 2014, 29(2):149

High Speed Processing Method for A SIMD Parallel Computer

Authors: Akira IWASE Hiroyuki MIYATA Hisao Koizumi et al.

Source: IEEJ Transactions on Electronics, Information and Systems. 2002, 122(5):878

Design and Implementation of Function-Classified Parallel Computer Architecture for Personal Robots ASPIRE using RISC Processors

Authors: Nobuyuki Yamasaki Yuichiro Anzai

Source: Journal of the Robotics Society of Japan. 1996, 14(4):593

A Parallel Pipeline Convolution for Perspective Projection in Real-Time Volume Rendering / 実時間ボリュームレンダリングにおける透視投影のための並列パイプライン・コンボリューション

Authors: Hanspeter Pfister Hugh C. Lauer Masato Ogata et al.

Source: 映像情報メディア学会誌 / The Journal of The Institute of Image Information and Television Engineers. 2000, 54(9):1339

Supercomputing for the Analysis and Control of Large Scale Systems / 大規模システムの解析・制御における超高速演算

Authors: Akira MURAMATSU 村松 晃

Source: 計測と制御 / Journal of The Society of Instrument and Control Engineers. 1985, 24(8):710

Software Architecture for Parallel Computer Vision ( 'Parallel and Cooperative Processing for Image Understanding') / 並列画像理解のソフトウェアアーキテクチャ (<小特集>「並列・分散協調画像理解」)

Authors: Rin-ichiro TANIGUCHI 谷口 倫一郎

Source: 人工知能 / Journal of the Japanese Society for Artificial Intelligence. 1994, 9(5):652

Computer Architecture for Sparse Modeling and Data-Driven Science / スパースモデリングとデータ駆動科学を実現する計算機アーキテクチャ

Authors: Kenji Nagata Kenji Tanaka 永田 賢二 et al.

Source: システム／制御／情報 / SYSTEMS, CONTROL AND INFORMATION. 2017, 61(4):152

Mobile Robot Architecture with Parallelism between and within Layers / 階層間・階層内並列実行による走行ロボットアーキテクチャ

Authors: Yoshimasa Goto 後藤 吉正

Source: 日本機械学会論文集 C編 / Transactions of the Japan Society of Mechanical Engineers Series C. 1993, 59(563):2198

Toward a Lingua Franca for Deterministic Concurrent Systems

Authors: Lohstroh, Marten Menard, Christian Bateni, Soroush et al.

Source: ACM Transactions on Embedded Computing Systems. 20(4)

Subject Terms: Polyglot, coordination language, concurrency, determinism, Computer Software, Distributed Computing, Computer Hardware, Computer Hardware & Architecture

Access URL: https://escholarship.org/uc/item/91v9b9r2

Software-Based Parallel Cryptographic Solution with Massive-Parallel Memory-Embedded SIMD Matrix Architecture for Data-Storage Systems

Authors: Hans Jürgen MATTAUSCH Masaharu TAGAMI Masakatsu ISHIZAKI et al.

Source: IEICE Transactions on Information and Systems. 2011, E94.D(9):1742

Implications of Emerging 3D GPU Architecture on the Scan Primitive

Authors: Power, Jason Li, Yinan Hill, Mark D et al.

Source: ACM SIGMOD Record. 44(1)

Subject Terms: Biotechnology, Bioengineering, Affordable and Clean Energy, Information Systems

File Description: application/pdf

Access URL: https://escholarship.org/uc/item/8k40w8tk
https://escholarship.org/content/qt8k40w8tk/qt8k40w8tk.pdf

The Use of ARM-Assembly Language and a Raspberry Pi 1 B+ as a Server to Improve Computer Architecture Skills

Authors: Ferreira, Vitor Manuel Pinto, Pedro Paiva, Sara et al.

Contributors: Ferreira, Vitor Manuel Pinto, Pedro Paiva, Sara et al.

Subject Terms: Always-visible in-class mobile test scenario, Arm-assembly language, Computer architecture skills, Raspberry pi, Students' efficiency and motivation levels evaluation, Geography, Planning and Development, Modelling and Simulation

File Description: application/pdf

Relation: 9783959771535; 2190-6807; PURE: 29348647

Availability: http://hdl.handle.net/10362/116230

A VLSI Architecture for Output Probability Computations of HMM-Based Recognition Systems with Store-Based Block Parallel Processing

Authors: Kazuhiro NAKAMURA Kazuyoshi TAKAGI Masatoshi YAMAMOTO et al.

Source: IEICE Transactions on Information and Systems. 2010, E93.D(2):300

A Novel Algorithm for Large-Scale Fock Matrix Generation with Small Local Distributed Memory Parallel Architecture. - Relation to the Integral Cutoff - / 分散メモリ型並列計算機に適した新しい大規模フォック行列生成アルゴリズム

Source: Journal of Chemical Software. 2000, 6(3):85

Parallel Fock Matrix Construction Algorithm for Molecular Orbital Calculation Specific Computer / 分子軌道計算専用計算機のためのフォック行列並列計算アルゴリズムの開発

Authors: Hiroaki HONDA Hiroaki UMEDA Umpei NAGASHIMA et al.

Source: Journal of Computer Chemistry, Japan. 2005, 4(4):179

724. 並列計算機PACS-32によるBWR炉心計算 / Attempt of BWR Core Simulation by Parallel Computer PACS-32

Authors: Tsutomu HOSHINO 星野 力

Source: 日本原子力学会誌 / Journal of the Atomic Energy Society of Japan / Atomic Energy Society of Japan. 1981, 23(8):598

Communication Strategy of Parallel Density-Matrix Renormalization Group Method with Considering Architecture of Multi-core Cluster / マルチコアクラスタのネットワーク構造を考慮した並列密度行列繰り込み群法の通信手法

Authors: Masahiko MACHIDA Susumu YAMADA Toshiyuki IMAMURA et al.

Source: 日本計算工学会論文集 / Transactions of the Japan Society for Computational Engineering and Science. 2009, 2009:20090015

High-Throughput Low-Complexity Four-Parallel Reed-Solomon Decoder Architecture for High-Rate WPAN Systems

Authors: Chang-Seok CHOI Hanho LEE Hyo-Jin AHN

Source: IEICE Transactions on Communications. 2011, E94.B(5):1332

An iterative pattern mapping for parallel string matching architecture in intrusion detection systems

Authors: HyunJin Kim

Source: IEICE Electronics Express. 2012, 9(11):985

High-Speed Two-Parallel Concatenated BCH-Based Super-FEC Architecture for Optical Communications

Authors: Hanho LEE Kihoon LEE Sangho YOON

Source: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. 2010, E93.A(4):769