Search Results - acm: c.: computer systems organisation/c.1: processor architecture

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  1. 1

    Novel Architecture of Smart FFT Processor

    Authors: Teymourzadeh, Rozita University of California San Francisco (UC San Francisco) University of California (UC)

    Contributors: Teymourzadeh, Rozita University of California San Francisco (UC San Francisco) University of California (UC)

    Source: https://hal.archives-ouvertes.fr/hal-01802071 ; 2014.

    Subject Terms: FFT, Digital Design, Processor, VLSI, Novel Architecture, Radix, Harmonic, ACM: D.: Software, ACM: B.: Hardware, ACM: C.: Computer Systems Organization, ACM: I.: Computing Methodologies, ACM: B.: Hardware/B.6: LOGIC DESIGN, ACM: B.: Hardware/B.5: REGISTER-TRANSFER-LEVEL IMPLEMENTATION, ACM: D.: Software/D.3: PROGRAMMING LANGUAGES, [INFO]Computer Science [cs], [INFO.INFO-AO]Computer Science [cs]/Computer Arithmetic, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [INFO.INFO-ES]Computer Science [cs]/Embedded Systems, [INFO.INFO-TS]Computer Science [cs]/Signal and Image Processing, [SPI]Engineering Sciences [physics], [SPI.SIGNAL]Engineering Sciences [physics]/Signal and Image processing, [SPI.TRON]Engineering Sciences [physics]/Electronics

    Relation: hal-01802071; https://hal.archives-ouvertes.fr/hal-01802071; https://hal.archives-ouvertes.fr/hal-01802071/document; https://hal.archives-ouvertes.fr/hal-01802071/file/Novel%20Architecture%20of%20Smart%20FFT%20Processor_Draft.pdf

    Availability: https://hal.archives-ouvertes.fr/hal-01802071
    https://hal.archives-ouvertes.fr/hal-01802071/document
    https://hal.archives-ouvertes.fr/hal-01802071/file/Novel%20Architecture%20of%20Smart%20FFT%20Processor_Draft.pdf

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  2. 2

    Towards a New Processor Architecture. ; Vers une nouvelle Architecture de Processeurs

    Authors: Vincent, Pierre Landru, Jacques Ecole nationale supérieure Mines-Télécom Lille Douai (IMT Nord Europe) et al.

    Contributors: Vincent, Pierre Landru, Jacques Ecole nationale supérieure Mines-Télécom Lille Douai (IMT Nord Europe) et al.

    Source: https://hal.science/hal-05117313 ; 2025.

    Subject Terms: silicon, parallel, serial, RISC, photonics, computer, optronics, optics, processor, fiber, laser, digital, silicium, parallèle, série, processeur, photonique, ordinateur, optronique, optique, numérique, fibre, ACM: B.: Hardware, ACM: C.: Computer Systems Organization, [INFO]Computer Science [cs], [PHYS]Physics [physics]

    Availability: https://hal.science/hal-05117313
    https://hal.science/hal-05117313v2/document
    https://hal.science/hal-05117313v2/file/frParalSerieRiscV1.pdf

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  3. 3

    Batch Processor Sharing with Hyper-Exponential Service Time

    Authors: Osipova, Natalia Models for the performance analysis and the control of networks (MAESTRO) Centre Inria d'Université Côte d'Azur et al.

    Contributors: Osipova, Natalia Models for the performance analysis and the control of networks (MAESTRO) Centre Inria d'Université Côte d'Azur et al.

    Source: https://inria.hal.science/inria-00144389 ; [Research Report] RR-6180, INRIA. 2007, pp.21.

    Subject Terms: Cauchy matrices, Batch Processor Sharing, Two Level Processor sharing, Hyper-Exponential distribution, Laplace transform, Communication Systems, ACM: C.: Computer Systems Organization/C.2: COMPUTER-COMMUNICATION NETWORKS/C.2.2: Network Protocols, [INFO.INFO-NI]Computer Science [cs]/Networking and Internet Architecture [cs.NI], [INFO.INFO-WB]Computer Science [cs]/Web

    Relation: info:eu-repo/semantics/altIdentifier/arxiv/0705.0425; ARXIV: 0705.0425

    Availability: https://inria.hal.science/inria-00144389
    https://inria.hal.science/inria-00144389v4/document
    https://inria.hal.science/inria-00144389v4/file/rr-6180.pdf

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  4. 4

    Covariance tracking: architecture optimizations for embedded systems

    Authors: Romero, Andrés Lacassagne, Lionel Gouiffès, Michèle et al.

    Contributors: Romero, Andrés Lacassagne, Lionel Gouiffès, Michèle et al.

    Source: ISSN: 1687-6172.

    Subject Terms: covariance-tracking, real-time image processing, SIMD, SSE, AVX, Neon, ACM: I.: Computing Methodologies/I.4: IMAGE PROCESSING AND COMPUTER VISION/I.4.8: Scene Analysis/I.4.8.2: Motion, ACM: I.: Computing Methodologies/I.4: IMAGE PROCESSING AND COMPUTER VISION/I.4.8: Scene Analysis/I.4.8.12: Tracking, ACM: I.: Computing Methodologies/I.4: IMAGE PROCESSING AND COMPUTER VISION/I.4.7: Feature Measurement/I.4.7.1: Invariants, ACM: I.: Computing Methodologies/I.4: IMAGE PROCESSING AND COMPUTER VISION/I.4.7: Feature Measurement/I.4.7.2: Moments, ACM: I.: Computing Methodologies/I.4: IMAGE PROCESSING AND COMPUTER VISION/I.4.7: Feature Measurement/I.4.7.5: Texture, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.4: Parallel Architectures/C.1.4.1: Mobile processors, ACM: D.: Software/D.3: PROGRAMMING LANGUAGES/D.3.4: Processors/D.3.4.6: Optimization, [INFO.INFO-DS]Computer Science [cs]/Data Structures and Algorithms [cs.DS], [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [SPI.AUTO]Engineering Sciences [physics]/Automatic, [SPI.SIGNAL]Engineering Sciences [physics]/Signal and Image processing, [INFO.INFO-AO]Computer Science [cs]/Computer Arithmetic, [INFO.INFO-DC]Computer Science [cs]/Distributed, Parallel, and Cluster Computing [cs.DC], [INFO.INFO-SE]Computer Science [cs]/Software Engineering [cs.SE], [INFO.INFO-DM]Computer Science [cs]/Discrete Mathematics [cs.DM], [INFO.INFO-RB]Computer Science [cs]/Robotics [cs.RO], [INFO.INFO-TI]Computer Science [cs]/Image Processing [eess.IV], [INFO.INFO-TS]Computer Science [cs]/Signal and Image Processing, [INFO.INFO-CV]Computer Science [cs]/Computer Vision and Pattern Recognition [cs.CV]

    Availability: https://inria.hal.science/hal-01094903
    https://inria.hal.science/hal-01094903v1/document
    https://inria.hal.science/hal-01094903v1/file/Eurasip%202014-12.pdf
    https://doi.org/10.1186/1687-6180-2014-175

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  5. 5

    Impact of Increasing Number of Neurons on Performance of Neuromorphic Architecture

    Authors: Shahsavari, Mahyar Boulet, Pierre Shahbahrami, Asadollah et al.

    Contributors: Shahsavari, Mahyar Boulet, Pierre Shahbahrami, Asadollah et al.

    Source: CADS 2017 - 19th CSI International Symposium on Computer Architecture & Digital Systems ; https://hal.science/hal-01633418 ; CADS 2017 - 19th CSI International Symposium on Computer Architecture & Digital Systems, Dec 2017, Kish, Iran

    Subject Terms: ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.3: Other Architecture Styles/C.1.3.7: Neural nets, ACM: I.: Computing Methodologies/I.5: PATTERN RECOGNITION, [INFO.INFO-NE]Computer Science [cs]/Neural and Evolutionary Computing [cs.NE], [INFO.INFO-CV]Computer Science [cs]/Computer Vision and Pattern Recognition [cs.CV], [INFO.INFO-AI]Computer Science [cs]/Artificial Intelligence [cs.AI]

    Subject Geographic: Kish, Iran

    Availability: https://hal.science/hal-01633418
    https://hal.science/hal-01633418v1/document
    https://hal.science/hal-01633418v1/file/Sub61_shahsavari_CADS17.pdf

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  6. 6

    Classification and Elimination of Conflicts in Hardware Transactional Memory Systems

    Authors: Waliullah, Mridha Mohammad Stenstrom, Per Amdahl's Law is Forever (ALF) et al.

    Contributors: Waliullah, Mridha Mohammad Stenstrom, Per Amdahl's Law is Forever (ALF) et al.

    Source: 23rd International Symposium on Computer Architecture and High Performance Computing - SBAC-PAD'2011
    https://inria.hal.science/hal-00640813
    23rd International Symposium on Computer Architecture and High Performance Computing - SBAC-PAD'2011, Oct 2011, Vitoria, Brazil

    Subject Terms: Transactional Memory, Contamination Misses, Intermediate Checkpointing, Manycore, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.0: General, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

    Subject Geographic: Vitoria, Brazil

    Time: Vitoria, Brazil

    Availability: https://inria.hal.science/hal-00640813
    https://inria.hal.science/hal-00640813/document
    https://inria.hal.science/hal-00640813/file/sbac-pad_ieee.pdf

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  7. 7

    Introduction à l'architecture des ordinateurs

    Authors: Anceau, François Etiemble, Daniel Circuits Intégrés Numériques et Analogiques (CIAN) et al.

    Contributors: Anceau, François Etiemble, Daniel Circuits Intégrés Numériques et Analogiques (CIAN) et al.

    Source: ISSN: 1776-0860 ; Techniques de l'Ingénieur ; https://hal.science/hal-01794102 ; 2010.

    Subject Terms: Architecture des ordinateurs, ACM: C.: Computer Systems Organization, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES, [INFO]Computer Science [cs], [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

    Availability: https://hal.science/hal-01794102

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  8. 8

    High Level Transforms for SIMD and Low-Level Computer Vision Algorithms

    Authors: Lacassagne, Lionel Etiemble, Daniel Zahraee, Hassan et al.

    Contributors: Lacassagne, Lionel Etiemble, Daniel Zahraee, Hassan et al.

    Source: Symposium on Principles and Practice of Parallel Programming / WPMVP ; https://inria.hal.science/hal-01094906 ; Symposium on Principles and Practice of Parallel Programming / WPMVP, Feb 2014, Orlando, Florida, United States. pp.8, ⟨10.1145/2568058.2568067⟩ ; https://sites.google.com/site/ppopp2014/

    Subject Terms: Intel SSE & XeonPhi, SIMD, High Level Transforms, ARM Neon, IBM Altivec, code optimization, 2D stencil, low-level computer vision and image processing algorithms, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.1: Single Data Stream Architectures, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.4: Parallel Architectures, ACM: D.: Software/D.1: PROGRAMMING TECHNIQUES/D.1.3: Concurrent Programming/D.1.3.1: Parallel programming, ACM: D.: Software/D.3: PROGRAMMING LANGUAGES/D.3.4: Processors/D.3.4.1: Compilers, ACM: D.: Software/D.3: PROGRAMMING LANGUAGES/D.3.4: Processors/D.3.4.6: Optimization, ACM: I.: Computing Methodologies/I.4: IMAGE PROCESSING AND COMPUTER VISION/I.4.7: Feature Measurement, [INFO.INFO-DS]Computer Science [cs]/Data Structures and Algorithms [cs.DS], [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [INFO.INFO-SE]Computer Science [cs]/Software Engineering [cs.SE], [INFO.INFO-DM]Computer Science [cs]/Discrete Mathematics [cs.DM], [INFO.INFO-RB]Computer Science [cs]/Robotics [cs.RO], [INFO.INFO-TI]Computer Science [cs]/Image Processing [eess.IV], [INFO.INFO-TS]Computer Science [cs]/Signal and Image Processing, [INFO.INFO-CV]Computer Science [cs]/Computer Vision and Pattern Recognition [cs.CV], [SPI.AUTO]Engineering Sciences [physics]/Automatic, [SPI.SIGNAL]Engineering Sciences [physics]/Signal and Image processing, [INFO.INFO-AO]Computer Science [cs]/Computer Arithmetic, [INFO.INFO-DC]Computer Science [cs]/Distributed, Parallel, and Cluster Computing [cs.DC]

    Subject Geographic: Orlando, Florida, United States

    Availability: https://inria.hal.science/hal-01094906
    https://inria.hal.science/hal-01094906v1/document
    https://inria.hal.science/hal-01094906v1/file/simd-140122.pdf
    https://doi.org/10.1145/2568058.2568067

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  9. 9

    Comparison of the Discriminatory Processor Sharing Policies

    Authors: Osipova, Natalia Models for the performance analysis and the control of networks (MAESTRO) Centre Inria d'Université Côte d'Azur et al.

    Contributors: Osipova, Natalia Models for the performance analysis and the control of networks (MAESTRO) Centre Inria d'Université Côte d'Azur et al.

    Source: https://inria.hal.science/inria-00264111 ; [Research Report] RR-6475, INRIA. 2008, pp.19.

    Subject Terms: ACM: C.: Computer Systems Organization/C.2: COMPUTER-COMMUNICATION NETWORKS/C.2.2: Network Protocols, ACM: G.: Mathematics of Computing/G.3: PROBABILITY AND STATISTICS/G.3.8: Queueing theory, [INFO.INFO-MO]Computer Science [cs]/Modeling and Simulation, [INFO.INFO-NI]Computer Science [cs]/Networking and Internet Architecture [cs.NI]

    Relation: info:eu-repo/semantics/altIdentifier/arxiv/0803.2129; ARXIV: 0803.2129

    Availability: https://inria.hal.science/inria-00264111
    https://inria.hal.science/inria-00264111v4/document
    https://inria.hal.science/inria-00264111v4/file/rr_6475_dps.pdf

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  10. 10

    Evolution de l'architecture des ordinateurs

    Authors: Etiemble, Daniel Laboratoire de Recherche en Informatique (LRI) Université Paris-Sud - Paris 11 (UP11)-CentraleSupélec-Centre National de la Recherche Scientifique (CNRS)

    Contributors: Etiemble, Daniel Laboratoire de Recherche en Informatique (LRI) Université Paris-Sud - Paris 11 (UP11)-CentraleSupélec-Centre National de la Recherche Scientifique (CNRS)

    Source: ISSN: 1776-0860 ; Techniques de l'Ingénieur ; https://hal.science/hal-01793615 ; 2016.

    Subject Terms: mur de la chaleur, mur mémoire, technologie CMOS, GPU, multi-cœur, CPU, ACM: C.: Computer Systems Organization, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES, [INFO]Computer Science [cs], [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

    Availability: https://hal.science/hal-01793615

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  11. 11

    From Scilab to Multicore Embedded Systems: Algorithms and Methodologies

    Authors: Goulas, George Alefragis, Panayiotis Voros, Nikolaos S. et al.

    Contributors: Goulas, George Alefragis, Panayiotis Voros, Nikolaos S. et al.

    Source: Proceedings of the IEEE International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (IC-SAMOS 2012 ; https://inria.hal.science/hal-00752615 ; Proceedings of the IEEE International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (IC-SAMOS 2012, Jul 2012, Samos, Greece

    Subject Terms: ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.4: Parallel Architectures, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

    Subject Geographic: Samos, Greece

    Availability: https://inria.hal.science/hal-00752615

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  12. 12

    Hardware-Accelerated Dynamic Binary Translation

    Authors: Rokicki, Simon Rohou, Erven Derrien, Steven et al.

    Contributors: Rokicki, Simon Rohou, Erven Derrien, Steven et al.

    Source: IEEE/ACM Design, Automation & Test in Europe Conference & Exhibition (DATE) ; https://inria.hal.science/hal-01423639 ; IEEE/ACM Design, Automation & Test in Europe Conference & Exhibition (DATE), Mar 2017, Lausanne, Switzerland ; https://www.date-conference.com/

    Subject Terms: ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.3: Other Architecture Styles/C.1.3.5: Heterogeneous (hybrid) systems, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.3: Other Architecture Styles/C.1.3.0: Adaptable architectures, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.2: Multiple Data Stream Architectures (Multiprocessors)/C.1.2.4: Multiple-instruction-stream, multiple-data-stream processors (MIMD), ACM: D.: Software/D.3: PROGRAMMING LANGUAGES/D.3.4: Processors/D.3.4.0: Code generation, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [INFO.INFO-ES]Computer Science [cs]/Embedded Systems

    Subject Geographic: Lausanne, Switzerland

    Availability: https://inria.hal.science/hal-01423639
    https://inria.hal.science/hal-01423639v1/document
    https://inria.hal.science/hal-01423639v1/file/rokicki_DATE_cr.pdf

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  13. 13

    Architecture des ordinateurs

    Authors: Lagadec, Loïc Pillement, Sébastien Tisserand, Arnaud et al.

    Contributors: Lagadec, Loïc Pillement, Sébastien Tisserand, Arnaud et al.

    Source: https://inria.hal.science/hal-00819668 ; Loïc Lagadec and Sébastien Pillement and Arnaud Tisserand. Hermes, 32, pp.150, 2013, Technique et science informatique, 9782746245679.

    Subject Terms: ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

    Availability: https://inria.hal.science/hal-00819668

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  14. 14

    Distributed Architecture for Resource Management in Large Scale Grids

    Authors: Jeanvoine, Emmanuel Rilling, Louis Morin, Christine et al.

    Contributors: Jeanvoine, Emmanuel Rilling, Louis Morin, Christine et al.

    Source: https://inria.hal.science/inria-00001066 ; [Research Report] PI 1775, 2006, pp.13.

    Subject Terms: Grid computing, distributed system, peer-to-peer overlay networks, resource allocation, self-healing \\ Grille de calcul, système distribué, réseaux logiques pair-à-pair, allocation de ressources, auto-réparation, ACM: C.: Computer Systems Organization/C.2: COMPUTER-COMMUNICATION NETWORKS/C.2.4: Distributed Systems, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.4: Parallel Architectures, [INFO.INFO-OH]Computer Science [cs]/Other [cs.OH]

    Relation: Report N°: PI 1775

    Availability: https://inria.hal.science/inria-00001066
    https://inria.hal.science/inria-00001066v1/document
    https://inria.hal.science/inria-00001066v1/file/PI-1775.pdf

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  15. 15

    Optimizing DDR-SDRAM Communications at C-level for Automatically-Generated Hardware Accelerators. An Experience with the Altera C2H HLS Tool.

    Authors: Alias, Christophe Darte, Alain Plesco, Alexandru et al.

    Contributors: Alias, Christophe Darte, Alain Plesco, Alexandru et al.

    Source: https://inria.hal.science/inria-00482035 ; [Research Report] RR-7281, INRIA. 2010, pp.19.

    Subject Terms: High-level synthesis, hardware accelerators, DDR-SDRAM, optimized communications, program transformation, reconfigurable architectures, FPGA, ACM: B.: Hardware/B.4: INPUT/OUTPUT AND DATA COMMUNICATIONS/B.4.1: Data Communications Devices/B.4.1.0: Processors, ACM: B.: Hardware/B.4: INPUT/OUTPUT AND DATA COMMUNICATIONS/B.4.2: Input/Output Devices/B.4.2.0: Channels and controllers, ACM: B.: Hardware/B.7: INTEGRATED CIRCUITS/B.7.1: Types and Design Styles/B.7.1.1: Algorithms implemented in hardware, ACM: B.: Hardware/B.7: INTEGRATED CIRCUITS/B.7.1: Types and Design Styles/B.7.1.3: Input/output circuits, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.3: Other Architecture Styles/C.1.3.0: Adaptable architectures, [INFO.INFO-ES]Computer Science [cs]/Embedded Systems, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [INFO.INFO-PL]Computer Science [cs]/Programming Languages [cs.PL]

    Availability: https://inria.hal.science/inria-00482035
    https://inria.hal.science/inria-00482035v1/document
    https://inria.hal.science/inria-00482035v1/file/RR-7281.pdf

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  16. 16

    Supporting Runtime Reconfigurable VLIWs Cores Through Dynamic Binary Translation

    Authors: Rokicki, Simon Rohou, Erven Derrien, Steven et al.

    Contributors: Rokicki, Simon Rohou, Erven Derrien, Steven et al.

    Source: DATE 2018 - IEEE/ACM Design, Automation & Test in Europe Conference & Exhibition ; https://hal.science/hal-01653110 ; DATE 2018 - IEEE/ACM Design, Automation & Test in Europe Conference & Exhibition, Mar 2018, Dresden, Germany. pp.1009-1014, ⟨10.23919/DATE.2018.8342160⟩ ; https://www.date-conference.com

    Subject Terms: ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.3: Other Architecture Styles/C.1.3.5: Heterogeneous (hybrid) systems, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.3: Other Architecture Styles/C.1.3.0: Adaptable architectures, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.2: Multiple Data Stream Architectures (Multiprocessors)/C.1.2.4: Multiple-instruction-stream, multiple-data-stream processors (MIMD), ACM: D.: Software/D.3: PROGRAMMING LANGUAGES/D.3.4: Processors/D.3.4.0: Code generation, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [INFO.INFO-ES]Computer Science [cs]/Embedded Systems

    Subject Geographic: Dresden, Germany

    Availability: https://hal.science/hal-01653110
    https://hal.science/hal-01653110v2/document
    https://hal.science/hal-01653110v2/file/rokicki_18_hal.pdf
    https://doi.org/10.23919/DATE.2018.8342160

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  17. 17

    Exploring branch predictability limits with the MTAGE+SC predictor *

    Authors: Seznec, André Pushing Architecture and Compilation for Application Performance (PACAP) Inria Rennes – Bretagne Atlantique et al.

    Contributors: Seznec, André Pushing Architecture and Compilation for Application Performance (PACAP) Inria Rennes – Bretagne Atlantique et al.

    Source: 5th JILP Workshop on Computer Architecture Competitions (JWAC-5): Championship Branch Prediction (CBP-5)
    https://inria.hal.science/hal-01354251
    5th JILP Workshop on Computer Architecture Competitions (JWAC-5): Championship Branch Prediction (CBP-5), Jun 2016, Seoul, South Korea. pp.4
    http://www.jilp.org/cbp2016/

    Subject Terms: ACM: C.: Computer Systems Organization, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.1: Single Data Stream Architectures/C.1.1.1: Pipeline processors, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

    Subject Geographic: Seoul, South Korea

    Availability: https://inria.hal.science/hal-01354251
    https://inria.hal.science/hal-01354251v1/document
    https://inria.hal.science/hal-01354251v1/file/MutiTage-SC.pdf

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  18. 18

    Simty: generalized SIMT execution on RISC-V

    Authors: Collange, Caroline Pushing Architecture and Compilation for Application Performance (PACAP) Inria Rennes – Bretagne Atlantique et al.

    Contributors: Collange, Caroline Pushing Architecture and Compilation for Application Performance (PACAP) Inria Rennes – Bretagne Atlantique et al.

    Source: CARRV 2017 - 1st Workshop on Computer Architecture Research with RISC-V ; https://inria.hal.science/hal-01622208 ; CARRV 2017 - 1st Workshop on Computer Architecture Research with RISC-V, Oct 2017, Boston, United States. pp.6

    Subject Terms: SIMT, SIMD, FPGA, RISC-V, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.2: Multiple Data Stream Architectures (Multiprocessors)/C.1.2.7: Single-instruction-stream, multiple-data-stream processors (SIMD), [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

    Subject Geographic: Boston, United States

    Time: Boston, United States

    Availability: https://inria.hal.science/hal-01622208
    https://inria.hal.science/hal-01622208v3/document
    https://inria.hal.science/hal-01622208v3/file/collange_simty_carrv17.pdf

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  19. 19

    Digital Systems Design

    Authors: Sameni, Reza Shiraz University (Shiraz University)

    Contributors: Sameni, Reza Shiraz University (Shiraz University)

    Source: https://hal.science/cel-01815308 ; Engineering school. Iran. 2018.

    Subject Terms: ACM: C.: Computer Systems Organization, ACM: B.: Hardware, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES, ACM: B.: Hardware/B.5: REGISTER-TRANSFER-LEVEL IMPLEMENTATION, ACM: B.: Hardware/B.5: REGISTER-TRANSFER-LEVEL IMPLEMENTATION/B.5.1: Design, [SPI.SIGNAL]Engineering Sciences [physics]/Signal and Image processing, [INFO.INFO-AO]Computer Science [cs]/Computer Arithmetic, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [INFO.INFO-LO]Computer Science [cs]/Logic in Computer Science [cs.LO]

    Availability: https://hal.science/cel-01815308
    https://hal.science/cel-01815308v1/document
    https://hal.science/cel-01815308v1/file/CourseSlides2018.pdf

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  20. 20

    Hybrid Super/Subthreshold Design of a Low Power Scalable-Throughput FFT Architecture

    Authors: Henry, Michael B. Nazhandali, Leyla Virginia Polytechnic Institute and State University Blacksburg et al.

    Contributors: Henry, Michael B. Nazhandali, Leyla Virginia Polytechnic Institute and State University Blacksburg et al.

    Source: HiPEAC 2009 - High Performance and Embedded Architectures and Compilers ; https://hal.inria.fr/inria-00446294 ; HiPEAC 2009 - High Performance and Embedded Architectures and Compilers, Jan 2009, Paphos, Cyprus. ⟨10.1007/978-3-540-92990-1_21⟩

    Subject Terms: ACM: B.: Hardware/B.2: ARITHMETIC AND LOGIC STRUCTURES, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES, ACM: D.: Software/D.3: PROGRAMMING LANGUAGES/D.3.4: Processors, [INFO.INFO-OH]Computer Science [cs]/Other [cs.OH], [INFO.INFO-ES]Computer Science [cs]/Embedded Systems

    Subject Geographic: Paphos, Cyprus

    Relation: inria-00446294; https://hal.inria.fr/inria-00446294

    Availability: https://hal.inria.fr/inria-00446294
    https://doi.org/10.1007/978-3-540-92990-1_21

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