Search Results - acm: c.: computer systems organisation/c.1: processor architecture/c.1.4: parallel architektura~
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Alternate Title: Stack matrix architecture for parallel processing using reverse Polish notation. (English)
Authors:
Source: Przegląd Elektrotechniczny; 2025, Issue 10, p82-89, 8p
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Authors: et al.
Contributors: et al.
Source: Bibliogr. przy rozdz.
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Source: Bibliogr. przy poszczególnych referatach.
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Alternate Title: Information Architecture in Foreign Literature 1982–2018. Quantitative Analysis. (English)
Authors: Matysek, Anna
Source: Zagadnienia Informacji Naukowej; 2018, Vol. 112 Issue 2, p88-111, 24p
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Source: Bibliogr. przy ref. Indeks.
Subject Terms: Architektura sieci komputerowych -- konferencje
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Alternate Title: Energooszczędna architektura sieci dla rozwoju inteligentnych miast. (Polish)
Authors: et al.
Source: Przegląd Elektrotechniczny; 2023, Vol. 2023 Issue 9, p135-140, 6p
Subject Terms: URBAN growth, 6G networks, SMART cities, MIXED integer linear programming, PROCESS capability, SOFTWARE architecture, COMPUTER networking equipment
Reviews & Products: SUSTAINABLE Development Goals (United Nations)
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7
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Subject Terms: procesor, čipová sada, inovace, architektura, otázky, technologie, Moodle, processor, chipset, innovation, architecture, questions, technology
File Description: 4772132 bytes; application/pdf
Relation: OSD002; http://hdl.handle.net/10084/88411; S2723; KAP098_FS_B2341_3902R001_2011
Availability: http://hdl.handle.net/10084/88411
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Alternate Title: WYMAGANIA I ARCHITEKTURA SYSTEMU PŁATNOŚCI W INTERNECIE PRZYSZŁOŚCI. (Polish)
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Source: Business Informatics / Informatyka Ekonomiczna; 2012, Vol. 2 Issue 24, p91-103, 13p
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Source: Bibliogr. przy rozdz. Indeks.
Subject Terms: Architektura komputerów, Przetwarzanie równoległe (informatyka)
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Authors: KRZESAJ, Marcin
Source: Scientific Papers of Silesian University of Technology. Organization & Management / Zeszyty Naukowe Politechniki Slaskiej. Seria Organizacji i Zarzadzanie; 2024, Issue 197, p425-442, 18p
Subject Terms: WORLD Wide Web, WEBSITES, INFORMATION architecture
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Authors:
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Subject Terms: klasifikace procesorů, architektura procesorů, jazyk pro popis architektur, ADL, procesor, mikrokontrolér, MCS51, zřetězené zpracování, hazard, modelování, simulace, Codasip, CodAL, processor classification, processor architecture, architecture description languages, processor, microcontroller, pipeline, modeling, simulation
Time: 8051
File Description: application/pdf; text/html
Relation: KRŮPA, T. Vytvoření modelu procesoru 8051 [online]. Brno: Vysoké učení technické v Brně. Fakulta informačních technologií. 2014.; 79794; http://hdl.handle.net/11012/56513
Availability: http://hdl.handle.net/11012/56513
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File Description: application/pdf
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Alternate Title: ARCHITEKTURA CHMURY OBLICZENIOWEJ DLA APLIKACJI I SERWISÓW LOGISTYCZNYCH. (Polish)
Authors:
Source: Polish Journal of Management Studies; 2013, Vol. 8, p132-140, 9p
Subject Terms: CLOUD computing, DISTRIBUTED computing, CLOUD storage, SOFTWARE as a service
Company/Entity: UNIWERSYTET Wroclawski
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Authors:
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Source: Bibliografia przy rozdziałach. Indeks.
Subject Terms: Architektura komputerów, Komputery -- projektowanie i konstrukcja
Other Title: Computer organisation and architecture
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Authors: et al.
Source: Museology & Cultural Heritage / Muzeologia a Kulturne Dedicstvo; 2025, Vol. 13 Issue 1, p113-137, 25p
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Authors:
Source: Computer Networks (9783642388644); 2013, p312-322, 11p
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Alternate Title: ARCHITECTURE OF THE BLOCKCHAIN 2.0. (English)
Authors: Sitarska-Buba, Monika
Source: Business Informatics / Informatyka Ekonomiczna; 2018, Vol. 4 Issue 50, p135-147, 13p
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Authors:
Source: Systémová Integrace; 2012, Vol. 19 Issue 4, p7-24, 18p
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Subject Terms: Computer, Počítač, Procesor, Predikce skoků, Paměť cache, Architecture, Branch prediction, Pipelining, Architektura, Cache memory, Processor, Instruction, Instrukce
File Description: application/pdf; text/html
Access URL: http://hdl.handle.net/11012/187521
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Subject Terms: TRIPS, Tera-op Reliable Intelligently Adaptive Processing System, EDGE, Explicit Data Graph Execution, procesorová architektura, paralelizmus, paralelní výpočty, polymorfní procesor, processor architecture, parallelism, parallel computation, polymorph processor
File Description: 1977663 bytes; application/pdf; application/octet-stream; text/plain; image/jpeg; downloadable_files_count: 5
Relation: OSD002; https://hdl.handle.net/10084/87594; S2724; KRU255_FEI_B2647_2612R025_2011
Availability: https://hdl.handle.net/10084/87594
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