Search Results - acm: c.: computer systems organisation/c.1: processor architecture/c.1.4: parallel architecture

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  1. 1

    Towards a New Processor Architecture. ; Vers une nouvelle Architecture de Processeurs

    Authors: Vincent, Pierre Landru, Jacques Ecole nationale supérieure Mines-Télécom Lille Douai (IMT Nord Europe) et al.

    Contributors: Vincent, Pierre Landru, Jacques Ecole nationale supérieure Mines-Télécom Lille Douai (IMT Nord Europe) et al.

    Source: https://hal.science/hal-05117313 ; 2025.

    Subject Terms: silicon, parallel, serial, RISC, photonics, computer, optronics, optics, processor, fiber, laser, digital, silicium, parallèle, série, processeur, photonique, ordinateur, optronique, optique, numérique, fibre, ACM: B.: Hardware, ACM: C.: Computer Systems Organization, [INFO]Computer Science [cs], [PHYS]Physics [physics]

    Availability: https://hal.science/hal-05117313
    https://hal.science/hal-05117313v2/document
    https://hal.science/hal-05117313v2/file/frParalSerieRiscV1.pdf

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  2. 2

    Covariance tracking: architecture optimizations for embedded systems

    Authors: Romero, Andrés Lacassagne, Lionel Gouiffès, Michèle et al.

    Contributors: Romero, Andrés Lacassagne, Lionel Gouiffès, Michèle et al.

    Source: ISSN: 1687-6172.

    Subject Terms: covariance-tracking, real-time image processing, SIMD, SSE, AVX, Neon, ACM: I.: Computing Methodologies/I.4: IMAGE PROCESSING AND COMPUTER VISION/I.4.8: Scene Analysis/I.4.8.2: Motion, ACM: I.: Computing Methodologies/I.4: IMAGE PROCESSING AND COMPUTER VISION/I.4.8: Scene Analysis/I.4.8.12: Tracking, ACM: I.: Computing Methodologies/I.4: IMAGE PROCESSING AND COMPUTER VISION/I.4.7: Feature Measurement/I.4.7.1: Invariants, ACM: I.: Computing Methodologies/I.4: IMAGE PROCESSING AND COMPUTER VISION/I.4.7: Feature Measurement/I.4.7.2: Moments, ACM: I.: Computing Methodologies/I.4: IMAGE PROCESSING AND COMPUTER VISION/I.4.7: Feature Measurement/I.4.7.5: Texture, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.4: Parallel Architectures/C.1.4.1: Mobile processors, ACM: D.: Software/D.3: PROGRAMMING LANGUAGES/D.3.4: Processors/D.3.4.6: Optimization, [INFO.INFO-DS]Computer Science [cs]/Data Structures and Algorithms [cs.DS], [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [SPI.AUTO]Engineering Sciences [physics]/Automatic, [SPI.SIGNAL]Engineering Sciences [physics]/Signal and Image processing, [INFO.INFO-AO]Computer Science [cs]/Computer Arithmetic, [INFO.INFO-DC]Computer Science [cs]/Distributed, Parallel, and Cluster Computing [cs.DC], [INFO.INFO-SE]Computer Science [cs]/Software Engineering [cs.SE], [INFO.INFO-DM]Computer Science [cs]/Discrete Mathematics [cs.DM], [INFO.INFO-RB]Computer Science [cs]/Robotics [cs.RO], [INFO.INFO-TI]Computer Science [cs]/Image Processing [eess.IV], [INFO.INFO-TS]Computer Science [cs]/Signal and Image Processing, [INFO.INFO-CV]Computer Science [cs]/Computer Vision and Pattern Recognition [cs.CV]

    Availability: https://inria.hal.science/hal-01094903
    https://inria.hal.science/hal-01094903v1/document
    https://inria.hal.science/hal-01094903v1/file/Eurasip%202014-12.pdf
    https://doi.org/10.1186/1687-6180-2014-175

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  3. 3

    High Level Transforms for SIMD and Low-Level Computer Vision Algorithms

    Authors: Lacassagne, Lionel Etiemble, Daniel Zahraee, Hassan et al.

    Contributors: Lacassagne, Lionel Etiemble, Daniel Zahraee, Hassan et al.

    Source: Symposium on Principles and Practice of Parallel Programming / WPMVP ; https://inria.hal.science/hal-01094906 ; Symposium on Principles and Practice of Parallel Programming / WPMVP, Feb 2014, Orlando, Florida, United States. pp.8, ⟨10.1145/2568058.2568067⟩ ; https://sites.google.com/site/ppopp2014/

    Subject Terms: Intel SSE & XeonPhi, SIMD, High Level Transforms, ARM Neon, IBM Altivec, code optimization, 2D stencil, low-level computer vision and image processing algorithms, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.1: Single Data Stream Architectures, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.4: Parallel Architectures, ACM: D.: Software/D.1: PROGRAMMING TECHNIQUES/D.1.3: Concurrent Programming/D.1.3.1: Parallel programming, ACM: D.: Software/D.3: PROGRAMMING LANGUAGES/D.3.4: Processors/D.3.4.1: Compilers, ACM: D.: Software/D.3: PROGRAMMING LANGUAGES/D.3.4: Processors/D.3.4.6: Optimization, ACM: I.: Computing Methodologies/I.4: IMAGE PROCESSING AND COMPUTER VISION/I.4.7: Feature Measurement, [INFO.INFO-DS]Computer Science [cs]/Data Structures and Algorithms [cs.DS], [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [INFO.INFO-SE]Computer Science [cs]/Software Engineering [cs.SE], [INFO.INFO-DM]Computer Science [cs]/Discrete Mathematics [cs.DM], [INFO.INFO-RB]Computer Science [cs]/Robotics [cs.RO], [INFO.INFO-TI]Computer Science [cs]/Image Processing [eess.IV], [INFO.INFO-TS]Computer Science [cs]/Signal and Image Processing, [INFO.INFO-CV]Computer Science [cs]/Computer Vision and Pattern Recognition [cs.CV], [SPI.AUTO]Engineering Sciences [physics]/Automatic, [SPI.SIGNAL]Engineering Sciences [physics]/Signal and Image processing, [INFO.INFO-AO]Computer Science [cs]/Computer Arithmetic, [INFO.INFO-DC]Computer Science [cs]/Distributed, Parallel, and Cluster Computing [cs.DC]

    Subject Geographic: Orlando, Florida, United States

    Availability: https://inria.hal.science/hal-01094906
    https://inria.hal.science/hal-01094906v1/document
    https://inria.hal.science/hal-01094906v1/file/simd-140122.pdf
    https://doi.org/10.1145/2568058.2568067

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  4. 4

    Distributed Architecture for Resource Management in Large Scale Grids

    Authors: Jeanvoine, Emmanuel Rilling, Louis Morin, Christine et al.

    Contributors: Jeanvoine, Emmanuel Rilling, Louis Morin, Christine et al.

    Source: https://inria.hal.science/inria-00001066 ; [Research Report] PI 1775, 2006, pp.13.

    Subject Terms: Grid computing, distributed system, peer-to-peer overlay networks, resource allocation, self-healing \\ Grille de calcul, système distribué, réseaux logiques pair-à-pair, allocation de ressources, auto-réparation, ACM: C.: Computer Systems Organization/C.2: COMPUTER-COMMUNICATION NETWORKS/C.2.4: Distributed Systems, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.4: Parallel Architectures, [INFO.INFO-OH]Computer Science [cs]/Other [cs.OH]

    Relation: Report N°: PI 1775

    Availability: https://inria.hal.science/inria-00001066
    https://inria.hal.science/inria-00001066v1/document
    https://inria.hal.science/inria-00001066v1/file/PI-1775.pdf

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  5. 5

    From Scilab to Multicore Embedded Systems: Algorithms and Methodologies

    Authors: Goulas, George Alefragis, Panayiotis Voros, Nikolaos S. et al.

    Contributors: Goulas, George Alefragis, Panayiotis Voros, Nikolaos S. et al.

    Source: Proceedings of the IEEE International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (IC-SAMOS 2012 ; https://inria.hal.science/hal-00752615 ; Proceedings of the IEEE International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (IC-SAMOS 2012, Jul 2012, Samos, Greece

    Subject Terms: ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.4: Parallel Architectures, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

    Subject Geographic: Samos, Greece

    Availability: https://inria.hal.science/hal-00752615

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  6. 6

    Parallel Evaluation of Hopfield Neural Networks

    Authors: Eiche, Antoine Chillet, Daniel Pillement, Sébastien et al.

    Contributors: Eiche, Antoine Chillet, Daniel Pillement, Sébastien et al.

    Source: NCTA, International Conference on Neural Computation Theory and Applications ; https://inria.hal.science/hal-00650633 ; NCTA, International Conference on Neural Computation Theory and Applications, Oct 2011, Paris, France

    Subject Terms: ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.3: Other Architecture Styles/C.1.3.7: Neural nets

    Subject Geographic: Paris, France

    Availability: https://inria.hal.science/hal-00650633

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  7. 7

    Dynamic sharing of a multiple access channel

    Authors: Bienkowski, Marcin Klonowski, Marek Korzeniowski, Miroslaw et al.

    Contributors: Bienkowski, Marcin Klonowski, Marek Korzeniowski, Miroslaw et al.

    Source: 27th International Symposium on Theoretical Aspects of Computer Science - STACS 2010
    https://inria.hal.science/inria-00457096
    27th International Symposium on Theoretical Aspects of Computer Science - STACS 2010, Inria Nancy Grand Est & Loria, Mar 2010, Nancy, France. pp.83-94

    Subject Terms: distributed algorithms, multiple access channel, mutual exclusion, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.4: Parallel Architectures, ACM: C.: Computer Systems Organization/C.2: COMPUTER-COMMUNICATION NETWORKS/C.2.1: Network Architecture and Design, ACM: F.: Theory of Computation/F.2: ANALYSIS OF ALGORITHMS AND PROBLEM COMPLEXITY/F.2.2: Nonnumerical Algorithms and Problems, [INFO.INFO-DS]Computer Science [cs]/Data Structures and Algorithms [cs.DS]

    Subject Geographic: Nancy, France

    Relation: inria-00457096; https://inria.hal.science/inria-00457096; https://inria.hal.science/inria-00457096/document; https://inria.hal.science/inria-00457096/file/bienkowski.pdf

    Availability: https://inria.hal.science/inria-00457096
    https://inria.hal.science/inria-00457096/document
    https://inria.hal.science/inria-00457096/file/bienkowski.pdf

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  8. 8

    Parameter Exploration to Improve Performance of Memristor-Based Neuromorphic Architectures

    Authors: Shahsavari, Mahyar Boulet, Pierre Centre de Recherche en Informatique, Signal et Automatique de Lille - UMR 9189 (CRIStAL) et al.

    Contributors: Shahsavari, Mahyar Boulet, Pierre Centre de Recherche en Informatique, Signal et Automatique de Lille - UMR 9189 (CRIStAL) et al.

    Source: ISSN: 2332-7766 ; IEEE Transactions on Multi-Scale Computing Systems ; https://hal.science/hal-01615032 ; IEEE Transactions on Multi-Scale Computing Systems, 2017, Oct.-Dec. 1 2018, 4 (4), ⟨10.1109/TMSCS.2017.2761231⟩ ; http://ieeexplore.ieee.org/document/8063353/.

    Subject Terms: Neuromorphic Computing, Parameter Evaluations, Spiking Neural Networks, Unsupervised Learning, Memristor, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.3: Other Architecture Styles/C.1.3.7: Neural nets, [INFO.INFO-ES]Computer Science [cs]/Embedded Systems, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [INFO.INFO-ET]Computer Science [cs]/Emerging Technologies [cs.ET], [INFO.INFO-DC]Computer Science [cs]/Distributed, Parallel, and Cluster Computing [cs.DC], [INFO.INFO-NE]Computer Science [cs]/Neural and Evolutionary Computing [cs.NE]

    Availability: https://hal.science/hal-01615032
    https://hal.science/hal-01615032/document
    https://hal.science/hal-01615032/file/TMSCSSI-2016-10-0051.R1-main.pdf
    https://doi.org/10.1109/TMSCS.2017.2761231

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  9. 9

    EdgeMORE: improving resource allocation with multiple options from tenants

    Authors: Araldo, Andrea Stefano, Alessandro, Di Di Stefano, Antonella et al.

    Contributors: Araldo, Andrea Stefano, Alessandro, Di Di Stefano, Antonella et al.

    Source: CCNC 2020: 17th Consumer Communications & Networking Conference ; https://hal.science/hal-02459433 ; CCNC 2020: 17th Consumer Communications & Networking Conference, Jan 2020, Las Vegas, United States. pp.1-6, ⟨10.1109/CCNC46108.2020.9045173⟩

    Subject Terms: Cloud-edge offloading, Resource allocation, Edge computing, ACM: C.: Computer Systems Organization/C.2: COMPUTER-COMMUNICATION NETWORKS/C.2.1: Network Architecture and Design/C.2.1.3: Distributed networks, ACM: C.: Computer Systems Organization/C.2: COMPUTER-COMMUNICATION NETWORKS/C.2.4: Distributed Systems, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.4: Parallel Architectures/C.1.4.0: Distributed architectures, [INFO.INFO-NI]Computer Science [cs]/Networking and Internet Architecture [cs.NI]

    Subject Geographic: Las Vegas, United States

    Availability: https://hal.science/hal-02459433
    https://hal.science/hal-02459433v1/document
    https://hal.science/hal-02459433v1/file/_CCNC2020__EdgeMore_mproving_resource_allocation_with_multiple_options_from_tenants.pdf
    https://doi.org/10.1109/CCNC46108.2020.9045173

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  10. 10

    Procédé de synthèse de circuits, dispositif et programme d’ordinateur associés

    Authors: Alias, Christophe Plesco, Alexandru Compilation and embedded computing systems (COMPSYS) et al.

    Contributors: Alias, Christophe Plesco, Alexandru Compilation and embedded computing systems (COMPSYS) et al.

    Source: https://inria.hal.science/hal-01096129 ; France, N° de brevet: FR1453308. 2014.

    Subject Terms: FPGA, réseaux de processus, Synthèse de circuits haut-niveau (HLS), ACM: B.: Hardware, ACM: D.: Software/D.3: PROGRAMMING LANGUAGES, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.4: Parallel Architectures, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [INFO.INFO-DC]Computer Science [cs]/Distributed, Parallel, and Cluster Computing [cs.DC], [INFO.INFO-PL]Computer Science [cs]/Programming Languages [cs.PL], [INFO.INFO-ES]Computer Science [cs]/Embedded Systems

    Relation: Patent N°: FR1453308

    Availability: https://inria.hal.science/hal-01096129

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  11. 11

    Contributions to Program Optimization and High-Level Synthesis ; Contributions à l'optimisation de programmes et à la synthèse de circuits haut-niveau

    Authors: Alias, Christophe CASH - Compilation and Analysis, Software and Hardware (CASH) Centre Inria de l'Université Grenoble Alpes et al.

    Contributors: Alias, Christophe CASH - Compilation and Analysis, Software and Hardware (CASH) Centre Inria de l'Université Grenoble Alpes et al.

    Source: https://inria.hal.science/tel-02151877 ; Hardware Architecture [cs.AR]. ENS de Lyon, 2019.

    Subject Terms: High-Level Synthesis, Compilation Techniques, Automatic Parallelization, Compilation, Parallélisation automatique, Synthèse haut-niveau, FPGA, ACM: B.: Hardware, ACM: B.: Hardware/B.6: LOGIC DESIGN/B.6.3: Design Aids/B.6.3.0: Automatic synthesis, ACM: B.: Hardware/B.6: LOGIC DESIGN/B.6.3: Design Aids/B.6.3.2: Optimization, ACM: D.: Software/D.3: PROGRAMMING LANGUAGES/D.3.4: Processors/D.3.4.1: Compilers, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.4: Parallel Architectures, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [INFO.INFO-DC]Computer Science [cs]/Distributed, Parallel, and Cluster Computing [cs.DC], [INFO.INFO-PL]Computer Science [cs]/Programming Languages [cs.PL]

    Availability: https://inria.hal.science/tel-02151877
    https://inria.hal.science/tel-02151877v2/document
    https://inria.hal.science/tel-02151877v2/file/hdr-alias.pdf

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  12. 12

    N2S3, an Open-Source Scalable Spiking Neuromorphic Hardware Simulator

    Authors: Boulet, Pierre Devienne, Philippe Falez, Pierre et al.

    Contributors: Boulet, Pierre Devienne, Philippe Falez, Pierre et al.

    Source: https://hal.science/hal-01432133 ; [Research Report] Université de Lille 1, Sciences et Technologies; CRIStAL UMR 9189. 2017.

    Subject Terms: simulation, neuromorphic architecture, SNN, SPiking neural networks, ACM: B.: Hardware/B.6: LOGIC DESIGN/B.6.3: Design Aids/B.6.3.3: Simulation, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.3: Other Architecture Styles/C.1.3.7: Neural nets, [INFO.INFO-NE]Computer Science [cs]/Neural and Evolutionary Computing [cs.NE], [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [INFO.INFO-ET]Computer Science [cs]/Emerging Technologies [cs.ET], [INFO.INFO-DC]Computer Science [cs]/Distributed, Parallel, and Cluster Computing [cs.DC]

    Availability: https://hal.science/hal-01432133
    https://hal.science/hal-01432133v2/document
    https://hal.science/hal-01432133v2/file/n2s3.pdf

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  13. 13

    Parallel LDPC Decoding on the Cell/B.E. Processor

    Authors: Falcão, Gabriel Sousa, Leonel Silva, Vitor et al.

    Contributors: Falcão, Gabriel Sousa, Leonel Silva, Vitor et al.

    Source: HiPEAC 2009 - High Performance and Embedded Architectures and Compilers ; https://hal.inria.fr/inria-00446368 ; HiPEAC 2009 - High Performance and Embedded Architectures and Compilers, Jan 2009, Paphos, Cyprus. ⟨10.1007/978-3-540-92990-1_28⟩

    Subject Terms: ACM: B.: Hardware/B.2: ARITHMETIC AND LOGIC STRUCTURES, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES, ACM: D.: Software/D.3: PROGRAMMING LANGUAGES/D.3.4: Processors, [INFO.INFO-OH]Computer Science [cs]/Other [cs.OH], [INFO.INFO-ES]Computer Science [cs]/Embedded Systems

    Subject Geographic: Paphos, Cyprus

    Relation: inria-00446368; https://hal.inria.fr/inria-00446368

    Availability: https://hal.inria.fr/inria-00446368
    https://doi.org/10.1007/978-3-540-92990-1_28

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  14. 14

    Implementing Wilson-Dirac Operator on the Cell Broadband Engine

    Authors: Ibrahim, Khaled Z. Bodin, François Compilation, parallel architectures and system (CAPS) et al.

    Contributors: Ibrahim, Khaled Z. Bodin, François Compilation, parallel architectures and system (CAPS) et al.

    Source: https://inria.hal.science/inria-00203478 ; [Research Report] PI 1880, 2007, pp.23.

    Subject Terms: IBM Cell BE, Vectorization, SIMD, Lattice QCD, Parallel Algorithms, Wilson-Dirac, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

    Relation: Report N°: PI 1880

    Availability: https://inria.hal.science/inria-00203478
    https://inria.hal.science/inria-00203478v1/document
    https://inria.hal.science/inria-00203478v1/file/PI-1880.pdf

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  15. 15

    A Novel Approach to Multiagent based Scheduling for Multicore Architecture.

    Authors: Muneeswari, G. Ahila, A. Sobitha Shunmuganathan, K. L.

    Source: GSTF Journal on Computing; 2011, Vol. 1 Issue 2, p184-189, 6p

    Subject Terms: MULTICORE processors, PARALLEL computers, COMPUTER operating systems, MULTIAGENT systems, ALGORITHMS

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  16. 16

    A continuation-based noninterruptible multithreading processor architecture.

    Authors: Amamiya, Satoshi Amamiya, Makoto Hasegawa, Ryuzo et al.

    Source: Journal of Supercomputing; Feb2009, Vol. 47 Issue 2, p228-252, 25p, 18 Diagrams, 1 Chart, 10 Graphs

    Subject Terms: INTEGRATED circuits, SIMULTANEOUS multithreading processors, COMPUTER architecture, COMPUTERS, COMPUTER operating systems, COMPUTER software, COMPUTER programming

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  17. 17

    Security and Safety Concerns in Air Taxis: A Systematic Literature Review

    Authors: Isadora Garcia Ferrão David Espes Catherine Dezan et al.

    Contributors: Isadora Garcia Ferrão David Espes Catherine Dezan et al.

    Source: Sensors (Basel)
    Sensors, Vol 22, Iss 18, p 6875 (2022)
    Sensors; Volume 22; Issue 18; Pages: 6875

    Subject Terms: ACM: C.: Computer Systems Organization/C.2: COMPUTER-COMMUNICATION NETWORKS/C.2.4: Distributed Systems, air taxi architecture, Aircraft, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.4: Parallel Architectures/C.1.4.1: Mobile processors, Chemical technology, 05 social sciences, TP1-1185, Article, [INFO.INFO-MC]Computer Science [cs]/Mobile Computing, [INFO.INFO-CR]Computer Science [cs]/Cryptography and Security [cs.CR], air taxi security, air taxi safety, 11. Sustainability, 0502 economics and business, Humans, Safety

    File Description: application/pdf

    Access URL: https://pubmed.ncbi.nlm.nih.gov/36146224
    https://doaj.org/article/6ede3995254045d2ae6cd72c94932ffc

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  18. 18

    Hybrid Super/Subthreshold Design of a Low Power Scalable-Throughput FFT Architecture

    Authors: Henry, Michael B. Nazhandali, Leyla Virginia Polytechnic Institute and State University Blacksburg et al.

    Contributors: Henry, Michael B. Nazhandali, Leyla Virginia Polytechnic Institute and State University Blacksburg et al.

    Source: HiPEAC 2009 - High Performance and Embedded Architectures and Compilers ; https://hal.inria.fr/inria-00446294 ; HiPEAC 2009 - High Performance and Embedded Architectures and Compilers, Jan 2009, Paphos, Cyprus. ⟨10.1007/978-3-540-92990-1_21⟩

    Subject Terms: ACM: B.: Hardware/B.2: ARITHMETIC AND LOGIC STRUCTURES, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES, ACM: D.: Software/D.3: PROGRAMMING LANGUAGES/D.3.4: Processors, [INFO.INFO-OH]Computer Science [cs]/Other [cs.OH], [INFO.INFO-ES]Computer Science [cs]/Embedded Systems

    Subject Geographic: Paphos, Cyprus

    Relation: inria-00446294; https://hal.inria.fr/inria-00446294

    Availability: https://hal.inria.fr/inria-00446294
    https://doi.org/10.1007/978-3-540-92990-1_21

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  19. 19

    Processing while routing: a network-on-chip-based parallel system.

    Authors: Fernandes, S. R. Oliveira, B. C. Costa, M. et al.

    Source: IET Computers & Digital Techniques (Institution of Engineering & Technology); Sep2009, Vol. 3 Issue 5, p525-538, 14p, 9 Diagrams, 2 Charts, 10 Graphs

    Subject Terms: COMPUTER architecture, NETWORK routers, SYSTEMS development, COMPUTER input-output equipment, COMPUTER systems

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  20. 20

    CASH Design Space Exploration

    Authors: He, Liqiang Dolbeau, Romain Seznec, André et al.

    Contributors: He, Liqiang Dolbeau, Romain Seznec, André et al.

    Source: https://inria.hal.science/inria-00116799 ; [Research Report] PI 1815, 2006, pp.59.

    Subject Terms: CASH, design space exploration, performance, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

    Relation: Report N°: PI 1815

    Availability: https://inria.hal.science/inria-00116799
    https://inria.hal.science/inria-00116799/document
    https://inria.hal.science/inria-00116799/file/PI-1815.pdf

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