Search Results - acm: c.: computer systems organisation/c.1: processor architectural/c.1.4: parallel architectural

Micro-architectural simulation of embedded core heterogeneity with gem5 and McPAT

Authors: Endo, F.A. Couroussé, Damien Charles, H.-P. et al.

Contributors: Endo, F.A. Couroussé, Damien Charles, H.-P. et al.

Source: RAPIDO '15 Proceedings of the 2015 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools ; https://cea.hal.science/cea-01818887 ; RAPIDO '15 Proceedings of the 2015 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools, Jan 2015, Amsterdam, Netherlands. ⟨10.1145/2693433.2693440⟩

Subject Terms: ACM: I.: Computing Methodologies/I.6: SIMULATION AND MODELING/I.6.7: Simulation Support Systems, ACM: I.: Computing Methodologies/I.6: SIMULATION AND MODELING/I.6.7: Simulation Support Systems/I.6.7.0: Environments, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.1: Single Data Stream Architectures, [INFO]Computer Science [cs]

Subject Geographic: Amsterdam, Netherlands

Availability: https://cea.hal.science/cea-01818887
https://doi.org/10.1145/2693433.2693440

Dynamic Thermal Management via Architectural Adaptation.

Authors: Jayaseelan, Ramkumar Mitra, Tulika

Source: DAC: Annual ACM/IEEE Design Automation Conference; Jul2009, p484-489, 6p, 3 Diagrams, 4 Graphs

Subject Terms: INTEGRATED circuit design, INTEGRATED circuit verification, SYSTEMS development, SYSTEMS engineering, COMPUTER systems, PARALLEL programming, TEMPERATURE measurements

HMP-ASIPs: heterogeneous multi-pipeline application-specific instruction-set processors.

Authors: Radhakrishnan, S. Guo, H. Parameswaran, S. et al.

Source: IET Computers & Digital Techniques (Institution of Engineering & Technology); Jan2009, Vol. 3 Issue 1, p94-108, 15p, 13 Diagrams, 4 Charts, 3 Graphs

Subject Terms: COMPUTER architecture, ARCHITECTURAL designs, ARCHITECTURE, INDUSTRIAL design, SET (Computer network protocol)

Hardware Architectural Support for Control Systems and Sensor Processing.

Authors: VYAS, SUDHANSHU GUPTE, ADWAIT GILL, CHRISTOPHER D. et al.

Source: ACM Transactions on Embedded Computing Systems; Sep2013, Vol. 13 Issue 2, p1-25, 25p

Subject Terms: COMPUTER input-output equipment, COMPUTER architecture, AUTOMATIC control systems, SENSOR networks, DIGITAL signal processing, ALGORITHMS, PID controllers

Concurrency in Transactional Memory

Authors: Gramoli, Vincent The University of Sydney Data61 Canberra (CSIRO) et al.

Contributors: Gramoli, Vincent The University of Sydney Data61 Canberra (CSIRO) et al.

Source: https://hal.archives-ouvertes.fr/tel-01522826 ; Distributed, Parallel, and Cluster Computing [cs.DC]. UPMC - Sorbonne University, 2015.

Subject Terms: Software transactional memory, multicore, manycore, transaction polymorphism, elastic transactions, Mémoire transactionnelle, ACM: D.: Software/D.3: PROGRAMMING LANGUAGES/D.3.3: Language Constructs and Features, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.4: Parallel Architectures, ACM: D.: Software/D.1: PROGRAMMING TECHNIQUES/D.1.3: Concurrent Programming, [INFO.INFO-DC]Computer Science [cs]/Distributed, Parallel, and Cluster Computing [cs.DC]

Relation: tel-01522826; https://hal.archives-ouvertes.fr/tel-01522826; https://hal.archives-ouvertes.fr/tel-01522826/document; https://hal.archives-ouvertes.fr/tel-01522826/file/hdr-v4.pdf; https://hal.archives-ouvertes.fr/tel-01522826/file/chronology%20%281%29.pdf; https://hal.archives-ouvertes.fr/tel-01522826/file/chronology.pdf; https://hal.archives-ouvertes.fr/tel-01522826/file/cmp.pdf; https://hal.archives-ouvertes.fr/tel-01522826/file/complexity%20%281%29.pdf; https://hal.archives-ouvertes.fr/tel-01522826/file/complexity.pdf; https://hal.archives-ouvertes.fr/tel-01522826/file/composition2%20%281%29.pdf; https://hal.archives-ouvertes.fr/tel-01522826/file/composition2.pdf; https://hal.archives-ouvertes.fr/tel-01522826/file/histories%20%281%29.pdf; https://hal.archives-ouvertes.fr/tel-01522826/file/histories.pdf; https://hal.archives-ouvertes.fr/tel-01522826/file/histories2%20%281%29.pdf; https://hal.archives-ouvertes.fr/tel-01522826/file/histories2.pdf; https://hal.archives-ouvertes.fr/tel-01522826/file/lf-vs-pstm-16384%20%281%29.pdf; https://hal.archives-ouvertes.fr/tel-01522826/file/lf-vs-pstm-16384.pdf; https://hal.archives-ouvertes.fr/tel-01522826/file/lf-vs-stm-16384%20%281%29.pdf; https://hal.archives-ouvertes.fr/tel-01522826/file/lf-vs-stm-16384.pdf; https://hal.archives-ouvertes.fr/tel-01522826/file/multiprocessor.pdf; https://hal.archives-ouvertes.fr/tel-01522826/file/skiplist_diagram%20%281%29.pdf; https://hal.archives-ouvertes.fr/tel-01522826/file/skiplist_diagram.pdf; https://hal.archives-ouvertes.fr/tel-01522826/file/tree1%20%281%29.pdf; https://hal.archives-ouvertes.fr/tel-01522826/file/tree1.pdf

Availability: https://hal.archives-ouvertes.fr/tel-01522826
https://hal.archives-ouvertes.fr/tel-01522826/document
https://hal.archives-ouvertes.fr/tel-01522826/file/hdr-v4.pdf
https://hal.archives-ouvertes.fr/tel-01522826/file/chronology%20%281%29.pdf
https://hal.archives-ouvertes.fr/tel-01522826/file/chronology.pdf
https://hal.archives-ouvertes.fr/tel-01522826/file/cmp.pdf
https://hal.archives-ouvertes.fr/tel-01522826/file/complexity%20%281%29.pdf
https://hal.archives-ouvertes.fr/tel-01522826/file/complexity.pdf
https://hal.archives-ouvertes.fr/tel-01522826/file/composition2%20%281%29.pdf
https://hal.archives-ouvertes.fr/tel-01522826/file/composition2.pdf

Parallel LDPC Decoding on the Cell/B.E. Processor

Authors: Falcão, Gabriel Sousa, Leonel Silva, Vitor et al.

Contributors: Falcão, Gabriel Sousa, Leonel Silva, Vitor et al.

Source: HiPEAC 2009 - High Performance and Embedded Architectures and Compilers ; https://hal.inria.fr/inria-00446368 ; HiPEAC 2009 - High Performance and Embedded Architectures and Compilers, Jan 2009, Paphos, Cyprus. ⟨10.1007/978-3-540-92990-1_28⟩

Subject Terms: ACM: B.: Hardware/B.2: ARITHMETIC AND LOGIC STRUCTURES, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES, ACM: D.: Software/D.3: PROGRAMMING LANGUAGES/D.3.4: Processors, [INFO.INFO-OH]Computer Science [cs]/Other [cs.OH], [INFO.INFO-ES]Computer Science [cs]/Embedded Systems

Subject Geographic: Paphos, Cyprus

Relation: inria-00446368; https://hal.inria.fr/inria-00446368

Availability: https://hal.inria.fr/inria-00446368
https://doi.org/10.1007/978-3-540-92990-1_28

A simultaneous multithreading processor architecture with predictable timing behavior.

Authors: Siqueira, Hadley Magno Kreutz, Marcio Eduardo

Source: Design Automation for Embedded Systems; Mar2020, Vol. 24 Issue 1, p45-62, 18p

Subject Terms: SIMULTANEOUS multithreading processors, COMPUTER systems, CYBER physical systems, DETERMINISTIC algorithms, ARCHITECTURAL design, SYSTEMS engineering

XPXM/C: a taxonomy of processor coupling techniques.

Authors: Artym, R. Mason, J.S.

Source: IEE Proceedings: Part E: Computers & Digital Techniques; May1988, Vol. 135 Issue 3, p173-180, 8p

Parallel Programming Patterns for Multi-Processor SoC: Application to Video Processing.

Authors: PAULIN, PIERRE G. ÖZCAN, ALI ERDEM GAGNÉ, VINCENT et al.

Source: ACM Transactions on Embedded Computing Systems; Mar2013, Vol. 12 Issue Supp 1, p47:1-47:25, 25p

Subject Terms: PARALLEL programming, VIDEO processing, COMPUTER simulation, EMBEDDED computer systems, MULTIPROCESSORS, PARALLEL computers

A Novel Approach to Multiagent based Scheduling for Multicore Architecture.

Authors: Muneeswari, G. Ahila, A. Sobitha Shunmuganathan, K. L.

Source: GSTF Journal on Computing; 2011, Vol. 1 Issue 2, p184-189, 6p

Subject Terms: MULTICORE processors, PARALLEL computers, COMPUTER operating systems, MULTIAGENT systems, ALGORITHMS

Towards a New Processor Architecture. ; Vers une nouvelle Architecture de Processeurs

Authors: Vincent, Pierre Landru, Jacques Ecole nationale supérieure Mines-Télécom Lille Douai (IMT Nord Europe) et al.

Contributors: Vincent, Pierre Landru, Jacques Ecole nationale supérieure Mines-Télécom Lille Douai (IMT Nord Europe) et al.

Source: https://hal.science/hal-05117313 ; 2025.

Subject Terms: silicon, parallel, serial, RISC, photonics, computer, optronics, optics, processor, fiber, laser, digital, silicium, parallèle, série, processeur, photonique, ordinateur, optronique, optique, numérique, fibre, ACM: B.: Hardware, ACM: C.: Computer Systems Organization, [INFO]Computer Science [cs], [PHYS]Physics [physics]

Availability: https://hal.science/hal-05117313
https://hal.science/hal-05117313v2/document
https://hal.science/hal-05117313v2/file/frParalSerieRiscV1.pdf

Energy-Efficient Multiprocessor Systems-on-Chip for Embedded Computing: Exploring Programming Models and Their Architectural Support.

Authors: Poletti, Francesco Poggiali, Antonio Bertozzi, Davide et al.

Source: IEEE Transactions on Computers; May2007, Vol. 56 Issue 5, p606-621, 16p, 7 Black and White Photographs, 8 Diagrams, 6 Charts, 6 Graphs

Subject Terms: MULTIPROCESSORS, COMPUTER programming, PARALLEL programming, PARALLEL processing, EMBEDDED computer systems, ENERGY consumption, MICROELECTRONICS, COMPUTER input-output equipment, INTEGRATED circuits

Architectural support for task scheduling: hardware scheduling for dataflow on NUMA systems.

Authors: Khan, Behram Goodman, Daniel Khan, Salman et al.

Source: Journal of Supercomputing; Jun2015, Vol. 71 Issue 6, p2309-2338, 30p

Subject Terms: DATA flow computing, NON-uniform memory access, COMPUTER software, QUEUEING networks, FIRST in, first out (Queuing theory)

Exploiting Timing Error Resilience in Processor Architecture.

Authors: SARTORI, JOHN KUMAR, RAKESH

Source: ACM Transactions on Embedded Computing Systems; May2013 Supplement 2, Vol. 12, p1-25, 25p

Subject Terms: COMPLEMENTARY metal oxide semiconductor design & construction, MACRO processors, COMPUTER architecture, ERROR rates, ERRORS, MOORE'S law, INDUSTRIAL costs

Development an efficient AXI-interconnect unit between set of customized peripheral devices and an implemented dual-core RISC-V processor.

Authors: Emil, Demyana Hamdy, Mohammed Nagib, Gihan

Source: Journal of Supercomputing; Oct2023, Vol. 79 Issue 15, p17000-17019, 20p

Subject Terms: TELECOMMUNICATION equipment, COMPUTER systems, ARCHITECTURAL design, MULTICORE processors, TAIGAS, CACHE memory

HPC Systems in the Next Decade – What to Expect, When, Where.

Authors: Doglioni, C. Kim, D. Stewart, G.A. et al.

Source: EPJ Web of Conferences; 11/16/2020, Vol. 245, p1-10, 10p

Subject Terms: HIGH performance computing, COMPUTER architecture, WORKFLOW management, COMPUTER software development, INFORMATION retrieval

Multiprocessor platform-based design for multimedia.

Authors: Ammari, A. C. Jemai, A.

Source: IET Computers & Digital Techniques (Institution of Engineering & Technology); Jan2009, Vol. 3 Issue 1, p52-61, 10p, 5 Diagrams, 2 Charts, 2 Graphs

Subject Terms: EMBEDDED computer systems, ARCHITECTURAL designs, COMPUTER architecture, SYSTEMS design, INTEGRATED circuits, APPLICATION-specific integrated circuits

VirtualSoC: A Research Tool for Modern MPSoCs.

Authors: BORTOLOTTI, DANIELE MARONGIU, ANDREA BENINI, LUCA

Source: ACM Transactions on Embedded Computing Systems; Oct2016, Vol. 16 Issue 1, p1-27, 27p

Subject Terms: COMPUTER system design & construction, HIGH performance computing, EMBEDDED computer systems, COMPUTER simulation, COMPUTER operating systems, CENTRAL processing units

Efficient Breadth-First Search on the Cell/BE Processor.

Authors: Scarpazza, Daniele Paolo Villa, Oreste Petrini, Fabrizio

Source: IEEE Transactions on Parallel & Distributed Systems; Oct2008, Vol. 19 Issue 10, p1381-1395, 28p, 3 Black and White Photographs, 5 Charts, 8 Graphs

Subject Terms: MICROPROCESSORS, PARALLEL computer software, COMPUTER software development, BROADBAND communication systems, SOFTWARE architecture, PROGRAM transformation, PARALLEL programs (Computer programs), COMPUTER system design & construction, ALGORITHMS, SYSTEMS software, INTEGRATED circuits, COMPUTER software

Parallel Rendering and Animation of Subdivision Surfaces on the Cell BE Processor.

Authors: Benini, L. Grottesi, R. Morigi, S. et al.

Source: International Journal of Parallel Programming; Aug2011, Vol. 39 Issue 4, p494-521, 28p, 12 Diagrams, 1 Chart, 5 Graphs

Subject Terms: ANIMATION cels, THREE-dimensional imaging, THREE-dimensional display systems, COMPUTER programming, SYSTEMS development, COMPUTER architecture