Search Results - acm: c.: computer systems organisation/c.1: processes architectures*

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  1. 1

    Alignment and Change Propagation between Business Processes and Service-Oriented Architectures

    Authors: Dahman, Karim Charoy, François Godart, Claude et al.

    Contributors: Dahman, Karim Charoy, François Godart, Claude et al.

    Source: 10th International Conference on Services Computing
    https://inria.hal.science/hal-00870721
    10th International Conference on Services Computing, Andrzej M Goscinski, Ephraim Feig, Jun 2013, Santa Clara, United States. pp.168-175, ⟨10.1109/SCC.2013.101⟩

    Subject Terms: ACM: C.: Computer Systems Organization/C.2: COMPUTER-COMMUNICATION NETWORKS/C.2.4: Distributed Systems/C.2.4.1: Distributed applications, [INFO.INFO-NI]Computer Science [cs]/Networking and Internet Architecture [cs.NI]

    Subject Geographic: Santa Clara, United States

    Availability: https://inria.hal.science/hal-00870721
    https://inria.hal.science/hal-00870721v1/document
    https://inria.hal.science/hal-00870721v1/file/SCC2013.pdf
    https://doi.org/10.1109/SCC.2013.101

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  2. 2

    Impact of on-chip network parameters on NUCA cache performances.

    Authors: Bardine, A. Comparetti, M. Foglia, P. et al.

    Source: IET Computers & Digital Techniques (Institution of Engineering & Technology); Sep2009, Vol. 3 Issue 5, p501-512, 12p, 3 Diagrams, 2 Charts, 7 Graphs

    Subject Terms: NETWORK routers, COMPUTER architecture, SYSTEMS development, COMPUTER systems, COMPUTER network architectures

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  3. 3

    Reusing enterprise models to build platform independent computer models.

    Authors: Pazos, Verónica Chalmeta, Ricardo

    Source: Information Systems & e-Business Management; May2017, Vol. 15 Issue 2, p377-421, 45p

    Subject Terms: BUSINESS process management, COMPUTER network architectures, SERVICE-oriented architecture (Computer science), DATA transmission systems, INFORMATION storage & retrieval systems

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  4. 4

    The Multiplicative Power of Consensus Numbers

    Authors: Imbs, Damien Raynal, Michel As Scalable As Possible: foundations of large scale dynamic distributed systems (ASAP) et al.

    Contributors: Imbs, Damien Raynal, Michel As Scalable As Possible: foundations of large scale dynamic distributed systems (ASAP) et al.

    Source: https://inria.hal.science/inria-00454399 ; [Research Report] PI 1949, 2010, pp.17.

    Subject Terms: Asynchronous processes, BG simulation, Consensus number, Distributed computability, Fault-Tolerance, Process crash failure, Reduction algorithm, t-Resilience, k-Set agreement, Shared memory system, Synchronization power, System model, Waitfreedom, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES, [INFO.INFO-OS]Computer Science [cs]/Operating Systems [cs.OS]

    Relation: Report N°: PI 1949

    Availability: https://inria.hal.science/inria-00454399
    https://inria.hal.science/inria-00454399v2/document
    https://inria.hal.science/inria-00454399v2/file/PI-1949.pdf

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  5. 5

    TBES: Template-Based Exploration and Synthesis of Heterogeneous Multiprocessor Architectures on FPGA

    Authors: Corre, Youenn Diguet, Jean-Philippe Heller, Dominique et al.

    Contributors: Corre, Youenn Diguet, Jean-Philippe Heller, Dominique et al.

    Source: ACM Transactions on Embedded Computing Systems. 15:1-27

    Subject Terms: [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES, 13. Climate action, Electronic System Level, 0202 electrical engineering, electronic engineering, information engineering, ACM: B.: Hardware/B.5: REGISTER-TRANSFER-LEVEL IMPLEMENTATION, Multiprocessor, 02 engineering and technology, High-Level Synthesis, ACM: D.: Software/D.2: SOFTWARE ENGINEERING/D.2.2: Design Tools and Techniques, System-on-Chip

    Access URL: https://hal.archives-ouvertes.fr/hal-01172103/document
    https://dblp.uni-trier.de/db/journals/tecs/tecs15.html#CorreDHBL16
    https://hal.archives-ouvertes.fr/hal-01172103
    https://dl.acm.org/doi/10.1145/2816817
    https://doi.org/10.1145/2816817

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  6. 6

    Loosely Time-Triggered Architectures based on Communication-by-Sampling

    Authors: Benveniste, Albert Caspi, Paul Di Natale, Marco et al.

    Contributors: Benveniste, Albert Caspi, Paul Di Natale, Marco et al.

    Source: https://inria.hal.science/inria-00156468 ; [Research Report] PI 1854, 2007, pp.41.

    Subject Terms: Real-time systems, distributed control, time-triggered, loosely time-triggered, MoCC, ACM: D.: Software/D.4: OPERATING SYSTEMS, ACM: C.: Computer Systems Organization/C.3: SPECIAL-PURPOSE AND APPLICATION-BASED SYSTEMS, [INFO.INFO-OH]Computer Science [cs]/Other [cs.OH]

    Relation: Report N°: PI 1854

    Availability: https://inria.hal.science/inria-00156468
    https://inria.hal.science/inria-00156468v1/document
    https://inria.hal.science/inria-00156468v1/file/PI-1854.pdf

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  7. 7

    Synchronous byzantine agreement with nearly a cubic number of communication bits

    Authors: Kowalski, Dariusz R. Mostefaoui, Achour Department of Computer Science Liverpool et al.

    Contributors: Kowalski, Dariusz R. Mostefaoui, Achour Department of Computer Science Liverpool et al.

    Source: ACM symposium on Principles of distributed computing (PODC'13) ; https://hal.science/hal-01151136 ; ACM symposium on Principles of distributed computing (PODC'13), Jul 2013, New-York, United States. pp.84-91, ⟨10.1145/2484239.2484271⟩

    Subject Terms: Agreement problem, Synchronous distributed system, Byzantine process, Message-passing model, Round-based protocol, EIG, Consensus, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.4: Parallel Architectures/C.1.4.0: Distributed architectures, ACM: C.: Computer Systems Organization/C.2: COMPUTER-COMMUNICATION NETWORKS/C.2.4: Distributed Systems, ACM: D.: Software/D.4: OPERATING SYSTEMS/D.4.7: Organization and Design/D.4.7.1: Distributed systems, ACM: D.: Software/D.4: OPERATING SYSTEMS/D.4.5: Reliability/D.4.5.2: Fault-tolerance, ACM: D.: Software/D.4: OPERATING SYSTEMS/D.4.1: Process Management/D.4.1.0: Concurrency, ACM: D.: Software/D.4: OPERATING SYSTEMS/D.4.1: Process Management/D.4.1.5: Synchronization, [INFO]Computer Science [cs], [INFO.INFO-DC]Computer Science [cs]/Distributed, Parallel, and Cluster Computing [cs.DC], [INFO.INFO-DS]Computer Science [cs]/Data Structures and Algorithms [cs.DS]

    Subject Geographic: New-York, United States

    Availability: https://hal.science/hal-01151136
    https://hal.science/hal-01151136v1/document
    https://hal.science/hal-01151136v1/file/podc%20final.pdf
    https://doi.org/10.1145/2484239.2484271

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  8. 8

    Towards a standardised framework for a multi-agent system approach for cooperation in an original design manufacturing company.

    Authors: Lin, Jiun-Shiung Ou-Yang, Chao Juan, Yeh-Chun

    Source: International Journal of Computer Integrated Manufacturing; Jun2009, Vol. 22 Issue 6, p494-514, 21p, 1 Color Photograph, 1 Black and White Photograph, 14 Diagrams

    Subject Terms: COMPUTER integrated manufacturing systems, COMPUTER-aided engineering, POLYNOMIALS, APPROXIMATION theory, COMPUTER network architectures

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  9. 9

    Systemic computation: A model of interacting systems with natural characteristics.

    Authors: Bentley, Peter J.

    Source: International Journal of Parallel, Emergent & Distributed Systems; Apr2007, Vol. 22 Issue 2, p103-121, 19p, 8 Diagrams, 3 Charts

    Subject Terms: COMPUTER architecture, BIOLOGY, COMPUTER systems, ALGORITHMS, ARTIFICIAL neural networks, COMPUTER simulation

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  10. 10

    Optimizing DDR-SDRAM Communications at C-level for Automatically-Generated Hardware Accelerators. An Experience with the Altera C2H HLS Tool.

    Authors: Alias, Christophe Darte, Alain Plesco, Alexandru et al.

    Contributors: Alias, Christophe Darte, Alain Plesco, Alexandru et al.

    Source: https://inria.hal.science/inria-00482035 ; [Research Report] RR-7281, INRIA. 2010, pp.19.

    Subject Terms: High-level synthesis, hardware accelerators, DDR-SDRAM, optimized communications, program transformation, reconfigurable architectures, FPGA, ACM: B.: Hardware/B.4: INPUT/OUTPUT AND DATA COMMUNICATIONS/B.4.1: Data Communications Devices/B.4.1.0: Processors, ACM: B.: Hardware/B.4: INPUT/OUTPUT AND DATA COMMUNICATIONS/B.4.2: Input/Output Devices/B.4.2.0: Channels and controllers, ACM: B.: Hardware/B.7: INTEGRATED CIRCUITS/B.7.1: Types and Design Styles/B.7.1.1: Algorithms implemented in hardware, ACM: B.: Hardware/B.7: INTEGRATED CIRCUITS/B.7.1: Types and Design Styles/B.7.1.3: Input/output circuits, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.3: Other Architecture Styles/C.1.3.0: Adaptable architectures, [INFO.INFO-ES]Computer Science [cs]/Embedded Systems, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [INFO.INFO-PL]Computer Science [cs]/Programming Languages [cs.PL]

    Availability: https://inria.hal.science/inria-00482035
    https://inria.hal.science/inria-00482035v1/document
    https://inria.hal.science/inria-00482035v1/file/RR-7281.pdf

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  11. 11

    Concurrency in Transactional Memory

    Authors: Gramoli, Vincent The University of Sydney Data61 Canberra (CSIRO) et al.

    Contributors: Gramoli, Vincent The University of Sydney Data61 Canberra (CSIRO) et al.

    Source: https://hal.archives-ouvertes.fr/tel-01522826 ; Distributed, Parallel, and Cluster Computing [cs.DC]. UPMC - Sorbonne University, 2015.

    Subject Terms: Software transactional memory, multicore, manycore, transaction polymorphism, elastic transactions, Mémoire transactionnelle, ACM: D.: Software/D.3: PROGRAMMING LANGUAGES/D.3.3: Language Constructs and Features, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.4: Parallel Architectures, ACM: D.: Software/D.1: PROGRAMMING TECHNIQUES/D.1.3: Concurrent Programming, [INFO.INFO-DC]Computer Science [cs]/Distributed, Parallel, and Cluster Computing [cs.DC]

    Relation: tel-01522826; https://hal.archives-ouvertes.fr/tel-01522826; https://hal.archives-ouvertes.fr/tel-01522826/document; https://hal.archives-ouvertes.fr/tel-01522826/file/hdr-v4.pdf; https://hal.archives-ouvertes.fr/tel-01522826/file/chronology%20%281%29.pdf; https://hal.archives-ouvertes.fr/tel-01522826/file/chronology.pdf; https://hal.archives-ouvertes.fr/tel-01522826/file/cmp.pdf; https://hal.archives-ouvertes.fr/tel-01522826/file/complexity%20%281%29.pdf; https://hal.archives-ouvertes.fr/tel-01522826/file/complexity.pdf; https://hal.archives-ouvertes.fr/tel-01522826/file/composition2%20%281%29.pdf; https://hal.archives-ouvertes.fr/tel-01522826/file/composition2.pdf; https://hal.archives-ouvertes.fr/tel-01522826/file/histories%20%281%29.pdf; https://hal.archives-ouvertes.fr/tel-01522826/file/histories.pdf; https://hal.archives-ouvertes.fr/tel-01522826/file/histories2%20%281%29.pdf; https://hal.archives-ouvertes.fr/tel-01522826/file/histories2.pdf; https://hal.archives-ouvertes.fr/tel-01522826/file/lf-vs-pstm-16384%20%281%29.pdf; https://hal.archives-ouvertes.fr/tel-01522826/file/lf-vs-pstm-16384.pdf; https://hal.archives-ouvertes.fr/tel-01522826/file/lf-vs-stm-16384%20%281%29.pdf; https://hal.archives-ouvertes.fr/tel-01522826/file/lf-vs-stm-16384.pdf; https://hal.archives-ouvertes.fr/tel-01522826/file/multiprocessor.pdf; https://hal.archives-ouvertes.fr/tel-01522826/file/skiplist_diagram%20%281%29.pdf; https://hal.archives-ouvertes.fr/tel-01522826/file/skiplist_diagram.pdf; https://hal.archives-ouvertes.fr/tel-01522826/file/tree1%20%281%29.pdf; https://hal.archives-ouvertes.fr/tel-01522826/file/tree1.pdf

    Availability: https://hal.archives-ouvertes.fr/tel-01522826
    https://hal.archives-ouvertes.fr/tel-01522826/document
    https://hal.archives-ouvertes.fr/tel-01522826/file/hdr-v4.pdf
    https://hal.archives-ouvertes.fr/tel-01522826/file/chronology%20%281%29.pdf
    https://hal.archives-ouvertes.fr/tel-01522826/file/chronology.pdf
    https://hal.archives-ouvertes.fr/tel-01522826/file/cmp.pdf
    https://hal.archives-ouvertes.fr/tel-01522826/file/complexity%20%281%29.pdf
    https://hal.archives-ouvertes.fr/tel-01522826/file/complexity.pdf
    https://hal.archives-ouvertes.fr/tel-01522826/file/composition2%20%281%29.pdf
    https://hal.archives-ouvertes.fr/tel-01522826/file/composition2.pdf

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  12. 12

    PRET-C: A new language for programming precision timed architectures

    Authors: Andalam, Sidharta Roop, Partha Girault, Alain et al.

    Contributors: Andalam, Sidharta Roop, Partha Girault, Alain et al.

    Source: https://inria.hal.science/inria-00391621 ; [Research Report] RR-6922, INRIA. 2009, pp.38.

    Subject Terms: Real-time systems, Precision Timed (PRET) Architectures, Synchronous Languages, ACM: B.: Hardware/B.1: CONTROL STRUCTURES AND MICROPROGRAMMING, ACM: C.: Computer Systems Organization/C.3: SPECIAL-PURPOSE AND APPLICATION-BASED SYSTEMS/C.3.2: Real-time and embedded systems, ACM: D.: Software/D.3: PROGRAMMING LANGUAGES/D.3.2: Language Classifications/D.3.2.1: Concurrent, distributed, and parallel languages, [INFO.INFO-ES]Computer Science [cs]/Embedded Systems

    Availability: https://inria.hal.science/inria-00391621
    https://inria.hal.science/inria-00391621v1/document
    https://inria.hal.science/inria-00391621v1/file/rr.pdf

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  13. 13

    Reconfigurable computing: architectures and design methods.

    Authors: Todman, T. J. Constantinides, G. A. Wilton, S. J. E. et al.

    Source: IEE Proceedings -- Computers & Digital Techniques; Mar2005, Vol. 152 Issue 2, p193-207, 15p

    Subject Terms: ADAPTIVE computing systems, COMPUTER systems, COMPUTER architecture, COMPUTER science, SYSTEMS development, SYSTEMS design, INFORMATION technology, COMPUTER industry

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  14. 14

    Robust Architectures for Embedded Wireless Network Control and Actuation.

    Authors: PAJIC, MIROSLAV CHERNOGUZOV, ALEXANDER MANGHARAM, RAHUL

    Source: ACM Transactions on Embedded Computing Systems; Dec2012, Vol. 11 Issue 4, p1-24, 24p

    Subject Terms: ROBUST control, COMPUTER architecture, EMBEDDED computer systems, COMPUTER networks, CLOSED loop systems, COMPUTER network protocols

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  15. 15

    Case for an explicit co-ordination layer in modern business information systems architectures.

    Authors: Warboys, B. C. Greenwood, R. M. Kawalek, P.

    Source: IEE Proceedings -- Software; Jun1999, Vol. 146 Issue 3, p160-166, 7p

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  16. 16

    Dynamic sharing of a multiple access channel

    Authors: Bienkowski, Marcin Klonowski, Marek Korzeniowski, Miroslaw et al.

    Contributors: Bienkowski, Marcin Klonowski, Marek Korzeniowski, Miroslaw et al.

    Source: 27th International Symposium on Theoretical Aspects of Computer Science - STACS 2010
    https://inria.hal.science/inria-00457096
    27th International Symposium on Theoretical Aspects of Computer Science - STACS 2010, Inria Nancy Grand Est & Loria, Mar 2010, Nancy, France. pp.83-94

    Subject Terms: distributed algorithms, multiple access channel, mutual exclusion, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.4: Parallel Architectures, ACM: C.: Computer Systems Organization/C.2: COMPUTER-COMMUNICATION NETWORKS/C.2.1: Network Architecture and Design, ACM: F.: Theory of Computation/F.2: ANALYSIS OF ALGORITHMS AND PROBLEM COMPLEXITY/F.2.2: Nonnumerical Algorithms and Problems, [INFO.INFO-DS]Computer Science [cs]/Data Structures and Algorithms [cs.DS]

    Subject Geographic: Nancy, France

    Relation: inria-00457096; https://inria.hal.science/inria-00457096; https://inria.hal.science/inria-00457096/document; https://inria.hal.science/inria-00457096/file/bienkowski.pdf

    Availability: https://inria.hal.science/inria-00457096
    https://inria.hal.science/inria-00457096/document
    https://inria.hal.science/inria-00457096/file/bienkowski.pdf

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  17. 17

    CA-STAR: a centrally-arbitrated broadcast-and-select star architecture...

    Authors: Yau Pawlikowski, Victor

    Source: Journal of High Speed Networks; 1999, Vol. 8 Issue 3, p173, 21p, 8 Diagrams, 5 Charts, 3 Graphs

    Subject Terms: OPTICAL communications, DATA transmission systems, COMPUTER network architectures

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  18. 18

    HARS: A Hardware-Assisted Runtime Software for embedded many-core architectures

    Authors: Lhuillier, Y. Ojail, M. Guerre, A. et al.

    Contributors: Lhuillier, Y. Ojail, M. Guerre, A. et al.

    Source: ISSN: 1539-9087.

    Subject Terms: B.5.0 [Register-Transfer-Level Implementation]: General, ACM: D.: Software/D.4: OPERATING SYSTEMS/D.4.7: Organization and Design/D.4.7.4: Real-time systems and embedded systems, ACM: D.: Software/D.4: OPERATING SYSTEMS/D.4.1: Process Management, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.4: Parallel Architectures, ACM: B.: Hardware/B.5: REGISTER-TRANSFER-LEVEL IMPLEMENTATION, [INFO]Computer Science [cs]

    Availability: https://cea.hal.science/cea-01818892
    https://doi.org/10.1145/2517311

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  19. 19

    NoC-Based Protection for SoC Time-Driven Attacks

    Authors: Sepulveda, Martha Johanna Diguet, Jean-Philippe Strum, Marius et al.

    Contributors: Sepulveda, Martha Johanna Diguet, Jean-Philippe Strum, Marius et al.

    Source: IEEE Embedded Systems Letters. 7:7-10

    Subject Terms: ACM: B.: Hardware/B.7: INTEGRATED CIRCUITS, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], Channel leakage, multiport memory, common bus, ACM: B.: Hardware/B.7: INTEGRATED CIRCUITS/B.7.1: Types and Design Styles/B.7.1.7: VLSI (very large scale integration), 02 engineering and technology, 3. Good health, Network On Chip, crossbar switch), Security, 0202 electrical engineering, electronic engineering, information engineering, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.2: Multiple Data Stream Architectures (Multiprocessors)/C.1.2.3: Interconnection architectures (e.g, [SPI.SIGNAL]Engineering Sciences [physics]/Signal and Image processing, [SPI.SIGNAL] Engineering Sciences [physics]/Signal and Image processing

    Access URL: https://hal.archives-ouvertes.fr/hal-01083270
    http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6994256
    https://hal.inria.fr/hal-01253500
    http://ieeexplore.ieee.org/document/6994256
    https://ieeexplore.ieee.org/document/6994256
    https://dblp.uni-trier.de/db/journals/esl/esl7.html#SepulvedaDSG15

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  20. 20

    EEA-Aware For Large-Scale Scientific Applications On Heterogeneous Architectures

    Authors: Garcia Henao, John Anderson, John Anderson Garcia Henao Hernandez, Esteban Navaux, Philippe, O.A. et al.

    Contributors: Garcia Henao, John Anderson, John Anderson Garcia Henao Hernandez, Esteban Navaux, Philippe, O.A. et al.

    Source: ACM Student Research Competition at Supercomputing. The International Conference for High Performance Computing, Networking, Storage and Analysis ; https://hal.science/hal-01739585 ; ACM Student Research Competition at Supercomputing. The International Conference for High Performance Computing, Networking, Storage and Analysis, Nov 2016, Salt Lake City, Utah, United States

    Subject Terms: Exascale Computing, Energy Aware, Power Capping, Energy Efficiency, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.4: Parallel Architectures, ACM: D.: Software/D.4: OPERATING SYSTEMS/D.4.8: Performance/D.4.8.2: Monitors, ACM: D.: Software/D.4: OPERATING SYSTEMS/D.4.8: Performance/D.4.8.1: Modeling and prediction, [INFO.INFO-DC]Computer Science [cs]/Distributed, Parallel, and Cluster Computing [cs.DC]

    Subject Geographic: Salt Lake City, Utah, United States

    Availability: https://hal.science/hal-01739585
    https://hal.science/hal-01739585v1/document
    https://hal.science/hal-01739585v1/file/01_EEAaware-SC16-JAGH-poster.pdf

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