Výsledky vyhľadávania - acm: c.: computer systems organisation/c.1: proceso architectures*

Concurrency in Transactional Memory

Autori: Gramoli, Vincent The University of Sydney Data61 Canberra (CSIRO) a ďalší

Prispievatelia: Gramoli, Vincent The University of Sydney Data61 Canberra (CSIRO) a ďalší

Zdroj: https://hal.archives-ouvertes.fr/tel-01522826 ; Distributed, Parallel, and Cluster Computing [cs.DC]. UPMC - Sorbonne University, 2015.

Predmety: Software transactional memory, multicore, manycore, transaction polymorphism, elastic transactions, Mémoire transactionnelle, ACM: D.: Software/D.3: PROGRAMMING LANGUAGES/D.3.3: Language Constructs and Features, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.4: Parallel Architectures, ACM: D.: Software/D.1: PROGRAMMING TECHNIQUES/D.1.3: Concurrent Programming, [INFO.INFO-DC]Computer Science [cs]/Distributed, Parallel, and Cluster Computing [cs.DC]

Relation: tel-01522826; https://hal.archives-ouvertes.fr/tel-01522826; https://hal.archives-ouvertes.fr/tel-01522826/document; https://hal.archives-ouvertes.fr/tel-01522826/file/hdr-v4.pdf; https://hal.archives-ouvertes.fr/tel-01522826/file/chronology%20%281%29.pdf; https://hal.archives-ouvertes.fr/tel-01522826/file/chronology.pdf; https://hal.archives-ouvertes.fr/tel-01522826/file/cmp.pdf; https://hal.archives-ouvertes.fr/tel-01522826/file/complexity%20%281%29.pdf; https://hal.archives-ouvertes.fr/tel-01522826/file/complexity.pdf; https://hal.archives-ouvertes.fr/tel-01522826/file/composition2%20%281%29.pdf; https://hal.archives-ouvertes.fr/tel-01522826/file/composition2.pdf; https://hal.archives-ouvertes.fr/tel-01522826/file/histories%20%281%29.pdf; https://hal.archives-ouvertes.fr/tel-01522826/file/histories.pdf; https://hal.archives-ouvertes.fr/tel-01522826/file/histories2%20%281%29.pdf; https://hal.archives-ouvertes.fr/tel-01522826/file/histories2.pdf; https://hal.archives-ouvertes.fr/tel-01522826/file/lf-vs-pstm-16384%20%281%29.pdf; https://hal.archives-ouvertes.fr/tel-01522826/file/lf-vs-pstm-16384.pdf; https://hal.archives-ouvertes.fr/tel-01522826/file/lf-vs-stm-16384%20%281%29.pdf; https://hal.archives-ouvertes.fr/tel-01522826/file/lf-vs-stm-16384.pdf; https://hal.archives-ouvertes.fr/tel-01522826/file/multiprocessor.pdf; https://hal.archives-ouvertes.fr/tel-01522826/file/skiplist_diagram%20%281%29.pdf; https://hal.archives-ouvertes.fr/tel-01522826/file/skiplist_diagram.pdf; https://hal.archives-ouvertes.fr/tel-01522826/file/tree1%20%281%29.pdf; https://hal.archives-ouvertes.fr/tel-01522826/file/tree1.pdf

Dostupnosť: https://hal.archives-ouvertes.fr/tel-01522826
https://hal.archives-ouvertes.fr/tel-01522826/document
https://hal.archives-ouvertes.fr/tel-01522826/file/hdr-v4.pdf
https://hal.archives-ouvertes.fr/tel-01522826/file/chronology%20%281%29.pdf
https://hal.archives-ouvertes.fr/tel-01522826/file/chronology.pdf
https://hal.archives-ouvertes.fr/tel-01522826/file/cmp.pdf
https://hal.archives-ouvertes.fr/tel-01522826/file/complexity%20%281%29.pdf
https://hal.archives-ouvertes.fr/tel-01522826/file/complexity.pdf
https://hal.archives-ouvertes.fr/tel-01522826/file/composition2%20%281%29.pdf
https://hal.archives-ouvertes.fr/tel-01522826/file/composition2.pdf

PRET-C: A new language for programming precision timed architectures

Autori: Andalam, Sidharta Roop, Partha Girault, Alain a ďalší

Prispievatelia: Andalam, Sidharta Roop, Partha Girault, Alain a ďalší

Zdroj: https://inria.hal.science/inria-00391621 ; [Research Report] RR-6922, INRIA. 2009, pp.38.

Predmety: Real-time systems, Precision Timed (PRET) Architectures, Synchronous Languages, ACM: B.: Hardware/B.1: CONTROL STRUCTURES AND MICROPROGRAMMING, ACM: C.: Computer Systems Organization/C.3: SPECIAL-PURPOSE AND APPLICATION-BASED SYSTEMS/C.3.2: Real-time and embedded systems, ACM: D.: Software/D.3: PROGRAMMING LANGUAGES/D.3.2: Language Classifications/D.3.2.1: Concurrent, distributed, and parallel languages, [INFO.INFO-ES]Computer Science [cs]/Embedded Systems

Dostupnosť: https://inria.hal.science/inria-00391621
https://inria.hal.science/inria-00391621v1/document
https://inria.hal.science/inria-00391621v1/file/rr.pdf

HARS: A Hardware-Assisted Runtime Software for embedded many-core architectures

Autori: Lhuillier, Y. Ojail, M. Guerre, A. a ďalší

Prispievatelia: Lhuillier, Y. Ojail, M. Guerre, A. a ďalší

Zdroj: ISSN: 1539-9087.

Predmety: B.5.0 [Register-Transfer-Level Implementation]: General, ACM: D.: Software/D.4: OPERATING SYSTEMS/D.4.7: Organization and Design/D.4.7.4: Real-time systems and embedded systems, ACM: D.: Software/D.4: OPERATING SYSTEMS/D.4.1: Process Management, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.4: Parallel Architectures, ACM: B.: Hardware/B.5: REGISTER-TRANSFER-LEVEL IMPLEMENTATION, [INFO]Computer Science [cs]

Dostupnosť: https://cea.hal.science/cea-01818892
https://doi.org/10.1145/2517311

EEA-Aware For Large-Scale Scientific Applications On Heterogeneous Architectures

Autori: Garcia Henao, John Anderson, John Anderson Garcia Henao Hernandez, Esteban Navaux, Philippe, O.A. a ďalší

Prispievatelia: Garcia Henao, John Anderson, John Anderson Garcia Henao Hernandez, Esteban Navaux, Philippe, O.A. a ďalší

Zdroj: ACM Student Research Competition at Supercomputing. The International Conference for High Performance Computing, Networking, Storage and Analysis ; https://hal.science/hal-01739585 ; ACM Student Research Competition at Supercomputing. The International Conference for High Performance Computing, Networking, Storage and Analysis, Nov 2016, Salt Lake City, Utah, United States

Predmety: Exascale Computing, Energy Aware, Power Capping, Energy Efficiency, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.4: Parallel Architectures, ACM: D.: Software/D.4: OPERATING SYSTEMS/D.4.8: Performance/D.4.8.2: Monitors, ACM: D.: Software/D.4: OPERATING SYSTEMS/D.4.8: Performance/D.4.8.1: Modeling and prediction, [INFO.INFO-DC]Computer Science [cs]/Distributed, Parallel, and Cluster Computing [cs.DC]

Geografické téma: Salt Lake City, Utah, United States

Dostupnosť: https://hal.science/hal-01739585
https://hal.science/hal-01739585v1/document
https://hal.science/hal-01739585v1/file/01_EEAaware-SC16-JAGH-poster.pdf

Predictive Runtime Code Scheduling for Heterogeneous Architectures

Autori: Jiménez, Victor J. Vilanova, Llu'Is Gelado, Isaac a ďalší

Prispievatelia: Jiménez, Victor J. Vilanova, Llu'Is Gelado, Isaac a ďalší

Zdroj: HiPEAC 2009 - High Performance and Embedded Architectures and Compilers ; https://inria.hal.science/inria-00445304 ; HiPEAC 2009 - High Performance and Embedded Architectures and Compilers, Jan 2009, Paphos, Cyprus. ⟨10.1007/978-3-540-92990-1_4⟩

Predmety: ACM: B.: Hardware/B.2: ARITHMETIC AND LOGIC STRUCTURES, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES, ACM: D.: Software/D.3: PROGRAMMING LANGUAGES/D.3.4: Processors, [INFO.INFO-OH]Computer Science [cs]/Other [cs.OH], [INFO.INFO-ES]Computer Science [cs]/Embedded Systems

Geografické téma: Paphos, Cyprus

Dostupnosť: https://inria.hal.science/inria-00445304
https://doi.org/10.1007/978-3-540-92990-1_4

ACM: An Efficient Approach for Managing Shared Caches in Chip Multiprocessors

Autori: Hammoud, Mohammad Cho, Sangyeun Melhem, Rami a ďalší

Prispievatelia: Hammoud, Mohammad Cho, Sangyeun Melhem, Rami a ďalší

Zdroj: HiPEAC 2009 - High Performance and Embedded Architectures and Compilers ; https://hal.inria.fr/inria-00446343 ; HiPEAC 2009 - High Performance and Embedded Architectures and Compilers, Jan 2009, Paphos, Cyprus. ⟨10.1007/978-3-540-92990-1_26⟩

Predmety: ACM: B.: Hardware/B.2: ARITHMETIC AND LOGIC STRUCTURES, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES, ACM: D.: Software/D.3: PROGRAMMING LANGUAGES/D.3.4: Processors, [INFO.INFO-OH]Computer Science [cs]/Other [cs.OH], [INFO.INFO-ES]Computer Science [cs]/Embedded Systems, manag, lang

Geografické téma: Paphos, Cyprus

Relation: https://hal.inria.fr/inria-00446343

Dostupnosť: https://hal.inria.fr/inria-00446343

Integrated Modulo Scheduling for Clustered VLIW Architectures

Autori: Eriksson, Mattias V. Kessler, Christoph W. Department of Computer and Information Science - Linköping University a ďalší

Prispievatelia: Eriksson, Mattias V. Kessler, Christoph W. Department of Computer and Information Science - Linköping University a ďalší

Zdroj: HiPEAC 2009 - High Performance and Embedded Architectures and Compilers ; https://hal.inria.fr/inria-00445475 ; HiPEAC 2009 - High Performance and Embedded Architectures and Compilers, Jan 2009, Paphos, Cyprus. ⟨10.1007/978-3-540-92990-1_7⟩

Predmety: ACM: B.: Hardware/B.2: ARITHMETIC AND LOGIC STRUCTURES, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES, ACM: D.: Software/D.3: PROGRAMMING LANGUAGES/D.3.4: Processors, [INFO.INFO-OH]Computer Science [cs]/Other [cs.OH], [INFO.INFO-ES]Computer Science [cs]/Embedded Systems

Geografické téma: Paphos, Cyprus

Relation: inria-00445475; https://hal.inria.fr/inria-00445475

Dostupnosť: https://hal.inria.fr/inria-00445475
https://doi.org/10.1007/978-3-540-92990-1_7

Survey of Models and Architectures to Ensure Linked Data Access

Autori: Toure, Mahamadou Gandon, Fabien Guidedi, Kaladzavi a ďalší

Prispievatelia: Toure, Mahamadou Gandon, Fabien Guidedi, Kaladzavi a ďalší

Zdroj: https://inria.hal.science/hal-03956456 ; Inria & Université Côte d'Azur, CNRS, I3S. 2023, pp.23.

Predmety: Web of Data, Gossip protocol, graph replication, limited connectivity, semantic overlay, mobile contributor, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.4: Parallel Architectures/C.1.4.0: Distributed architectures, ACM: I.: Computing Methodologies/I.2: ARTIFICIAL INTELLIGENCE/I.2.4: Knowledge Representation Formalisms and Methods, [INFO.INFO-DS]Computer Science [cs]/Data Structures and Algorithms [cs.DS]

Dostupnosť: https://inria.hal.science/hal-03956456
https://inria.hal.science/hal-03956456v1/document
https://inria.hal.science/hal-03956456v1/file/MahamadouToureSurvey.pdf

TBES: Template-Based Exploration and Synthesis of Heterogeneous Multiprocessor Architectures on FPGA

Autori: Corre, Youenn Diguet, Jean-Philippe Heller, Dominique a ďalší

Prispievatelia: Corre, Youenn Diguet, Jean-Philippe Heller, Dominique a ďalší

Zdroj: ACM Transactions on Embedded Computing Systems. 15:1-27

Predmety: [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES, 13. Climate action, Electronic System Level, 0202 electrical engineering, electronic engineering, information engineering, ACM: B.: Hardware/B.5: REGISTER-TRANSFER-LEVEL IMPLEMENTATION, Multiprocessor, 02 engineering and technology, High-Level Synthesis, ACM: D.: Software/D.2: SOFTWARE ENGINEERING/D.2.2: Design Tools and Techniques, System-on-Chip

Prístupová URL adresa: https://hal.archives-ouvertes.fr/hal-01172103/document
https://dblp.uni-trier.de/db/journals/tecs/tecs15.html#CorreDHBL16
https://hal.archives-ouvertes.fr/hal-01172103
https://dl.acm.org/doi/10.1145/2816817
https://doi.org/10.1145/2816817

Introduction au parallélisme et aux architectures parallèles

Autori: Etiemble, Daniel Cappello, Franck Laboratoire de Recherche en Informatique (LRI) a ďalší

Prispievatelia: Etiemble, Daniel Cappello, Franck Laboratoire de Recherche en Informatique (LRI) a ďalší

Zdroj: ISSN: 1776-0860 ; Techniques de l'Ingénieur ; https://hal.science/hal-01793592 ; 2017.

Predmety: pThreads, loi d'Amdhal, modèle Roofline, mémoires partagées et distribuées, parallélisme de données et de contrôle, modèles d'exécution, classification de Flynn, extensions SIMD, OpenMP, modèles de programmation, MPI, ACM: C.: Computer Systems Organization, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES, [INFO]Computer Science [cs], [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

Dostupnosť: https://hal.science/hal-01793592

El proceso de creaión de una base de datos web. (Spanish)

Alternate Title: The development process for databases on the Web. (English)

Autori: Marcos, Esperanza Vela, Belen

Zdroj: El Profesional de la Información; jul/ago2002, Vol. 11 Issue 4, p248, 8p

Predmety: WEBSITES, DATABASES, WORLD Wide Web, INFORMATION storage & retrieval systems, INTERNET

Embedded Runtime for Reconfigurable Dataflow Graphs on Manycore Architectures

Autori: Miomandre, Hugo Hascoët, Julien Desnos, Karol a ďalší

Prispievatelia: Miomandre, Hugo Hascoët, Julien Desnos, Karol a ďalší

Zdroj: PARMA-DITAM ; https://hal.science/hal-01704702 ; PARMA-DITAM, Jan 2018, Manchester, United Kingdom. ⟨10.1145/3183767.3183780⟩

Predmety: ACM: C.: Computer Systems Organization, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.4: Parallel Architectures, [INFO.INFO-ES]Computer Science [cs]/Embedded Systems

Geografické téma: Manchester, United Kingdom

Dostupnosť: https://hal.science/hal-01704702
https://hal.science/hal-01704702v1/document
https://hal.science/hal-01704702v1/file/parma-ditam18.pdf
https://doi.org/10.1145/3183767.3183780

Architectures and Mechanisms to Maintain efficiently Consistency in Collaborative Virtual Environments

Autori: Fleury, Cédric Duval, Thierry Gouranton, Valérie a ďalší

Prispievatelia: Fleury, Cédric Duval, Thierry Gouranton, Valérie a ďalší

Zdroj: SEARIS 2010 (IEEE VR 2010 Workshop on Software Engineering and Architectures for Realtime Interactive Systems) ; https://inria.hal.science/inria-00534082 ; SEARIS 2010 (IEEE VR 2010 Workshop on Software Engineering and Architectures for Realtime Interactive Systems), Mar 2010, Waltham, United States

Predmety: ACM: H.: Information Systems/H.5: INFORMATION INTERFACES AND PRESENTATION (e.g., HCI)/H.5.3: Group and Organization Interfaces/H.5.3.2: Computer-supported cooperative work, ACM: C.: Computer Systems Organization/C.2: COMPUTER-COMMUNICATION NETWORKS/C.2.4: Distributed Systems/C.2.4.1: Distributed applications, ACM: I.: Computing Methodologies/I.3: COMPUTER GRAPHICS/I.3.7: Three-Dimensional Graphics and Realism/I.3.7.6: Virtual reality, [INFO.INFO-GR]Computer Science [cs]/Graphics [cs.GR]

Geografické téma: Waltham, United States

Dostupnosť: https://inria.hal.science/inria-00534082
https://inria.hal.science/inria-00534082/document
https://inria.hal.science/inria-00534082/file/searis2010.pdf

Proceso de Lope de Vega por libelos contra unos cómicos / anotado por D. A. Tomillo y D. C. Pérez Pastor.., 1901

Autori: Pérez Pastor, Cristóbal, Auteur du texte Tomillo, Atanasio. Auteur du texte

Zdroj: Bibliothèque nationale de France, département Philosophie, histoire, sciences de l'homme, 8-OO-1246, 1901.

Relation: Notice du catalogue : http://catalogue.bnf.fr/ark:/12148/cb31479008k

Prístupová URL adresa: http://gallica.bnf.fr/ark:/12148/bpt6k1484166

Software Abstractions for Parallel Architectures ; Abstractions Logicielles pour Architectures Parallèles

Autori: Falcou, Joel Systèmes parallèles (LRI) (ParSys - LRI) Laboratoire de Recherche en Informatique (LRI) a ďalší

Prispievatelia: Falcou, Joel Systèmes parallèles (LRI) (ParSys - LRI) Laboratoire de Recherche en Informatique (LRI) a ďalší

Zdroj: https://inria.hal.science/tel-01111708 ; Distributed, Parallel, and Cluster Computing [cs.DC]. Universite de Paris 11, 2014.

Predmety: parallel programming, generic programming, generative programming, meta-programming, parallel skeletons, programmation parallèle, méta-programmation, programmation générative, programmation générique, squelettes parallèles, ACM: D.: Software/D.2: SOFTWARE ENGINEERING, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.4: Parallel Architectures, [INFO.INFO-DC]Computer Science [cs]/Distributed, Parallel, and Cluster Computing [cs.DC]

Dostupnosť: https://inria.hal.science/tel-01111708
https://inria.hal.science/tel-01111708v1/document
https://inria.hal.science/tel-01111708v1/file/Thesis.pdf

From Scilab to Multicore Embedded Systems: Algorithms and Methodologies

Autori: Goulas, George Alefragis, Panayiotis Voros, Nikolaos S. a ďalší

Prispievatelia: Goulas, George Alefragis, Panayiotis Voros, Nikolaos S. a ďalší

Zdroj: Proceedings of the IEEE International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (IC-SAMOS 2012 ; https://inria.hal.science/hal-00752615 ; Proceedings of the IEEE International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (IC-SAMOS 2012, Jul 2012, Samos, Greece

Predmety: ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.4: Parallel Architectures, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

Geografické téma: Samos, Greece

Dostupnosť: https://inria.hal.science/hal-00752615

Demo: OneLab: Major Computer Networking Testbeds for IoT and Wireless Experimentation

Autori: Baron, Loïc Boubekeur, Fadwa Klacza, Radomir a ďalší

Prispievatelia: Baron, Loïc Boubekeur, Fadwa Klacza, Radomir a ďalší

Zdroj: MobiCom '15: Proceedings of the 21st Annual International Conference on Mobile Computing and Networking ; MobiCom 2015 ; https://hal.science/hal-01305359 ; MobiCom 2015, ACM, Sep 2015, Paris, France. ⟨10.1145/2789168.2789180⟩ ; http://www.sigmobile.org/mobicom/2015/

Predmety: testbeds, distributed systems, routing protocols, Internet of Things, ACM: C.: Computer Systems Organization/C.2: COMPUTER-COMMUNICATION NETWORKS, ACM: C.: Computer Systems Organization/C.2: COMPUTER-COMMUNICATION NETWORKS/C.2.2: Network Protocols, ACM: C.: Computer Systems Organization/C.2: COMPUTER-COMMUNICATION NETWORKS/C.2.4: Distributed Systems, ACM: C.: Computer Systems Organization/C.2: COMPUTER-COMMUNICATION NETWORKS/C.2.1: Network Architecture and Design, ACM: D.: Software/D.2: SOFTWARE ENGINEERING, ACM: D.: Software/D.2: SOFTWARE ENGINEERING/D.2.11: Software Architectures, ACM: D.: Software/D.2: SOFTWARE ENGINEERING/D.2.12: Interoperability, [INFO.INFO-WB]Computer Science [cs]/Web, [INFO.INFO-NI]Computer Science [cs]/Networking and Internet Architecture [cs.NI], [INFO.INFO-ES]Computer Science [cs]/Embedded Systems, [INFO.INFO-MC]Computer Science [cs]/Mobile Computing, [INFO.INFO-ET]Computer Science [cs]/Emerging Technologies [cs.ET]

Geografické téma: Paris, France

Relation: info:eu-repo/grantAgreement//287581/EU/OpenLab: extending FIRE testbeds and tools/OpenLab

Dostupnosť: https://hal.science/hal-01305359
https://hal.science/hal-01305359v1/document
https://hal.science/hal-01305359v1/file/p199-baron.pdf
https://doi.org/10.1145/2789168.2789180

Self-organisation for survival in complex computer architectures

Autori: Fiona A. C. Polack The Pennsylvania State University CiteSeerX Archives

Prispievatelia: Fiona A. C. Polack The Pennsylvania State University CiteSeerX Archives

Zdroj: http://www-users.cs.york.ac.uk/~fiona/PUBS/SOAR2010chapter.pdf.

Popis súboru: application/pdf

Relation: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.421.2939

Dostupnosť: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.421.2939
http://www-users.cs.york.ac.uk/~fiona/PUBS/SOAR2010chapter.pdf

Loosely Time-Triggered Architectures based on Communication-by-Sampling

Autori: Benveniste, Albert Caspi, Paul Di Natale, Marco a ďalší

Prispievatelia: Benveniste, Albert Caspi, Paul Di Natale, Marco a ďalší

Zdroj: https://inria.hal.science/inria-00156468 ; [Research Report] PI 1854, 2007, pp.41.

Predmety: Real-time systems, distributed control, time-triggered, loosely time-triggered, MoCC, ACM: D.: Software/D.4: OPERATING SYSTEMS, ACM: C.: Computer Systems Organization/C.3: SPECIAL-PURPOSE AND APPLICATION-BASED SYSTEMS, [INFO.INFO-OH]Computer Science [cs]/Other [cs.OH]

Relation: Report N°: PI 1854

Dostupnosť: https://inria.hal.science/inria-00156468
https://inria.hal.science/inria-00156468v1/document
https://inria.hal.science/inria-00156468v1/file/PI-1854.pdf

A Unifying View of Loosely Time-Triggered Architectures

Autori: Baudart, Guillaume Benveniste, Albert Bouillard, Anne a ďalší

Prispievatelia: Baudart, Guillaume Benveniste, Albert Bouillard, Anne a ďalší

Zdroj: https://inria.hal.science/hal-00955496 ; [Research Report] RR-8494, INRIA. 2014, pp.14.

Predmety: Time-Triggered Architecture, Elastic Circuits, Loosely Time-Triggered Architecture, ACM: C.: Computer Systems Organization/C.0: GENERAL, [INFO.INFO-ES]Computer Science [cs]/Embedded Systems

Dostupnosť: https://inria.hal.science/hal-00955496
https://inria.hal.science/hal-00955496v1/document
https://inria.hal.science/hal-00955496v1/file/RR-8494.pdf