Search Results - acm: c.: computer system organization/c.1: processor architectures~

Synchronous byzantine agreement with nearly a cubic number of communication bits

Authors: Kowalski, Dariusz R. Mostefaoui, Achour Department of Computer Science Liverpool et al.

Contributors: Kowalski, Dariusz R. Mostefaoui, Achour Department of Computer Science Liverpool et al.

Source: ACM symposium on Principles of distributed computing (PODC'13) ; https://hal.science/hal-01151136 ; ACM symposium on Principles of distributed computing (PODC'13), Jul 2013, New-York, United States. pp.84-91, ⟨10.1145/2484239.2484271⟩

Subject Terms: Agreement problem, Synchronous distributed system, Byzantine process, Message-passing model, Round-based protocol, EIG, Consensus, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.4: Parallel Architectures/C.1.4.0: Distributed architectures, ACM: C.: Computer Systems Organization/C.2: COMPUTER-COMMUNICATION NETWORKS/C.2.4: Distributed Systems, ACM: D.: Software/D.4: OPERATING SYSTEMS/D.4.7: Organization and Design/D.4.7.1: Distributed systems, ACM: D.: Software/D.4: OPERATING SYSTEMS/D.4.5: Reliability/D.4.5.2: Fault-tolerance, ACM: D.: Software/D.4: OPERATING SYSTEMS/D.4.1: Process Management/D.4.1.0: Concurrency, ACM: D.: Software/D.4: OPERATING SYSTEMS/D.4.1: Process Management/D.4.1.5: Synchronization, [INFO]Computer Science [cs], [INFO.INFO-DC]Computer Science [cs]/Distributed, Parallel, and Cluster Computing [cs.DC], [INFO.INFO-DS]Computer Science [cs]/Data Structures and Algorithms [cs.DS]

Subject Geographic: New-York, United States

Availability: https://hal.science/hal-01151136
https://hal.science/hal-01151136v1/document
https://hal.science/hal-01151136v1/file/podc%20final.pdf
https://doi.org/10.1145/2484239.2484271

HARS: A Hardware-Assisted Runtime Software for embedded many-core architectures

Authors: Lhuillier, Y. Ojail, M. Guerre, A. et al.

Contributors: Lhuillier, Y. Ojail, M. Guerre, A. et al.

Source: ISSN: 1539-9087.

Subject Terms: B.5.0 [Register-Transfer-Level Implementation]: General, ACM: D.: Software/D.4: OPERATING SYSTEMS/D.4.7: Organization and Design/D.4.7.4: Real-time systems and embedded systems, ACM: D.: Software/D.4: OPERATING SYSTEMS/D.4.1: Process Management, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.4: Parallel Architectures, ACM: B.: Hardware/B.5: REGISTER-TRANSFER-LEVEL IMPLEMENTATION, [INFO]Computer Science [cs]

Availability: https://cea.hal.science/cea-01818892
https://doi.org/10.1145/2517311

Embedded Runtime for Reconfigurable Dataflow Graphs on Manycore Architectures

Authors: Miomandre, Hugo Hascoët, Julien Desnos, Karol et al.

Contributors: Miomandre, Hugo Hascoët, Julien Desnos, Karol et al.

Source: PARMA-DITAM ; https://hal.science/hal-01704702 ; PARMA-DITAM, Jan 2018, Manchester, United Kingdom. ⟨10.1145/3183767.3183780⟩

Subject Terms: ACM: C.: Computer Systems Organization, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.4: Parallel Architectures, [INFO.INFO-ES]Computer Science [cs]/Embedded Systems

Subject Geographic: Manchester, United Kingdom

Availability: https://hal.science/hal-01704702
https://hal.science/hal-01704702v1/document
https://hal.science/hal-01704702v1/file/parma-ditam18.pdf
https://doi.org/10.1145/3183767.3183780

Introduction au parallélisme et aux architectures parallèles

Authors: Etiemble, Daniel Cappello, Franck Laboratoire de Recherche en Informatique (LRI) et al.

Contributors: Etiemble, Daniel Cappello, Franck Laboratoire de Recherche en Informatique (LRI) et al.

Source: ISSN: 1776-0860 ; Techniques de l'Ingénieur ; https://hal.science/hal-01793592 ; 2017.

Subject Terms: pThreads, loi d'Amdhal, modèle Roofline, mémoires partagées et distribuées, parallélisme de données et de contrôle, modèles d'exécution, classification de Flynn, extensions SIMD, OpenMP, modèles de programmation, MPI, ACM: C.: Computer Systems Organization, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES, [INFO]Computer Science [cs], [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

Availability: https://hal.science/hal-01793592

An Experience Report on Using Gamification in Technical Higher Education, ACM Technical Symposium on Computer Science Education SIGCSE 2014, March 5.8, 2014

Authors: Alexandru Iosup Dick Epema The Pennsylvania State University CiteSeerX Archives

Contributors: Alexandru Iosup Dick Epema The Pennsylvania State University CiteSeerX Archives

Source: http://www.pds.ewi.tudelft.nl/~iosup/gamification-higher-education14sigcse_sub.pdf.

Subject Terms: ganization, General—System architectures, C.1.0 [Computer Systems Organization, Processor Architectures—Gen- eral, H.3.4 [Information Systems, Systems and Soft- ware—Distributed systems Keywords CS Ed research, gamification, experience report

File Description: application/pdf

Relation: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.637.388

Availability: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.637.388
http://www.pds.ewi.tudelft.nl/~iosup/gamification-higher-education14sigcse_sub.pdf

Probabilistic System-on-a-Chip Architectures

Authors: Lakshmi N. Chakrapani Pinar Korkmaz Bilge E. S. Akgul et al.

Contributors: Lakshmi N. Chakrapani Pinar Korkmaz Bilge E. S. Akgul et al.

Source: http://www.crest.gatech.edu/palempbitscurrent/a29-chakrapani.pdf.

Subject Terms: Categories and Subject Descriptors, C.3 [Computer Systems Organization, Special-Purpose and Application-Based Systems, C.1.3 [Processor Architectures, Other Architecture Styles General Terms, Performance, Design, Reliability Additional Key Words and Phrases, Embedded systems, probabilistic computing ACM Reference Format

File Description: application/pdf

Relation: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.91.430

Availability: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.91.430
http://www.crest.gatech.edu/palempbitscurrent/a29-chakrapani.pdf

A Framework for Task Scheduling and Memory Partitioning for Multi-Processor System-on-Chip

Authors: Salamy, Hassan Ramanujam, J. Department of Electrical and Computer Engineering - Louisiana State University (ECE) et al.

Contributors: Salamy, Hassan Ramanujam, J. Department of Electrical and Computer Engineering - Louisiana State University (ECE) et al.

Source: HiPEAC 2009 - High Performance and Embedded Architectures and Compilers ; https://hal.inria.fr/inria-00446288 ; HiPEAC 2009 - High Performance and Embedded Architectures and Compilers, Jan 2009, Paphos, Cyprus. ⟨10.1007/978-3-540-92990-1_20⟩

Subject Terms: ACM: B.: Hardware/B.2: ARITHMETIC AND LOGIC STRUCTURES, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES, ACM: D.: Software/D.3: PROGRAMMING LANGUAGES/D.3.4: Processors, [INFO.INFO-OH]Computer Science [cs]/Other [cs.OH], [INFO.INFO-ES]Computer Science [cs]/Embedded Systems

Subject Geographic: Paphos, Cyprus

Relation: inria-00446288; https://hal.inria.fr/inria-00446288

Availability: https://hal.inria.fr/inria-00446288
https://doi.org/10.1007/978-3-540-92990-1_20

ACM Transactions on Embedded Computing Systems Special Issue on Application Specific Processors

Authors: Spiridon F. Beldianu Sotirios G. Ziavras The Pennsylvania State University CiteSeerX Archives

Contributors: Spiridon F. Beldianu Sotirios G. Ziavras The Pennsylvania State University CiteSeerX Archives

Source: http://web.njit.edu/~ziavras/ACM-TECS-2013.pdf.

Subject Terms: Categories and Subject Descriptors, C.1.2 [Computer Systems Organization, Processor Architectures – Multipl

File Description: application/pdf

Relation: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.459.7648

Availability: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.459.7648
http://web.njit.edu/~ziavras/ACM-TECS-2013.pdf

TBES: Template-Based Exploration and Synthesis of Heterogeneous Multiprocessor Architectures on FPGA

Authors: Corre, Youenn Diguet, Jean-Philippe Heller, Dominique et al.

Contributors: Corre, Youenn Diguet, Jean-Philippe Heller, Dominique et al.

Source: ACM Transactions on Embedded Computing Systems. 15:1-27

Subject Terms: [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES, 13. Climate action, Electronic System Level, 0202 electrical engineering, electronic engineering, information engineering, ACM: B.: Hardware/B.5: REGISTER-TRANSFER-LEVEL IMPLEMENTATION, Multiprocessor, 02 engineering and technology, High-Level Synthesis, ACM: D.: Software/D.2: SOFTWARE ENGINEERING/D.2.2: Design Tools and Techniques, System-on-Chip

Access URL: https://hal.archives-ouvertes.fr/hal-01172103/document
https://dblp.uni-trier.de/db/journals/tecs/tecs15.html#CorreDHBL16
https://hal.archives-ouvertes.fr/hal-01172103
https://dl.acm.org/doi/10.1145/2816817
https://doi.org/10.1145/2816817

Skewed Compressed Cache

Authors: Sardashti, Somayeh Seznec, André Wood, David A. et al.

Contributors: Sardashti, Somayeh Seznec, André Wood, David A. et al.

Source: Proceeding of the 47th Annual IEEE/ACM International Symposium on Microarchitecture ; MICRO - 47th Annual IEEE/ACM International Symposium on Microarchitecture ; https://inria.hal.science/hal-01088050 ; MICRO - 47th Annual IEEE/ACM International Symposium on Microarchitecture, Dec 2014, Cambridge, United Kingdom

Subject Terms: component, cache design, compression, performance, energy, ACM: C.: Computer Systems Organization, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

Subject Geographic: Cambridge, United Kingdom

Relation: info:eu-repo/grantAgreement//267175/EU/Defying Amdahl\'s Law/DAL

Availability: https://inria.hal.science/hal-01088050
https://inria.hal.science/hal-01088050/document
https://inria.hal.science/hal-01088050/file/scc%20october%202%20%281%29.pdf

Exploring branch predictability limits with the MTAGE+SC predictor *

Authors: Seznec, André Pushing Architecture and Compilation for Application Performance (PACAP) Inria Rennes – Bretagne Atlantique et al.

Contributors: Seznec, André Pushing Architecture and Compilation for Application Performance (PACAP) Inria Rennes – Bretagne Atlantique et al.

Source: 5th JILP Workshop on Computer Architecture Competitions (JWAC-5): Championship Branch Prediction (CBP-5)
https://inria.hal.science/hal-01354251
5th JILP Workshop on Computer Architecture Competitions (JWAC-5): Championship Branch Prediction (CBP-5), Jun 2016, Seoul, South Korea. pp.4
http://www.jilp.org/cbp2016/

Subject Terms: ACM: C.: Computer Systems Organization, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.1: Single Data Stream Architectures/C.1.1.1: Pipeline processors, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

Subject Geographic: Seoul, South Korea

Availability: https://inria.hal.science/hal-01354251
https://inria.hal.science/hal-01354251v1/document
https://inria.hal.science/hal-01354251v1/file/MutiTage-SC.pdf

Yet Another Compressed Cache: a Low Cost Yet Effective Compressed Cache

Authors: Sardashti, Somayeh Seznec, André Wood, David A. et al.

Contributors: Sardashti, Somayeh Seznec, André Wood, David A. et al.

Source: ISSN: 1544-3566.

Subject Terms: ACM: C.: Computer Systems Organization, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.2: Multiple Data Stream Architectures (Multiprocessors), [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

Relation: info:eu-repo/grantAgreement//267175/EU/Defying Amdahl\'s Law/DAL

Availability: https://inria.hal.science/hal-01354248
https://inria.hal.science/hal-01354248v1/document
https://inria.hal.science/hal-01354248v1/file/yacc-taco-july%2022-final.pdf
https://doi.org/10.1145/2976740

Evolution de l'architecture des ordinateurs

Authors: Etiemble, Daniel Laboratoire de Recherche en Informatique (LRI) Université Paris-Sud - Paris 11 (UP11)-CentraleSupélec-Centre National de la Recherche Scientifique (CNRS)

Contributors: Etiemble, Daniel Laboratoire de Recherche en Informatique (LRI) Université Paris-Sud - Paris 11 (UP11)-CentraleSupélec-Centre National de la Recherche Scientifique (CNRS)

Source: ISSN: 1776-0860 ; Techniques de l'Ingénieur ; https://hal.science/hal-01793615 ; 2016.

Subject Terms: mur de la chaleur, mur mémoire, technologie CMOS, GPU, multi-cœur, CPU, ACM: C.: Computer Systems Organization, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES, [INFO]Computer Science [cs], [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

Availability: https://hal.science/hal-01793615

Hiérarchie mémoire : les caches

Authors: Etiemble, Daniel Anceau, François Laboratoire de Recherche en Informatique (LRI) et al.

Contributors: Etiemble, Daniel Anceau, François Laboratoire de Recherche en Informatique (LRI) et al.

Source: ISSN: 1776-0860 ; Techniques de l'Ingénieur ; https://hal.science/hal-01794025 ; 2012.

Subject Terms: fonctionnement des caches, cohérence des caches, caches multiprocesseurs et multicoeurs, optimisations logicielles, ACM: C.: Computer Systems Organization, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES, [INFO]Computer Science [cs], [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

Availability: https://hal.science/hal-01794025

Extensions SIMD des jeux d'instructions

Authors: Etiemble, Daniel Lacassagne, Lionel Laboratoire de Recherche en Informatique (LRI) et al.

Contributors: Etiemble, Daniel Lacassagne, Lionel Laboratoire de Recherche en Informatique (LRI) et al.

Source: ISSN: 1776-0860 ; Techniques de l'Ingénieur ; https://hal.science/hal-01793974 ; Techniques de l'Ingénieur, 2015.

Subject Terms: Instructions SIMD, SSE, intrinsèque, vectorisation, Altivec, Neon, AVX, ACM: C.: Computer Systems Organization, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES, [INFO]Computer Science [cs], [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

Availability: https://hal.science/hal-01793974

TAGE-SC-L Branch Predictors

Authors: Seznec, André Amdahl's Law is Forever (ALF) Inria Rennes – Bretagne Atlantique et al.

Contributors: Seznec, André Amdahl's Law is Forever (ALF) Inria Rennes – Bretagne Atlantique et al.

Source: Proceedings of the 4th Championship Branch Prediction ; JILP - Championship Branch Prediction ; https://inria.hal.science/hal-01086920 ; JILP - Championship Branch Prediction, Jun 2014, Minneapolis, United States ; http://www.jilp.org/cbp2014/

Subject Terms: ACM: C.: Computer Systems Organization, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

Subject Geographic: Minneapolis, United States

Relation: info:eu-repo/grantAgreement//267175/EU/Defying Amdahl\'s Law/DAL

Availability: https://inria.hal.science/hal-01086920
https://inria.hal.science/hal-01086920/document
https://inria.hal.science/hal-01086920/file/CBP4-TAGE-SC-L.pdf

Jeux d'instructions des processeurs

Authors: Etiemble, Daniel Laboratoire de Recherche en Informatique (LRI) Université Paris-Sud - Paris 11 (UP11)-CentraleSupélec-Centre National de la Recherche Scientifique (CNRS)

Contributors: Etiemble, Daniel Laboratoire de Recherche en Informatique (LRI) Université Paris-Sud - Paris 11 (UP11)-CentraleSupélec-Centre National de la Recherche Scientifique (CNRS)

Source: https://hal.science/hal-01794009 ; 2016.

Subject Terms: CISC, format d'instructions, type d'instructions, RISC, interface matériel-logiciel, jeu d'instructions, ACM: C.: Computer Systems Organization, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES, [INFO]Computer Science [cs], [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

Availability: https://hal.science/hal-01794009

Processeurs superscalaires 'flots de données'

Authors: Anceau, François Etiemble, Daniel Circuits Intégrés Numériques et Analogiques (CIAN) et al.

Contributors: Anceau, François Etiemble, Daniel Circuits Intégrés Numériques et Analogiques (CIAN) et al.

Source: https://hal.science/hal-01793606 ; 2018.

Subject Terms: superscalaire, parpallélisme d’instruction, flot de données, renommage de registres, stations de réservation, tampon de réordonnancement, ACM: C.: Computer Systems Organization, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES, [INFO]Computer Science [cs], [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

Availability: https://hal.science/hal-01793606

Processeurs superscalaires multi-pipelines

Authors: Etiemble, Daniel Anceau, François Laboratoire de Recherche en Informatique (LRI) et al.

Contributors: Etiemble, Daniel Anceau, François Laboratoire de Recherche en Informatique (LRI) et al.

Source: ISSN: 1776-0860 ; Techniques de l'Ingénieur ; https://hal.science/hal-01793667 ; 2015.

Subject Terms: superscalaire, multi-pipeline, lancement des instructions, parallélisme d'instructions, ACM: C.: Computer Systems Organization, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES, [INFO]Computer Science [cs], [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

Availability: https://hal.science/hal-01793667

Introduction aux systèmes embarqués, enfouis et mobiles

Authors: Etiemble, Daniel Laboratoire de Recherche en Informatique (LRI) Université Paris-Sud - Paris 11 (UP11)-CentraleSupélec-Centre National de la Recherche Scientifique (CNRS)

Contributors: Etiemble, Daniel Laboratoire de Recherche en Informatique (LRI) Université Paris-Sud - Paris 11 (UP11)-CentraleSupélec-Centre National de la Recherche Scientifique (CNRS)

Source: ISSN: 1776-0860 ; Techniques de l'Ingénieur ; https://hal.science/hal-01793572 ; 2016.

Subject Terms: temps réel, énergie, taille, coût, systèmes de communication, systèmes de contrôle, ACM: C.: Computer Systems Organization, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES, [INFO]Computer Science [cs]

Availability: https://hal.science/hal-01793572