Search Results - acm: c.: computer system organization/c.1: processor architectures/c.1.4: parallel architecture*

Towards a New Processor Architecture. ; Vers une nouvelle Architecture de Processeurs

Authors: Vincent, Pierre Landru, Jacques Ecole nationale supérieure Mines-Télécom Lille Douai (IMT Nord Europe) et al.

Contributors: Vincent, Pierre Landru, Jacques Ecole nationale supérieure Mines-Télécom Lille Douai (IMT Nord Europe) et al.

Source: https://hal.science/hal-05117313 ; 2025.

Subject Terms: silicon, parallel, serial, RISC, photonics, computer, optronics, optics, processor, fiber, laser, digital, silicium, parallèle, série, processeur, photonique, ordinateur, optronique, optique, numérique, fibre, ACM: B.: Hardware, ACM: C.: Computer Systems Organization, [INFO]Computer Science [cs], [PHYS]Physics [physics]

Availability: https://hal.science/hal-05117313
https://hal.science/hal-05117313v2/document
https://hal.science/hal-05117313v2/file/frParalSerieRiscV1.pdf

HARS: A Hardware-Assisted Runtime Software for embedded many-core architectures

Authors: Lhuillier, Y. Ojail, M. Guerre, A. et al.

Contributors: Lhuillier, Y. Ojail, M. Guerre, A. et al.

Source: ISSN: 1539-9087.

Subject Terms: B.5.0 [Register-Transfer-Level Implementation]: General, ACM: D.: Software/D.4: OPERATING SYSTEMS/D.4.7: Organization and Design/D.4.7.4: Real-time systems and embedded systems, ACM: D.: Software/D.4: OPERATING SYSTEMS/D.4.1: Process Management, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.4: Parallel Architectures, ACM: B.: Hardware/B.5: REGISTER-TRANSFER-LEVEL IMPLEMENTATION, [INFO]Computer Science [cs]

Availability: https://cea.hal.science/cea-01818892
https://doi.org/10.1145/2517311

Embedded Runtime for Reconfigurable Dataflow Graphs on Manycore Architectures

Authors: Miomandre, Hugo Hascoët, Julien Desnos, Karol et al.

Contributors: Miomandre, Hugo Hascoët, Julien Desnos, Karol et al.

Source: PARMA-DITAM ; https://hal.science/hal-01704702 ; PARMA-DITAM, Jan 2018, Manchester, United Kingdom. ⟨10.1145/3183767.3183780⟩

Subject Terms: ACM: C.: Computer Systems Organization, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.4: Parallel Architectures, [INFO.INFO-ES]Computer Science [cs]/Embedded Systems

Subject Geographic: Manchester, United Kingdom

Availability: https://hal.science/hal-01704702
https://hal.science/hal-01704702v1/document
https://hal.science/hal-01704702v1/file/parma-ditam18.pdf
https://doi.org/10.1145/3183767.3183780

Distributed Architecture for Resource Management in Large Scale Grids

Authors: Jeanvoine, Emmanuel Rilling, Louis Morin, Christine et al.

Contributors: Jeanvoine, Emmanuel Rilling, Louis Morin, Christine et al.

Source: https://inria.hal.science/inria-00001066 ; [Research Report] PI 1775, 2006, pp.13.

Subject Terms: Grid computing, distributed system, peer-to-peer overlay networks, resource allocation, self-healing \\ Grille de calcul, système distribué, réseaux logiques pair-à-pair, allocation de ressources, auto-réparation, ACM: C.: Computer Systems Organization/C.2: COMPUTER-COMMUNICATION NETWORKS/C.2.4: Distributed Systems, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.4: Parallel Architectures, [INFO.INFO-OH]Computer Science [cs]/Other [cs.OH]

Relation: Report N°: PI 1775

Availability: https://inria.hal.science/inria-00001066
https://inria.hal.science/inria-00001066v1/document
https://inria.hal.science/inria-00001066v1/file/PI-1775.pdf

VLSI design of 1-D DWT architecture with parallel filters

Authors: Souani, C. Abid, M. Torki, K. et al.

Contributors: Souani, C. Abid, M. Torki, K. et al.

Source: Integration. 29:181-207

Subject Terms: Computer system organization, discrete wavelet transform, parallel filters, VLSI design, DWT processor, 02 engineering and technology, adaptive-signal-processing, discrete-wavelet-transforms, Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.), VLSI, PACS 85.42, 0202 electrical engineering, electronic engineering, information engineering, new optimized architecture, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, digital-signal-processing-chips, parallel-architectures

File Description: application/xml

Access URL: https://zbmath.org/1542293
https://doi.org/10.1016/s0167-9260(00)00007-9
https://dblp.uni-trier.de/db/journals/integration/integration29.html#SouaniATT00
https://doi.org/10.1016/S0167-9260(00)00007-9
http://www.sciencedirect.com/science/article/pii/S0167926000000079
https://www.sciencedirect.com/science/article/abs/pii/S0167926000000079

Processor-embedded distributed smart disks for I/O-intensive workloads: architectures, performance models and evaluation

Authors: LiaoWei-keng N ChoudharyAlok T KandemirMahmut et al.

Source: Journal of Parallel and Distributed Computing. 65:532-551

Subject Terms: Computer system organization, Parallel I/O, Embedded systems, I/O architecture, 1. No poverty, 02 engineering and technology, Data clustering, Distributed systems, Reliability, testing and fault tolerance of networks and computer systems, Smart disk, InfiniBand, 0202 electrical engineering, electronic engineering, information engineering, Association rules mining, disk-based distributed smart storage architectures

File Description: application/xml

Access URL: https://dl.acm.org/doi/10.1016/j.jpdc.2004.01.006

On-Chip Memory Architecture Exploration Framework for DSP Processor-Based Embedded System on Chip.

Authors: Kumar, T. S. Rajesh Govindarajan, R. Ravikumar, C. P.

Source: ACM Transactions on Embedded Computing Systems; Mar2012, Vol. 11 Issue 1, p1-25, 25p

Subject Terms: SYSTEMS on a chip, COMPUTER storage devices, COMPUTER architecture, DIGITAL signal processing, EMBEDDED computer systems, PERFORMANCE evaluation, PERSONAL computers

A Survey on Memory-centric Computer Architectures.

Authors: GEBREGIORGIS, ANTENEH HOANG ANH DU NGUYEN JINTAO YU et al.

Source: ACM Journal on Emerging Technologies in Computing Systems; Oct2022, Vol. 18 Issue 4, p1-50, 50p

Subject Terms: COMPUTER architecture, INTERNET surveys, PARALLEL processing

Synchronous byzantine agreement with nearly a cubic number of communication bits

Authors: Kowalski, Dariusz R. Mostefaoui, Achour Department of Computer Science Liverpool et al.

Contributors: Kowalski, Dariusz R. Mostefaoui, Achour Department of Computer Science Liverpool et al.

Source: ACM symposium on Principles of distributed computing (PODC'13) ; https://hal.science/hal-01151136 ; ACM symposium on Principles of distributed computing (PODC'13), Jul 2013, New-York, United States. pp.84-91, ⟨10.1145/2484239.2484271⟩

Subject Terms: Agreement problem, Synchronous distributed system, Byzantine process, Message-passing model, Round-based protocol, EIG, Consensus, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.4: Parallel Architectures/C.1.4.0: Distributed architectures, ACM: C.: Computer Systems Organization/C.2: COMPUTER-COMMUNICATION NETWORKS/C.2.4: Distributed Systems, ACM: D.: Software/D.4: OPERATING SYSTEMS/D.4.7: Organization and Design/D.4.7.1: Distributed systems, ACM: D.: Software/D.4: OPERATING SYSTEMS/D.4.5: Reliability/D.4.5.2: Fault-tolerance, ACM: D.: Software/D.4: OPERATING SYSTEMS/D.4.1: Process Management/D.4.1.0: Concurrency, ACM: D.: Software/D.4: OPERATING SYSTEMS/D.4.1: Process Management/D.4.1.5: Synchronization, [INFO]Computer Science [cs], [INFO.INFO-DC]Computer Science [cs]/Distributed, Parallel, and Cluster Computing [cs.DC], [INFO.INFO-DS]Computer Science [cs]/Data Structures and Algorithms [cs.DS]

Subject Geographic: New-York, United States

Availability: https://hal.science/hal-01151136
https://hal.science/hal-01151136v1/document
https://hal.science/hal-01151136v1/file/podc%20final.pdf
https://doi.org/10.1145/2484239.2484271

Parameter Exploration to Improve Performance of Memristor-Based Neuromorphic Architectures

Authors: Mahyar Shahsavari Pierre Boulet Boulet, Pierre et al.

Contributors: Mahyar Shahsavari Pierre Boulet Boulet, Pierre et al.

Source: IEEE Transactions on Multi-Scale Computing Systems. 4:833-846

Subject Terms: [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], Neuromorphic Computing, 0301 basic medicine, [INFO.INFO-DC]Computer Science [cs]/Distributed, [INFO.INFO-AR] Computer Science [cs]/Hardware Architecture [cs.AR], ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.3: Other Architecture Styles/C.1.3.7: Neural nets, [INFO.INFO-NE] Computer Science [cs]/Neural and Evolutionary Computing [cs.NE], Unsupervised Learning, 02 engineering and technology, [INFO.INFO-NE]Computer Science [cs]/Neural and Evolutionary Computing [cs.NE], Memristor, Parallel, [INFO.INFO-ES] Computer Science [cs]/Embedded Systems, Spiking Neural Networks, 03 medical and health sciences, and Cluster Computing [cs.DC], Parameter Evaluations, [INFO.INFO-ET] Computer Science [cs]/Emerging Technologies [cs.ET], [INFO.INFO-DC] Computer Science [cs]/Distributed, Parallel, and Cluster Computing [cs.DC], 0202 electrical engineering, electronic engineering, information engineering, [INFO.INFO-ES]Computer Science [cs]/Embedded Systems, [INFO.INFO-ET]Computer Science [cs]/Emerging Technologies [cs.ET]

File Description: application/pdf

Access URL: https://hal.archives-ouvertes.fr/hal-01615032/file/TMSCSSI-2016-10-0051.R1-main.pdf
https://ieeexplore.ieee.org/document/8063353
https://hal.archives-ouvertes.fr/hal-01615032/document
https://jglobal.jst.go.jp/en/detail?JGLOBAL_ID=201902258056300336
https://dblp.uni-trier.de/db/journals/tmscs/tmscs4.html#ShahsavariB18
https://hal.archives-ouvertes.fr/hal-01615032
https://hal.science/hal-01615032v1/document
https://hal.science/hal-01615032v1
https://doi.org/10.1109/tmscs.2017.2761231

An architecture for tolerating processor failures in shared-memory multiprocessors: An architecture for tolerating processor failures in shared-memory multiprocessors.

Authors: Banatre M Gefflaut A Joubert P et al.

Contributors: Banatre M Gefflaut A Joubert P et al.

Source: IEEE Transactions on Computers. 45:1101-1115

Subject Terms: Computer system organization, TAF, 0103 physical sciences, FASST, [INFO.INFO-DC] Computer Science [cs]/Distributed, Parallel, and Cluster Computing [cs.DC], 0202 electrical engineering, electronic engineering, information engineering, fault tolerance, 02 engineering and technology, 01 natural sciences, Reliability, testing and fault tolerance of networks and computer systems, backward error recovery

File Description: application/xml

Access URL: https://hal.inria.fr/inria-00074708/file/RR-1965.pdf
https://zbmath.org/1966772
https://doi.org/10.1109/12.543705
https://inria.hal.science/hal-01271108v1
https://dblp.uni-trier.de/db/journals/tc/tc45.html#BanatreGJML96
https://hal.archives-ouvertes.fr/hal-01276682
https://ieeexplore.ieee.org/document/543705/
https://hal.inria.fr/inria-00074708
https://hal.inria.fr/inria-00074708/document
https://dl.acm.org/doi/10.1109/12.543705

The Bulk Multicore Architecture for Improved Programmability. (cover story)

Authors: TORRELAS, JOSEP CEZE, LUIS TUCK, JAMES et al.

Source: Communications of the ACM; Dec2009, Vol. 52 Issue 12, p58-65, 8p, 1 Color Photograph, 7 Diagrams

Subject Terms: COMPUTER architecture, MULTIPROCESSORS, MICROPROCESSOR programming, PARALLEL processing, PARALLEL programming, SCALABILITY

Flexible Web-Based Educational System for Teaching Computer Architecture and Organization.

Authors: Djordjevic, Jovan Nikolic, Bosko Milenkovic, Aleksandar

Source: IEEE Transactions on Education; May2005, Vol. 48 Issue 2, p264-273, 10p

Subject Terms: COMPUTER training, EDUCATION, TEACHING, COMPUTER architecture, COMPUTER input-output equipment, COMPUTER science

6.823 Computer System Architecture, Spring 2002 ; Computer System Architecture

Authors: Asanovic, Krste Arvind, V. Devadas, Srinivas et al.

Contributors: Asanovic, Krste Arvind, V. Devadas, Srinivas et al.

Subject Terms: computer architecture, computer system architecture, hardware, hardware design, software, software design, instruction set design, processor micro-architecture, pipelining, cache memory, virtual memory, I/O, input/output, interrupts, superscalar architectures, VLIW machines, vector supercomputers, multithreaded architectures, symmetric multiprocessors, parallel computers

Subject Geographic: Spring 2002

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Relation: local: 6.823; http://hdl.handle.net/1721.1/35849

Availability: http://hdl.handle.net/1721.1/35849

Survey of Models and Architectures to Ensure Linked Data Access

Authors: Toure, Mahamadou Gandon, Fabien Guidedi, Kaladzavi et al.

Contributors: Toure, Mahamadou Gandon, Fabien Guidedi, Kaladzavi et al.

Source: https://inria.hal.science/hal-03956456 ; Inria & Université Côte d'Azur, CNRS, I3S. 2023, pp.23.

Subject Terms: Web of Data, Gossip protocol, graph replication, limited connectivity, semantic overlay, mobile contributor, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.4: Parallel Architectures/C.1.4.0: Distributed architectures, ACM: I.: Computing Methodologies/I.2: ARTIFICIAL INTELLIGENCE/I.2.4: Knowledge Representation Formalisms and Methods, [INFO.INFO-DS]Computer Science [cs]/Data Structures and Algorithms [cs.DS]

Availability: https://inria.hal.science/hal-03956456
https://inria.hal.science/hal-03956456v1/document
https://inria.hal.science/hal-03956456v1/file/MahamadouToureSurvey.pdf

Software Abstractions for Parallel Architectures ; Abstractions Logicielles pour Architectures Parallèles

Authors: Falcou, Joel Systèmes parallèles (LRI) (ParSys - LRI) Laboratoire de Recherche en Informatique (LRI) et al.

Contributors: Falcou, Joel Systèmes parallèles (LRI) (ParSys - LRI) Laboratoire de Recherche en Informatique (LRI) et al.

Source: https://inria.hal.science/tel-01111708 ; Distributed, Parallel, and Cluster Computing [cs.DC]. Universite de Paris 11, 2014.

Subject Terms: parallel programming, generic programming, generative programming, meta-programming, parallel skeletons, programmation parallèle, méta-programmation, programmation générative, programmation générique, squelettes parallèles, ACM: D.: Software/D.2: SOFTWARE ENGINEERING, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.4: Parallel Architectures, [INFO.INFO-DC]Computer Science [cs]/Distributed, Parallel, and Cluster Computing [cs.DC]

Availability: https://inria.hal.science/tel-01111708
https://inria.hal.science/tel-01111708v1/document
https://inria.hal.science/tel-01111708v1/file/Thesis.pdf

Novel Architecture of Smart FFT Processor

Authors: Teymourzadeh, Rozita University of California San Francisco (UC San Francisco) University of California (UC)

Contributors: Teymourzadeh, Rozita University of California San Francisco (UC San Francisco) University of California (UC)

Source: https://hal.archives-ouvertes.fr/hal-01802071 ; 2014.

Subject Terms: FFT, Digital Design, Processor, VLSI, Novel Architecture, Radix, Harmonic, ACM: D.: Software, ACM: B.: Hardware, ACM: C.: Computer Systems Organization, ACM: I.: Computing Methodologies, ACM: B.: Hardware/B.6: LOGIC DESIGN, ACM: B.: Hardware/B.5: REGISTER-TRANSFER-LEVEL IMPLEMENTATION, ACM: D.: Software/D.3: PROGRAMMING LANGUAGES, [INFO]Computer Science [cs], [INFO.INFO-AO]Computer Science [cs]/Computer Arithmetic, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [INFO.INFO-ES]Computer Science [cs]/Embedded Systems, [INFO.INFO-TS]Computer Science [cs]/Signal and Image Processing, [SPI]Engineering Sciences [physics], [SPI.SIGNAL]Engineering Sciences [physics]/Signal and Image processing, [SPI.TRON]Engineering Sciences [physics]/Electronics

Relation: hal-01802071; https://hal.archives-ouvertes.fr/hal-01802071; https://hal.archives-ouvertes.fr/hal-01802071/document; https://hal.archives-ouvertes.fr/hal-01802071/file/Novel%20Architecture%20of%20Smart%20FFT%20Processor_Draft.pdf

Availability: https://hal.archives-ouvertes.fr/hal-01802071
https://hal.archives-ouvertes.fr/hal-01802071/document
https://hal.archives-ouvertes.fr/hal-01802071/file/Novel%20Architecture%20of%20Smart%20FFT%20Processor_Draft.pdf

A continuation-based noninterruptible multithreading processor architecture.

Authors: Amamiya, Satoshi Amamiya, Makoto Hasegawa, Ryuzo et al.

Source: Journal of Supercomputing; Feb2009, Vol. 47 Issue 2, p228-252, 25p, 18 Diagrams, 1 Chart, 10 Graphs

Subject Terms: INTEGRATED circuits, SIMULTANEOUS multithreading processors, COMPUTER architecture, COMPUTERS, COMPUTER operating systems, COMPUTER software, COMPUTER programming

Configurable simulator for computer architecture and organization.

Authors: Radivojevic, Zaharije Stanisavljevic, Zarko Punt, Marija

Source: Computer Applications in Engineering Education; Sep2018, Vol. 26 Issue 5, p1711-1724, 14p, 10 Diagrams, 2 Charts, 2 Graphs

Subject Terms: COMPUTER architecture, STUDENTS, COMPUTER systems, MICROPROGRAMMING, COMPUTER programming

Architectures of Flexible Symmetric Key Crypto Engines-A Survey: From Hardware Coprocessor to Multi-Crypto-Processor System on Chip.

Authors: BOSSUET, LILIAN GRAND, MICHAEL GASPAR, LUBOS et al.

Source: ACM Computing Surveys; Aug2013, Vol. 45 Issue 4, p41-41:32, 32p, 9 Diagrams, 3 Charts, 2 Graphs

Subject Terms: CRYPTOGRAPHY research, COMPUTER network security, COMPUTER architecture, FAULT-tolerant computing, FAULT tolerance (Engineering), RELIABILITY in engineering