Suchergebnisse - acm: c.: computer system organization/c.1: processor architecture/c.1.4: parallel architecture

Towards a New Processor Architecture. ; Vers une nouvelle Architecture de Processeurs

Autoren: Vincent, Pierre Landru, Jacques Ecole nationale supérieure Mines-Télécom Lille Douai (IMT Nord Europe) et al.

Weitere Verfasser: Vincent, Pierre Landru, Jacques Ecole nationale supérieure Mines-Télécom Lille Douai (IMT Nord Europe) et al.

Quelle: https://hal.science/hal-05117313 ; 2025.

Schlagwörter: silicon, parallel, serial, RISC, photonics, computer, optronics, optics, processor, fiber, laser, digital, silicium, parallèle, série, processeur, photonique, ordinateur, optronique, optique, numérique, fibre, ACM: B.: Hardware, ACM: C.: Computer Systems Organization, [INFO]Computer Science [cs], [PHYS]Physics [physics]

Verfügbarkeit: https://hal.science/hal-05117313
https://hal.science/hal-05117313v2/document
https://hal.science/hal-05117313v2/file/frParalSerieRiscV1.pdf

Distributed Architecture for Resource Management in Large Scale Grids

Autoren: Jeanvoine, Emmanuel Rilling, Louis Morin, Christine et al.

Weitere Verfasser: Jeanvoine, Emmanuel Rilling, Louis Morin, Christine et al.

Quelle: https://inria.hal.science/inria-00001066 ; [Research Report] PI 1775, 2006, pp.13.

Schlagwörter: Grid computing, distributed system, peer-to-peer overlay networks, resource allocation, self-healing \\ Grille de calcul, système distribué, réseaux logiques pair-à-pair, allocation de ressources, auto-réparation, ACM: C.: Computer Systems Organization/C.2: COMPUTER-COMMUNICATION NETWORKS/C.2.4: Distributed Systems, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.4: Parallel Architectures, [INFO.INFO-OH]Computer Science [cs]/Other [cs.OH]

Relation: Report N°: PI 1775

Verfügbarkeit: https://inria.hal.science/inria-00001066
https://inria.hal.science/inria-00001066v1/document
https://inria.hal.science/inria-00001066v1/file/PI-1775.pdf

The Bulk Multicore Architecture for Improved Programmability. (cover story)

Autoren: TORRELAS, JOSEP CEZE, LUIS TUCK, JAMES et al.

Quelle: Communications of the ACM; Dec2009, Vol. 52 Issue 12, p58-65, 8p, 1 Color Photograph, 7 Diagrams

Schlagwörter: COMPUTER architecture, MULTIPROCESSORS, MICROPROCESSOR programming, PARALLEL processing, PARALLEL programming, SCALABILITY

7 Probabilistic Modeling for Job Symbiosis Scheduling on SMT Processors

Autoren: Stijn Eyerman Lieven Eeckhout The Pennsylvania State University CiteSeerX Archives

Weitere Verfasser: Stijn Eyerman Lieven Eeckhout The Pennsylvania State University CiteSeerX Archives

Quelle: http://users.elis.ugent.be/~leeckhou/papers/taco12_2.pdf.

Schlagwörter: Categories and Subject Descriptors, C.0 [Computer Systems Organization, General—Modeling of computer architecture, C.1.4 [Processor Architectures, Parallel Architectures, C.4 [Computer Systems Organization, Performance of Systems—Modeling techniques General Terms, Design, Experimentation, Measurement, Performance Additional Key Words and Phrases, Simultaneous multithreading (SMT, symbiotic job scheduling, performance modeling ACM Reference Format

Dateibeschreibung: application/pdf

Relation: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.308.3569; http://users.elis.ugent.be/~leeckhou/papers/taco12_2.pdf

Verfügbarkeit: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.308.3569
http://users.elis.ugent.be/~leeckhou/papers/taco12_2.pdf

On-Chip Memory Architecture Exploration Framework for DSP Processor-Based Embedded System on Chip.

Autoren: Kumar, T. S. Rajesh Govindarajan, R. Ravikumar, C. P.

Quelle: ACM Transactions on Embedded Computing Systems; Mar2012, Vol. 11 Issue 1, p1-25, 25p

Schlagwörter: SYSTEMS on a chip, COMPUTER storage devices, COMPUTER architecture, DIGITAL signal processing, EMBEDDED computer systems, PERFORMANCE evaluation, PERSONAL computers

Embedded Runtime for Reconfigurable Dataflow Graphs on Manycore Architectures

Autoren: Miomandre, Hugo Hascoët, Julien Desnos, Karol et al.

Weitere Verfasser: Miomandre, Hugo Hascoët, Julien Desnos, Karol et al.

Quelle: PARMA-DITAM ; https://hal.science/hal-01704702 ; PARMA-DITAM, Jan 2018, Manchester, United Kingdom. ⟨10.1145/3183767.3183780⟩

Schlagwörter: ACM: C.: Computer Systems Organization, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.4: Parallel Architectures, [INFO.INFO-ES]Computer Science [cs]/Embedded Systems

Geographisches Schlagwort: Manchester, United Kingdom

Verfügbarkeit: https://hal.science/hal-01704702
https://hal.science/hal-01704702v1/document
https://hal.science/hal-01704702v1/file/parma-ditam18.pdf
https://doi.org/10.1145/3183767.3183780

Flexible Web-Based Educational System for Teaching Computer Architecture and Organization.

Autoren: Djordjevic, Jovan Nikolic, Bosko Milenkovic, Aleksandar

Quelle: IEEE Transactions on Education; May2005, Vol. 48 Issue 2, p264-273, 10p

Schlagwörter: COMPUTER training, EDUCATION, TEACHING, COMPUTER architecture, COMPUTER input-output equipment, COMPUTER science

A continuation-based noninterruptible multithreading processor architecture.

Autoren: Amamiya, Satoshi Amamiya, Makoto Hasegawa, Ryuzo et al.

Quelle: Journal of Supercomputing; Feb2009, Vol. 47 Issue 2, p228-252, 25p, 18 Diagrams, 1 Chart, 10 Graphs

Schlagwörter: INTEGRATED circuits, SIMULTANEOUS multithreading processors, COMPUTER architecture, COMPUTERS, COMPUTER operating systems, COMPUTER software, COMPUTER programming

Novel Architecture of Smart FFT Processor

Autoren: Teymourzadeh, Rozita University of California San Francisco (UC San Francisco) University of California (UC)

Weitere Verfasser: Teymourzadeh, Rozita University of California San Francisco (UC San Francisco) University of California (UC)

Quelle: https://hal.archives-ouvertes.fr/hal-01802071 ; 2014.

Schlagwörter: FFT, Digital Design, Processor, VLSI, Novel Architecture, Radix, Harmonic, ACM: D.: Software, ACM: B.: Hardware, ACM: C.: Computer Systems Organization, ACM: I.: Computing Methodologies, ACM: B.: Hardware/B.6: LOGIC DESIGN, ACM: B.: Hardware/B.5: REGISTER-TRANSFER-LEVEL IMPLEMENTATION, ACM: D.: Software/D.3: PROGRAMMING LANGUAGES, [INFO]Computer Science [cs], [INFO.INFO-AO]Computer Science [cs]/Computer Arithmetic, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [INFO.INFO-ES]Computer Science [cs]/Embedded Systems, [INFO.INFO-TS]Computer Science [cs]/Signal and Image Processing, [SPI]Engineering Sciences [physics], [SPI.SIGNAL]Engineering Sciences [physics]/Signal and Image processing, [SPI.TRON]Engineering Sciences [physics]/Electronics

Relation: hal-01802071; https://hal.archives-ouvertes.fr/hal-01802071; https://hal.archives-ouvertes.fr/hal-01802071/document; https://hal.archives-ouvertes.fr/hal-01802071/file/Novel%20Architecture%20of%20Smart%20FFT%20Processor_Draft.pdf

Verfügbarkeit: https://hal.archives-ouvertes.fr/hal-01802071
https://hal.archives-ouvertes.fr/hal-01802071/document
https://hal.archives-ouvertes.fr/hal-01802071/file/Novel%20Architecture%20of%20Smart%20FFT%20Processor_Draft.pdf

Organization of Parallel Query Processing in Multiprocessor Database Machines with Hierarchical Architecture.

Autoren: L. B. Sokolinsky

Quelle: Programming & Computer Software; Nov2001, Vol. 27 Issue 6, p297-308, 12p

6.823 Computer System Architecture, Spring 2002 ; Computer System Architecture

Autoren: Asanovic, Krste Arvind, V. Devadas, Srinivas et al.

Weitere Verfasser: Asanovic, Krste Arvind, V. Devadas, Srinivas et al.

Schlagwörter: computer architecture, computer system architecture, hardware, hardware design, software, software design, instruction set design, processor micro-architecture, pipelining, cache memory, virtual memory, I/O, input/output, interrupts, superscalar architectures, VLIW machines, vector supercomputers, multithreaded architectures, symmetric multiprocessors, parallel computers

Geographisches Schlagwort: Spring 2002

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Relation: local: 6.823; http://hdl.handle.net/1721.1/35849

Verfügbarkeit: http://hdl.handle.net/1721.1/35849

Synchronous byzantine agreement with nearly a cubic number of communication bits

Autoren: Kowalski, Dariusz R. Mostefaoui, Achour Department of Computer Science Liverpool et al.

Weitere Verfasser: Kowalski, Dariusz R. Mostefaoui, Achour Department of Computer Science Liverpool et al.

Quelle: ACM symposium on Principles of distributed computing (PODC'13) ; https://hal.science/hal-01151136 ; ACM symposium on Principles of distributed computing (PODC'13), Jul 2013, New-York, United States. pp.84-91, ⟨10.1145/2484239.2484271⟩

Schlagwörter: Agreement problem, Synchronous distributed system, Byzantine process, Message-passing model, Round-based protocol, EIG, Consensus, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.4: Parallel Architectures/C.1.4.0: Distributed architectures, ACM: C.: Computer Systems Organization/C.2: COMPUTER-COMMUNICATION NETWORKS/C.2.4: Distributed Systems, ACM: D.: Software/D.4: OPERATING SYSTEMS/D.4.7: Organization and Design/D.4.7.1: Distributed systems, ACM: D.: Software/D.4: OPERATING SYSTEMS/D.4.5: Reliability/D.4.5.2: Fault-tolerance, ACM: D.: Software/D.4: OPERATING SYSTEMS/D.4.1: Process Management/D.4.1.0: Concurrency, ACM: D.: Software/D.4: OPERATING SYSTEMS/D.4.1: Process Management/D.4.1.5: Synchronization, [INFO]Computer Science [cs], [INFO.INFO-DC]Computer Science [cs]/Distributed, Parallel, and Cluster Computing [cs.DC], [INFO.INFO-DS]Computer Science [cs]/Data Structures and Algorithms [cs.DS]

Geographisches Schlagwort: New-York, United States

Verfügbarkeit: https://hal.science/hal-01151136
https://hal.science/hal-01151136v1/document
https://hal.science/hal-01151136v1/file/podc%20final.pdf
https://doi.org/10.1145/2484239.2484271

A universal parallel computer architecture.

Autoren: Dally, William

Quelle: New Generation Computing; Sep1993, Vol. 11 Issue 3/4, p227-249, 23p

Reconstruction of switching thresholds in piecewise-affine models of genetic regulatory networks

Autoren: Drulhe, Samuel Ferrari-Trecate, Giancarlo de Jong, Hidde et al.

Weitere Verfasser: Drulhe, Samuel Ferrari-Trecate, Giancarlo de Jong, Hidde et al.

Quelle: Hybrid Systems: Computation and Control, HSCC 2006 ; https://inria.hal.science/inria-00001225 ; Hybrid Systems: Computation and Control, HSCC 2006, Mar 2006, Santa Barbara, CA, USA, pp.184 - 199, ⟨10.1007/11730637⟩

Schlagwörter: Hybrid system, Genetic regulatory network, system identification, switching thresholds reconstruction, ACM: C.: Computer Systems Organization, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.3: Other Architecture Styles/C.1.3.5: Heterogeneous (hybrid) systems, ACM: I.: Computing Methodologies/I.6: SIMULATION AND MODELING/I.6.1: Simulation Theory/I.6.1.1: Systems theory, [SDV.OT]Life Sciences [q-bio]/Other [q-bio.OT]

Verfügbarkeit: https://inria.hal.science/inria-00001225
https://inria.hal.science/inria-00001225v1/document
https://inria.hal.science/inria-00001225v1/file/LNCS_HSCC06.pdf
https://doi.org/10.1007/11730637

p88110: A Graphical Simulator for Computer Architecture and Organization Courses.

Autoren: Garcia, M. Isabel Rodríguez, Santiago Perez, Antonio et al.

Quelle: IEEE Transactions on Education; May2009, Vol. 52 Issue 2, p248-256, 9p, 8 Charts, 2 Graphs

Schlagwörter: COMPUTER systems, COMPUTER architecture, REDUCED instruction set computers, ACTIVE learning, CACHE memory, COMPUTATION laboratories, EDUCATION

Geografische Kategorien: MADRID (Spain), SPAIN

Configurable simulator for computer architecture and organization.

Autoren: Radivojevic, Zaharije Stanisavljevic, Zarko Punt, Marija

Quelle: Computer Applications in Engineering Education; Sep2018, Vol. 26 Issue 5, p1711-1724, 14p, 10 Diagrams, 2 Charts, 2 Graphs

Schlagwörter: COMPUTER architecture, STUDENTS, COMPUTER systems, MICROPROGRAMMING, COMPUTER programming

Can Parallel Algorithms Enhance Serial Implementations?

Autoren: Vishkin, Uzi

Quelle: Communications of the ACM; Sep96, Vol. 39 Issue 9, p88-91, 4p

Schlagwörter: COMPUTER software, COMPUTER architecture, COMPUTER science, MULTIPROCESSORS, PARALLEL computers, PARALLEL programming

Using Network Processor to Establish Security Agent for AODV Routing Protocol.

Autoren: Chen Hongsong Fu Zhongchuan Wang Chengyao et al.

Quelle: Journal of Computing & Information Technology; Mar2007, Vol. 15 Issue 1, p61-70, 10p

Schlagwörter: COMPUTER architecture, COMPUTER network security, COMPUTER security, ALGORITHMS, COMPUTER simulation, PARALLEL processing

Processor Design for Soft Errors: Challenges and State of the Art.

Autoren: LI, TUO AMBROSE, JUDE ANGELO RAGEL, ROSHAN et al.

Quelle: ACM Computing Surveys; Dec2016, Vol. 49 Issue 3, p1-44, 44p, 3 Diagrams, 4 Charts, 1 Graph

Schlagwörter: SOFT errors, MICROPROCESSOR design & construction, ERROR rates, COMPUTER architecture, DATA, ERROR detection (Information theory)

A Hands-on approach in Teaching Computer Organization & Architecture through Project Based Learning.

Autoren: Nayak, Aruna S. Hiremath, Namrata D. F. M., Umadevi et al.

Quelle: Journal of Engineering Education Transformations; 2021 Special Issue, Vol. 34, p742-746, 5p

Schlagwörter: COMPUTER science education, COMPUTER organization, COMPUTER architecture, PROJECT method in teaching, ENGINEERING education, EXPERIENTIAL learning, CRITICAL thinking