Výsledky vyhľadávania - acm: c.: computer system organization/c.1: processor architecture/c.1.4: parallel architecture*

Towards a New Processor Architecture. ; Vers une nouvelle Architecture de Processeurs

Autori: Vincent, Pierre Landru, Jacques Ecole nationale supérieure Mines-Télécom Lille Douai (IMT Nord Europe) a ďalší

Prispievatelia: Vincent, Pierre Landru, Jacques Ecole nationale supérieure Mines-Télécom Lille Douai (IMT Nord Europe) a ďalší

Zdroj: https://hal.science/hal-05117313 ; 2025.

Predmety: silicon, parallel, serial, RISC, photonics, computer, optronics, optics, processor, fiber, laser, digital, silicium, parallèle, série, processeur, photonique, ordinateur, optronique, optique, numérique, fibre, ACM: B.: Hardware, ACM: C.: Computer Systems Organization, [INFO]Computer Science [cs], [PHYS]Physics [physics]

Dostupnosť: https://hal.science/hal-05117313
https://hal.science/hal-05117313v2/document
https://hal.science/hal-05117313v2/file/frParalSerieRiscV1.pdf

Distributed Architecture for Resource Management in Large Scale Grids

Autori: Jeanvoine, Emmanuel Rilling, Louis Morin, Christine a ďalší

Prispievatelia: Jeanvoine, Emmanuel Rilling, Louis Morin, Christine a ďalší

Zdroj: https://inria.hal.science/inria-00001066 ; [Research Report] PI 1775, 2006, pp.13.

Predmety: Grid computing, distributed system, peer-to-peer overlay networks, resource allocation, self-healing \\ Grille de calcul, système distribué, réseaux logiques pair-à-pair, allocation de ressources, auto-réparation, ACM: C.: Computer Systems Organization/C.2: COMPUTER-COMMUNICATION NETWORKS/C.2.4: Distributed Systems, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.4: Parallel Architectures, [INFO.INFO-OH]Computer Science [cs]/Other [cs.OH]

Relation: Report N°: PI 1775

Dostupnosť: https://inria.hal.science/inria-00001066
https://inria.hal.science/inria-00001066v1/document
https://inria.hal.science/inria-00001066v1/file/PI-1775.pdf

The Bulk Multicore Architecture for Improved Programmability. (cover story)

Autori: TORRELAS, JOSEP CEZE, LUIS TUCK, JAMES a ďalší

Zdroj: Communications of the ACM; Dec2009, Vol. 52 Issue 12, p58-65, 8p, 1 Color Photograph, 7 Diagrams

Predmety: COMPUTER architecture, MULTIPROCESSORS, MICROPROCESSOR programming, PARALLEL processing, PARALLEL programming, SCALABILITY

7 Probabilistic Modeling for Job Symbiosis Scheduling on SMT Processors

Autori: Stijn Eyerman Lieven Eeckhout The Pennsylvania State University CiteSeerX Archives

Prispievatelia: Stijn Eyerman Lieven Eeckhout The Pennsylvania State University CiteSeerX Archives

Zdroj: http://users.elis.ugent.be/~leeckhou/papers/taco12_2.pdf.

Predmety: Categories and Subject Descriptors, C.0 [Computer Systems Organization, General—Modeling of computer architecture, C.1.4 [Processor Architectures, Parallel Architectures, C.4 [Computer Systems Organization, Performance of Systems—Modeling techniques General Terms, Design, Experimentation, Measurement, Performance Additional Key Words and Phrases, Simultaneous multithreading (SMT, symbiotic job scheduling, performance modeling ACM Reference Format

Popis súboru: application/pdf

Relation: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.308.3569; http://users.elis.ugent.be/~leeckhou/papers/taco12_2.pdf

Dostupnosť: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.308.3569
http://users.elis.ugent.be/~leeckhou/papers/taco12_2.pdf

On-Chip Memory Architecture Exploration Framework for DSP Processor-Based Embedded System on Chip.

Autori: Kumar, T. S. Rajesh Govindarajan, R. Ravikumar, C. P.

Zdroj: ACM Transactions on Embedded Computing Systems; Mar2012, Vol. 11 Issue 1, p1-25, 25p

Predmety: SYSTEMS on a chip, COMPUTER storage devices, COMPUTER architecture, DIGITAL signal processing, EMBEDDED computer systems, PERFORMANCE evaluation, PERSONAL computers

Embedded Runtime for Reconfigurable Dataflow Graphs on Manycore Architectures

Autori: Miomandre, Hugo Hascoët, Julien Desnos, Karol a ďalší

Prispievatelia: Miomandre, Hugo Hascoët, Julien Desnos, Karol a ďalší

Zdroj: PARMA-DITAM ; https://hal.science/hal-01704702 ; PARMA-DITAM, Jan 2018, Manchester, United Kingdom. ⟨10.1145/3183767.3183780⟩

Predmety: ACM: C.: Computer Systems Organization, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.4: Parallel Architectures, [INFO.INFO-ES]Computer Science [cs]/Embedded Systems

Geografické téma: Manchester, United Kingdom

Dostupnosť: https://hal.science/hal-01704702
https://hal.science/hal-01704702v1/document
https://hal.science/hal-01704702v1/file/parma-ditam18.pdf
https://doi.org/10.1145/3183767.3183780

A continuation-based noninterruptible multithreading processor architecture.

Autori: Amamiya, Satoshi Amamiya, Makoto Hasegawa, Ryuzo a ďalší

Zdroj: Journal of Supercomputing; Feb2009, Vol. 47 Issue 2, p228-252, 25p, 18 Diagrams, 1 Chart, 10 Graphs

Predmety: INTEGRATED circuits, SIMULTANEOUS multithreading processors, COMPUTER architecture, COMPUTERS, COMPUTER operating systems, COMPUTER software, COMPUTER programming

Flexible Web-Based Educational System for Teaching Computer Architecture and Organization.

Autori: Djordjevic, Jovan Nikolic, Bosko Milenkovic, Aleksandar

Zdroj: IEEE Transactions on Education; May2005, Vol. 48 Issue 2, p264-273, 10p

Predmety: COMPUTER training, EDUCATION, TEACHING, COMPUTER architecture, COMPUTER input-output equipment, COMPUTER science

Novel Architecture of Smart FFT Processor

Autori: Teymourzadeh, Rozita University of California San Francisco (UC San Francisco) University of California (UC)

Prispievatelia: Teymourzadeh, Rozita University of California San Francisco (UC San Francisco) University of California (UC)

Zdroj: https://hal.archives-ouvertes.fr/hal-01802071 ; 2014.

Predmety: FFT, Digital Design, Processor, VLSI, Novel Architecture, Radix, Harmonic, ACM: D.: Software, ACM: B.: Hardware, ACM: C.: Computer Systems Organization, ACM: I.: Computing Methodologies, ACM: B.: Hardware/B.6: LOGIC DESIGN, ACM: B.: Hardware/B.5: REGISTER-TRANSFER-LEVEL IMPLEMENTATION, ACM: D.: Software/D.3: PROGRAMMING LANGUAGES, [INFO]Computer Science [cs], [INFO.INFO-AO]Computer Science [cs]/Computer Arithmetic, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [INFO.INFO-ES]Computer Science [cs]/Embedded Systems, [INFO.INFO-TS]Computer Science [cs]/Signal and Image Processing, [SPI]Engineering Sciences [physics], [SPI.SIGNAL]Engineering Sciences [physics]/Signal and Image processing, [SPI.TRON]Engineering Sciences [physics]/Electronics

Relation: hal-01802071; https://hal.archives-ouvertes.fr/hal-01802071; https://hal.archives-ouvertes.fr/hal-01802071/document; https://hal.archives-ouvertes.fr/hal-01802071/file/Novel%20Architecture%20of%20Smart%20FFT%20Processor_Draft.pdf

Dostupnosť: https://hal.archives-ouvertes.fr/hal-01802071
https://hal.archives-ouvertes.fr/hal-01802071/document
https://hal.archives-ouvertes.fr/hal-01802071/file/Novel%20Architecture%20of%20Smart%20FFT%20Processor_Draft.pdf

Organization of Parallel Query Processing in Multiprocessor Database Machines with Hierarchical Architecture.

Autori: L. B. Sokolinsky

Zdroj: Programming & Computer Software; Nov2001, Vol. 27 Issue 6, p297-308, 12p

6.823 Computer System Architecture, Spring 2002 ; Computer System Architecture

Autori: Asanovic, Krste Arvind, V. Devadas, Srinivas a ďalší

Prispievatelia: Asanovic, Krste Arvind, V. Devadas, Srinivas a ďalší

Predmety: computer architecture, computer system architecture, hardware, hardware design, software, software design, instruction set design, processor micro-architecture, pipelining, cache memory, virtual memory, I/O, input/output, interrupts, superscalar architectures, VLIW machines, vector supercomputers, multithreaded architectures, symmetric multiprocessors, parallel computers

Geografické téma: Spring 2002

Popis súboru: 15904 bytes; 18116 bytes; 76031 bytes; 38470 bytes; 13521 bytes; 17491 bytes; 17208 bytes; 11 bytes; 4586 bytes; 21366 bytes; 11602 bytes; 38351 bytes; 4755 bytes; 27322 bytes; 25313 bytes; 4039 bytes; 301 bytes; 354 bytes; 339 bytes; 180 bytes; 285 bytes; 67 bytes; 17685 bytes; 49 bytes; 143 bytes; 247 bytes; 19283 bytes; 262 bytes; 25949 bytes; 547311 bytes; 94135 bytes; 128447 bytes; 272685 bytes; 174522 bytes; 220321 bytes; 121050 bytes; 295953 bytes; 327250 bytes; 280519 bytes; 467767 bytes; 400880 bytes; 239528 bytes; 286310 bytes; 259091 bytes; 347438 bytes; 160795 bytes; 230943 bytes; 139072 bytes; 163877 bytes; 176304 bytes; 333149 bytes; 360886 bytes; 460427 bytes; 214591 bytes; 194918 bytes; 288178 bytes; 230380 bytes; 743706 bytes; 130008 bytes; 367269 bytes; 229817 bytes; 228911 bytes; 257717 bytes; 176594 bytes; 236711 bytes; 317637 bytes; 128440 bytes; 220287 bytes; 283791 bytes; 259095 bytes; 333152 bytes; 194914 bytes; 367265 bytes; 246274 bytes; 288561 bytes; 317555 bytes; 3486 bytes; 811 bytes; 813 bytes; 830 bytes; 573 bytes; 2097 bytes; 68877 bytes; 10290 bytes; 10280 bytes; 10259 bytes; 10289 bytes; 10256 bytes; 10262 bytes; 10226 bytes; 10242 bytes; 10668 bytes; 9922 bytes; 10240 bytes; 10247 bytes; 10051 bytes; 10239 bytes; 10621 bytes; 9759 bytes; 10266 bytes; 10318 bytes; 10265 bytes; 10850 bytes; 10310 bytes; 10246 bytes; 9622 bytes; 10276 bytes; 10250 bytes; 10269 bytes; 10326 bytes; 9976 bytes; 10263 bytes; 10366 bytes; 10298 bytes; 9909 bytes; 11017 bytes; 10292 bytes; 10071 bytes; 10303 bytes; 10241 bytes; 10260 bytes; 9750 bytes; 10287 bytes; 10236 bytes; text/html

Relation: local: 6.823; http://hdl.handle.net/1721.1/35849

Dostupnosť: http://hdl.handle.net/1721.1/35849

Synchronous byzantine agreement with nearly a cubic number of communication bits

Autori: Kowalski, Dariusz R. Mostefaoui, Achour Department of Computer Science Liverpool a ďalší

Prispievatelia: Kowalski, Dariusz R. Mostefaoui, Achour Department of Computer Science Liverpool a ďalší

Zdroj: ACM symposium on Principles of distributed computing (PODC'13) ; https://hal.science/hal-01151136 ; ACM symposium on Principles of distributed computing (PODC'13), Jul 2013, New-York, United States. pp.84-91, ⟨10.1145/2484239.2484271⟩

Predmety: Agreement problem, Synchronous distributed system, Byzantine process, Message-passing model, Round-based protocol, EIG, Consensus, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.4: Parallel Architectures/C.1.4.0: Distributed architectures, ACM: C.: Computer Systems Organization/C.2: COMPUTER-COMMUNICATION NETWORKS/C.2.4: Distributed Systems, ACM: D.: Software/D.4: OPERATING SYSTEMS/D.4.7: Organization and Design/D.4.7.1: Distributed systems, ACM: D.: Software/D.4: OPERATING SYSTEMS/D.4.5: Reliability/D.4.5.2: Fault-tolerance, ACM: D.: Software/D.4: OPERATING SYSTEMS/D.4.1: Process Management/D.4.1.0: Concurrency, ACM: D.: Software/D.4: OPERATING SYSTEMS/D.4.1: Process Management/D.4.1.5: Synchronization, [INFO]Computer Science [cs], [INFO.INFO-DC]Computer Science [cs]/Distributed, Parallel, and Cluster Computing [cs.DC], [INFO.INFO-DS]Computer Science [cs]/Data Structures and Algorithms [cs.DS]

Geografické téma: New-York, United States

Dostupnosť: https://hal.science/hal-01151136
https://hal.science/hal-01151136v1/document
https://hal.science/hal-01151136v1/file/podc%20final.pdf
https://doi.org/10.1145/2484239.2484271

A universal parallel computer architecture.

Autori: Dally, William

Zdroj: New Generation Computing; Sep1993, Vol. 11 Issue 3/4, p227-249, 23p

Reconstruction of switching thresholds in piecewise-affine models of genetic regulatory networks

Autori: Drulhe, Samuel Ferrari-Trecate, Giancarlo de Jong, Hidde a ďalší

Prispievatelia: Drulhe, Samuel Ferrari-Trecate, Giancarlo de Jong, Hidde a ďalší

Zdroj: Hybrid Systems: Computation and Control, HSCC 2006 ; https://inria.hal.science/inria-00001225 ; Hybrid Systems: Computation and Control, HSCC 2006, Mar 2006, Santa Barbara, CA, USA, pp.184 - 199, ⟨10.1007/11730637⟩

Predmety: Hybrid system, Genetic regulatory network, system identification, switching thresholds reconstruction, ACM: C.: Computer Systems Organization, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.3: Other Architecture Styles/C.1.3.5: Heterogeneous (hybrid) systems, ACM: I.: Computing Methodologies/I.6: SIMULATION AND MODELING/I.6.1: Simulation Theory/I.6.1.1: Systems theory, [SDV.OT]Life Sciences [q-bio]/Other [q-bio.OT]

Dostupnosť: https://inria.hal.science/inria-00001225
https://inria.hal.science/inria-00001225v1/document
https://inria.hal.science/inria-00001225v1/file/LNCS_HSCC06.pdf
https://doi.org/10.1007/11730637

p88110: A Graphical Simulator for Computer Architecture and Organization Courses.

Autori: Garcia, M. Isabel Rodríguez, Santiago Perez, Antonio a ďalší

Zdroj: IEEE Transactions on Education; May2009, Vol. 52 Issue 2, p248-256, 9p, 8 Charts, 2 Graphs

Predmety: COMPUTER systems, COMPUTER architecture, REDUCED instruction set computers, ACTIVE learning, CACHE memory, COMPUTATION laboratories, EDUCATION

Geografický termín: MADRID (Spain), SPAIN

Configurable simulator for computer architecture and organization.

Autori: Radivojevic, Zaharije Stanisavljevic, Zarko Punt, Marija

Zdroj: Computer Applications in Engineering Education; Sep2018, Vol. 26 Issue 5, p1711-1724, 14p, 10 Diagrams, 2 Charts, 2 Graphs

Predmety: COMPUTER architecture, STUDENTS, COMPUTER systems, MICROPROGRAMMING, COMPUTER programming

Can Parallel Algorithms Enhance Serial Implementations?

Autori: Vishkin, Uzi

Zdroj: Communications of the ACM; Sep96, Vol. 39 Issue 9, p88-91, 4p

Predmety: COMPUTER software, COMPUTER architecture, COMPUTER science, MULTIPROCESSORS, PARALLEL computers, PARALLEL programming

Processor Design for Soft Errors: Challenges and State of the Art.

Autori: LI, TUO AMBROSE, JUDE ANGELO RAGEL, ROSHAN a ďalší

Zdroj: ACM Computing Surveys; Dec2016, Vol. 49 Issue 3, p1-44, 44p, 3 Diagrams, 4 Charts, 1 Graph

Predmety: SOFT errors, MICROPROCESSOR design & construction, ERROR rates, COMPUTER architecture, DATA, ERROR detection (Information theory)

Using Network Processor to Establish Security Agent for AODV Routing Protocol.

Autori: Chen Hongsong Fu Zhongchuan Wang Chengyao a ďalší

Zdroj: Journal of Computing & Information Technology; Mar2007, Vol. 15 Issue 1, p61-70, 10p

Predmety: COMPUTER architecture, COMPUTER network security, COMPUTER security, ALGORITHMS, COMPUTER simulation, PARALLEL processing

A Hands-on approach in Teaching Computer Organization & Architecture through Project Based Learning.

Autori: Nayak, Aruna S. Hiremath, Namrata D. F. M., Umadevi a ďalší

Zdroj: Journal of Engineering Education Transformations; 2021 Special Issue, Vol. 34, p742-746, 5p

Predmety: COMPUTER science education, COMPUTER organization, COMPUTER architecture, PROJECT method in teaching, ENGINEERING education, EXPERIENTIAL learning, CRITICAL thinking