Search Results - acm: c.: computer system organization/c.1: processor architectural~

Design and Implementation of a MicroBlaze-Based Warp Processor.

Authors: LYSECKY, ROMAN VAHID, FRANK

Source: ACM Transactions on Embedded Computing Systems; Apr2009, Vol. 8 Issue 3, p22-22-22, 22p, 4 Diagrams, 2 Charts, 6 Graphs

Subject Terms: SYSTEMS design, NETWORK processors, FIELD programmable gate arrays, GATE array circuits, ELECTRIC power consumption, COMPUTER organization, EMBEDDED computer systems

Processor Design for Soft Errors: Challenges and State of the Art.

Authors: LI, TUO AMBROSE, JUDE ANGELO RAGEL, ROSHAN et al.

Source: ACM Computing Surveys; Dec2016, Vol. 49 Issue 3, p1-44, 44p, 3 Diagrams, 4 Charts, 1 Graph

Subject Terms: SOFT errors, MICROPROCESSOR design & construction, ERROR rates, COMPUTER architecture, DATA, ERROR detection (Information theory)

Hardware Architectural Support for Control Systems and Sensor Processing.

Authors: VYAS, SUDHANSHU GUPTE, ADWAIT GILL, CHRISTOPHER D. et al.

Source: ACM Transactions on Embedded Computing Systems; Sep2013, Vol. 13 Issue 2, p1-25, 25p

Subject Terms: COMPUTER input-output equipment, COMPUTER architecture, AUTOMATIC control systems, SENSOR networks, DIGITAL signal processing, ALGORITHMS, PID controllers

Micro-architectural simulation of embedded core heterogeneity with gem5 and McPAT

Authors: Endo, F.A. Couroussé, Damien Charles, H.-P. et al.

Contributors: Endo, F.A. Couroussé, Damien Charles, H.-P. et al.

Source: RAPIDO '15 Proceedings of the 2015 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools ; https://cea.hal.science/cea-01818887 ; RAPIDO '15 Proceedings of the 2015 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools, Jan 2015, Amsterdam, Netherlands. ⟨10.1145/2693433.2693440⟩

Subject Terms: ACM: I.: Computing Methodologies/I.6: SIMULATION AND MODELING/I.6.7: Simulation Support Systems, ACM: I.: Computing Methodologies/I.6: SIMULATION AND MODELING/I.6.7: Simulation Support Systems/I.6.7.0: Environments, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.1: Single Data Stream Architectures, [INFO]Computer Science [cs]

Subject Geographic: Amsterdam, Netherlands

Availability: https://cea.hal.science/cea-01818887
https://doi.org/10.1145/2693433.2693440

Probabilistic System-on-a-Chip Architectures

Authors: Lakshmi N. Chakrapani Pinar Korkmaz Bilge E. S. Akgul et al.

Contributors: Lakshmi N. Chakrapani Pinar Korkmaz Bilge E. S. Akgul et al.

Source: http://www.crest.gatech.edu/palempbitscurrent/a29-chakrapani.pdf.

Subject Terms: Categories and Subject Descriptors, C.3 [Computer Systems Organization, Special-Purpose and Application-Based Systems, C.1.3 [Processor Architectures, Other Architecture Styles General Terms, Performance, Design, Reliability Additional Key Words and Phrases, Embedded systems, probabilistic computing ACM Reference Format

File Description: application/pdf

Relation: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.91.430

Availability: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.91.430
http://www.crest.gatech.edu/palempbitscurrent/a29-chakrapani.pdf

Synchronous byzantine agreement with nearly a cubic number of communication bits

Authors: Kowalski, Dariusz R. Mostefaoui, Achour Department of Computer Science Liverpool et al.

Contributors: Kowalski, Dariusz R. Mostefaoui, Achour Department of Computer Science Liverpool et al.

Source: ACM symposium on Principles of distributed computing (PODC'13) ; https://hal.science/hal-01151136 ; ACM symposium on Principles of distributed computing (PODC'13), Jul 2013, New-York, United States. pp.84-91, ⟨10.1145/2484239.2484271⟩

Subject Terms: Agreement problem, Synchronous distributed system, Byzantine process, Message-passing model, Round-based protocol, EIG, Consensus, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.4: Parallel Architectures/C.1.4.0: Distributed architectures, ACM: C.: Computer Systems Organization/C.2: COMPUTER-COMMUNICATION NETWORKS/C.2.4: Distributed Systems, ACM: D.: Software/D.4: OPERATING SYSTEMS/D.4.7: Organization and Design/D.4.7.1: Distributed systems, ACM: D.: Software/D.4: OPERATING SYSTEMS/D.4.5: Reliability/D.4.5.2: Fault-tolerance, ACM: D.: Software/D.4: OPERATING SYSTEMS/D.4.1: Process Management/D.4.1.0: Concurrency, ACM: D.: Software/D.4: OPERATING SYSTEMS/D.4.1: Process Management/D.4.1.5: Synchronization, [INFO]Computer Science [cs], [INFO.INFO-DC]Computer Science [cs]/Distributed, Parallel, and Cluster Computing [cs.DC], [INFO.INFO-DS]Computer Science [cs]/Data Structures and Algorithms [cs.DS]

Subject Geographic: New-York, United States

Availability: https://hal.science/hal-01151136
https://hal.science/hal-01151136v1/document
https://hal.science/hal-01151136v1/file/podc%20final.pdf
https://doi.org/10.1145/2484239.2484271

Reconstruction of switching thresholds in piecewise-affine models of genetic regulatory networks

Authors: Drulhe, Samuel Ferrari-Trecate, Giancarlo de Jong, Hidde et al.

Contributors: Drulhe, Samuel Ferrari-Trecate, Giancarlo de Jong, Hidde et al.

Source: Hybrid Systems: Computation and Control, HSCC 2006 ; https://inria.hal.science/inria-00001225 ; Hybrid Systems: Computation and Control, HSCC 2006, Mar 2006, Santa Barbara, CA, USA, pp.184 - 199, ⟨10.1007/11730637⟩

Subject Terms: Hybrid system, Genetic regulatory network, system identification, switching thresholds reconstruction, ACM: C.: Computer Systems Organization, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.3: Other Architecture Styles/C.1.3.5: Heterogeneous (hybrid) systems, ACM: I.: Computing Methodologies/I.6: SIMULATION AND MODELING/I.6.1: Simulation Theory/I.6.1.1: Systems theory, [SDV.OT]Life Sciences [q-bio]/Other [q-bio.OT]

Availability: https://inria.hal.science/inria-00001225
https://inria.hal.science/inria-00001225v1/document
https://inria.hal.science/inria-00001225v1/file/LNCS_HSCC06.pdf
https://doi.org/10.1007/11730637

Teaching computer architecture by designing and simulating processors from their bits and bytes.

Authors: Doğan, Mustafa Öztoprak, Kasım Tolun, Mehmet Reşit

Source: PeerJ Computer Science; Feb2024, p1-25, 25p

Subject Terms: COMPUTER architecture, COMPUTER engineering, ARCHES, ARCHITECTURAL design, VERILOG (Computer hardware description language), COMPUTER hardware description languages, MICROPROCESSORS

VirtualSoC: A Research Tool for Modern MPSoCs.

Authors: BORTOLOTTI, DANIELE MARONGIU, ANDREA BENINI, LUCA

Source: ACM Transactions on Embedded Computing Systems; Oct2016, Vol. 16 Issue 1, p1-27, 27p

Subject Terms: COMPUTER system design & construction, HIGH performance computing, EMBEDDED computer systems, COMPUTER simulation, COMPUTER operating systems, CENTRAL processing units

A simultaneous multithreading processor architecture with predictable timing behavior.

Authors: Siqueira, Hadley Magno Kreutz, Marcio Eduardo

Source: Design Automation for Embedded Systems; Mar2020, Vol. 24 Issue 1, p45-62, 18p

Subject Terms: SIMULTANEOUS multithreading processors, COMPUTER systems, CYBER physical systems, DETERMINISTIC algorithms, ARCHITECTURAL design, SYSTEMS engineering

ProWATCh: A Proactive Cross-Layer Workload-Aware Temperature Management Framework for Low-Power Chip Multi-Processors.

Authors: PATNAIK, MILAN R., CHIDHAMBARANATHAN GARG, CHIRAG et al.

Source: ACM Journal on Emerging Technologies in Computing Systems; Sep2015, Vol. 12 Issue 3, p1-25, 25p

Subject Terms: MULTIPROCESSORS, TEMPERATURE, CROSS layer optimization, COMPILERS (Computer programs), COMPUTER operating systems, VOLTAGE control

Towards a New Processor Architecture. ; Vers une nouvelle Architecture de Processeurs

Authors: Vincent, Pierre Landru, Jacques Ecole nationale supérieure Mines-Télécom Lille Douai (IMT Nord Europe) et al.

Contributors: Vincent, Pierre Landru, Jacques Ecole nationale supérieure Mines-Télécom Lille Douai (IMT Nord Europe) et al.

Source: https://hal.science/hal-05117313 ; 2025.

Subject Terms: silicon, parallel, serial, RISC, photonics, computer, optronics, optics, processor, fiber, laser, digital, silicium, parallèle, série, processeur, photonique, ordinateur, optronique, optique, numérique, fibre, ACM: B.: Hardware, ACM: C.: Computer Systems Organization, [INFO]Computer Science [cs], [PHYS]Physics [physics]

Availability: https://hal.science/hal-05117313
https://hal.science/hal-05117313v2/document
https://hal.science/hal-05117313v2/file/frParalSerieRiscV1.pdf

Novel Architecture of Smart FFT Processor

Authors: Teymourzadeh, Rozita University of California San Francisco (UC San Francisco) University of California (UC)

Contributors: Teymourzadeh, Rozita University of California San Francisco (UC San Francisco) University of California (UC)

Source: https://hal.archives-ouvertes.fr/hal-01802071 ; 2014.

Subject Terms: FFT, Digital Design, Processor, VLSI, Novel Architecture, Radix, Harmonic, ACM: D.: Software, ACM: B.: Hardware, ACM: C.: Computer Systems Organization, ACM: I.: Computing Methodologies, ACM: B.: Hardware/B.6: LOGIC DESIGN, ACM: B.: Hardware/B.5: REGISTER-TRANSFER-LEVEL IMPLEMENTATION, ACM: D.: Software/D.3: PROGRAMMING LANGUAGES, [INFO]Computer Science [cs], [INFO.INFO-AO]Computer Science [cs]/Computer Arithmetic, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [INFO.INFO-ES]Computer Science [cs]/Embedded Systems, [INFO.INFO-TS]Computer Science [cs]/Signal and Image Processing, [SPI]Engineering Sciences [physics], [SPI.SIGNAL]Engineering Sciences [physics]/Signal and Image processing, [SPI.TRON]Engineering Sciences [physics]/Electronics

Relation: hal-01802071; https://hal.archives-ouvertes.fr/hal-01802071; https://hal.archives-ouvertes.fr/hal-01802071/document; https://hal.archives-ouvertes.fr/hal-01802071/file/Novel%20Architecture%20of%20Smart%20FFT%20Processor_Draft.pdf

Availability: https://hal.archives-ouvertes.fr/hal-01802071
https://hal.archives-ouvertes.fr/hal-01802071/document
https://hal.archives-ouvertes.fr/hal-01802071/file/Novel%20Architecture%20of%20Smart%20FFT%20Processor_Draft.pdf

The i750 Video Processor: A Total Multimedia Solution.

Authors: Harney, Kevin Keith, Mike Lavelle, Gary et al.

Source: Communications of the ACM; Apr91, Vol. 34 Issue 4, p64-78, 15p

Subject Terms: DIGITAL video, MULTIMEDIA systems, COMPUTER graphics

Exploiting Timing Error Resilience in Processor Architecture.

Authors: SARTORI, JOHN KUMAR, RAKESH

Source: ACM Transactions on Embedded Computing Systems; May2013 Supplement 2, Vol. 12, p1-25, 25p

Subject Terms: COMPLEMENTARY metal oxide semiconductor design & construction, MACRO processors, COMPUTER architecture, ERROR rates, ERRORS, MOORE'S law, INDUSTRIAL costs

A Survey of Machine Learning for Computer Architecture and Systems.

Authors: NAN WU YUAN XIE

Source: ACM Computing Surveys; Apr2023, Vol. 55 Issue 3, p1-39, 39p

Subject Terms: COMPUTER architecture, COMPUTER systems, MACHINE learning, SYSTEMS design, COMPILERS (Computer programs), SERVER farms (Computer network management), ARCHITECTURAL design

An Architectural Comparison of Dataflow Systems.

Authors: Srini

Source: Computer (00189162); 1986, Vol. 19 Issue 3, p68-88, 21p

On-Chip Memory Architecture Exploration Framework for DSP Processor-Based Embedded System on Chip.

Authors: Kumar, T. S. Rajesh Govindarajan, R. Ravikumar, C. P.

Source: ACM Transactions on Embedded Computing Systems; Mar2012, Vol. 11 Issue 1, p1-25, 25p

Subject Terms: SYSTEMS on a chip, COMPUTER storage devices, COMPUTER architecture, DIGITAL signal processing, EMBEDDED computer systems, PERFORMANCE evaluation, PERSONAL computers

Market Mechanisms for Managing Datacenters with Heterogeneous Microarchitectures.

Authors: GUEVARA, MARISABEL LUBIN, BENJAMIN LEE, BENJAMIN C.

Source: ACM Transactions on Computer Systems; Feb2014, Vol. 32 Issue 1, p3:1-3:31, 31p

Subject Terms: DATA libraries, EXPERTISE, RESOURCE allocation, MULTIAGENT systems, CENTRAL processing units, REACTION time

Phase-Change Memory: An Architectural Perspective.

Authors: ZILBERBERG, OMER WEISS, SHLOMO TOLEDO, SIVAN

Source: ACM Computing Surveys; Jun2013, Vol. 45 Issue 3, p29:1-29:33, 33p, 10 Diagrams, 1 Chart, 1 Graph

Subject Terms: COMPUTER architecture, PHASE change memory, DYNAMIC random access memory, ARCHITECTURAL design, DATA protection, COMPUTER systems