Search Results - acm: c.: computer system organization/c.1: processor architectural/c.1.4: parallel architecture*

Towards a New Processor Architecture. ; Vers une nouvelle Architecture de Processeurs

Authors: Vincent, Pierre Landru, Jacques Ecole nationale supérieure Mines-Télécom Lille Douai (IMT Nord Europe) et al.

Contributors: Vincent, Pierre Landru, Jacques Ecole nationale supérieure Mines-Télécom Lille Douai (IMT Nord Europe) et al.

Source: https://hal.science/hal-05117313 ; 2025.

Subject Terms: silicon, parallel, serial, RISC, photonics, computer, optronics, optics, processor, fiber, laser, digital, silicium, parallèle, série, processeur, photonique, ordinateur, optronique, optique, numérique, fibre, ACM: B.: Hardware, ACM: C.: Computer Systems Organization, [INFO]Computer Science [cs], [PHYS]Physics [physics]

Availability: https://hal.science/hal-05117313
https://hal.science/hal-05117313v2/document
https://hal.science/hal-05117313v2/file/frParalSerieRiscV1.pdf

Hardware Architectural Support for Control Systems and Sensor Processing.

Authors: VYAS, SUDHANSHU GUPTE, ADWAIT GILL, CHRISTOPHER D. et al.

Source: ACM Transactions on Embedded Computing Systems; Sep2013, Vol. 13 Issue 2, p1-25, 25p

Subject Terms: COMPUTER input-output equipment, COMPUTER architecture, AUTOMATIC control systems, SENSOR networks, DIGITAL signal processing, ALGORITHMS, PID controllers

Processor Design for Soft Errors: Challenges and State of the Art.

Authors: LI, TUO AMBROSE, JUDE ANGELO RAGEL, ROSHAN et al.

Source: ACM Computing Surveys; Dec2016, Vol. 49 Issue 3, p1-44, 44p, 3 Diagrams, 4 Charts, 1 Graph

Subject Terms: SOFT errors, MICROPROCESSOR design & construction, ERROR rates, COMPUTER architecture, DATA, ERROR detection (Information theory)

A simultaneous multithreading processor architecture with predictable timing behavior.

Authors: Siqueira, Hadley Magno Kreutz, Marcio Eduardo

Source: Design Automation for Embedded Systems; Mar2020, Vol. 24 Issue 1, p45-62, 18p

Subject Terms: SIMULTANEOUS multithreading processors, COMPUTER systems, CYBER physical systems, DETERMINISTIC algorithms, ARCHITECTURAL design, SYSTEMS engineering

Lightweight Chip Multi-Threading (LCMT): Maximizing Fine-Grained Parallelism On-Chip.

Authors: Li, Sheng Kuntz, Shannon Brockman, Jay et al.

Source: IEEE Transactions on Parallel & Distributed Systems; Jul2011, Vol. 22 Issue 7, p1178-1191, 0p

Subject Terms: INTEGRATED circuits, SIMULTANEOUS multithreading processors, PARALLEL algorithms, SIMULATION methods & models, PERFORMANCE evaluation, MULTICORE processors, SYNCHRONIZATION, COMPUTER software, COMPUTER architecture

A Survey on Memory-centric Computer Architectures.

Authors: GEBREGIORGIS, ANTENEH HOANG ANH DU NGUYEN JINTAO YU et al.

Source: ACM Journal on Emerging Technologies in Computing Systems; Oct2022, Vol. 18 Issue 4, p1-50, 50p

Subject Terms: COMPUTER architecture, INTERNET surveys, PARALLEL processing

The Bulk Multicore Architecture for Improved Programmability. (cover story)

Authors: TORRELAS, JOSEP CEZE, LUIS TUCK, JAMES et al.

Source: Communications of the ACM; Dec2009, Vol. 52 Issue 12, p58-65, 8p, 1 Color Photograph, 7 Diagrams

Subject Terms: COMPUTER architecture, MULTIPROCESSORS, MICROPROCESSOR programming, PARALLEL processing, PARALLEL programming, SCALABILITY

On-Chip Memory Architecture Exploration Framework for DSP Processor-Based Embedded System on Chip.

Authors: Kumar, T. S. Rajesh Govindarajan, R. Ravikumar, C. P.

Source: ACM Transactions on Embedded Computing Systems; Mar2012, Vol. 11 Issue 1, p1-25, 25p

Subject Terms: SYSTEMS on a chip, COMPUTER storage devices, COMPUTER architecture, DIGITAL signal processing, EMBEDDED computer systems, PERFORMANCE evaluation, PERSONAL computers

Exploiting Timing Error Resilience in Processor Architecture.

Authors: SARTORI, JOHN KUMAR, RAKESH

Source: ACM Transactions on Embedded Computing Systems; May2013 Supplement 2, Vol. 12, p1-25, 25p

Subject Terms: COMPLEMENTARY metal oxide semiconductor design & construction, MACRO processors, COMPUTER architecture, ERROR rates, ERRORS, MOORE'S law, INDUSTRIAL costs

Reliability aware throughput management of chip multi-processor architecture via thread migration.

Authors: Pouyan, Fatemeh Azarpeyvand, Ali Safari, Saeed et al.

Source: Journal of Supercomputing; Apr2016, Vol. 72 Issue 4, p1363-1380, 18p

Subject Terms: SIMULTANEOUS multithreading processors, COMPUTER architecture, SOFT errors, MINIATURE electronic equipment, PARALLEL processing, MULTIPROCESSORS

Autonomous driving systems hardware and software architecture exploration: optimizing latency and cost under safety constraints.

Authors: Collin, Anne Siddiqi, Afreen Imanishi, Yuto et al.

Source: Systems Engineering; May2020, Vol. 23 Issue 3, p327-337, 11p

Subject Terms: SYSTEMS software, SOFTWARE architecture, COMPUTER vision, ARCHITECTURAL design, COST

A Survey of Machine Learning for Computer Architecture and Systems.

Authors: NAN WU YUAN XIE

Source: ACM Computing Surveys; Apr2023, Vol. 55 Issue 3, p1-39, 39p

Subject Terms: COMPUTER architecture, COMPUTER systems, MACHINE learning, SYSTEMS design, COMPILERS (Computer programs), SERVER farms (Computer network management), ARCHITECTURAL design

PARALLEL ALGORITHMS FOR THE EXECUTION OF RELATIONAL DATABASE OPERATIONS REVISITED ON GRIDS.

Authors: Mach, Werner Schikuta, Erich

Source: International Journal of High Performance Computing Applications; May2009, Vol. 23 Issue 2, p152-170, 19p, 4 Diagrams, 4 Charts, 19 Graphs

Subject Terms: PARALLEL algorithms, GRID computing, RELATIONAL databases, DATA transmission systems, GRIDS (Cartography), COMPUTER architecture, GEOGRAPHICAL positions, DATABASE selection, DATABASES

A universal parallel computer architecture.

Authors: Dally, William

Source: New Generation Computing; Sep1993, Vol. 11 Issue 3/4, p227-249, 23p

VirtualSoC: A Research Tool for Modern MPSoCs.

Authors: BORTOLOTTI, DANIELE MARONGIU, ANDREA BENINI, LUCA

Source: ACM Transactions on Embedded Computing Systems; Oct2016, Vol. 16 Issue 1, p1-27, 27p

Subject Terms: COMPUTER system design & construction, HIGH performance computing, EMBEDDED computer systems, COMPUTER simulation, COMPUTER operating systems, CENTRAL processing units

An Efficient Data-Distribution Mechanism in a Processor-In-Memory (PIM) Architecture Applied to Motion Estimation.

Authors: Jung-Yup Kang Gupta, Sandeep Gaudiot, Jean-Luc

Source: IEEE Transactions on Computers; Mar2008, Vol. 57 Issue 3, p375-388, 14p, 1 Black and White Photograph, 1 Diagram, 1 Chart

Subject Terms: BANDWIDTHS, COMPUTER storage devices, MACRO processors, DATA transmission systems, MPEG (Video coding standard), DIGITAL video standards, INTEGRATED circuits, ALGORITHMS, DIGITAL communications, SPECTRUM allocation

Top Picks in Computer Architecture from Conferences in 2018.

Authors: Dwarkadas, Sandhya

Source: IEEE Micro; May-Jun2019, Vol. 39 Issue 3, p6-10, 5p

Subject Terms: COMPUTER architecture, ORDER picking systems, MESSAGE authentication codes, PARALLEL computers, RANDOM access memory

Prediction Modeling for Application-Specific Communication Architecture Design of Optical NoC.

Authors: TRAJKOVIC, JELENA KARIMI, SARA HANGSAN, SAMANTHA et al.

Source: ACM Transactions on Embedded Computing Systems; Aug2022, Vol. 21 Issue 4, p1-29, 29p

Subject Terms: ARCHITECTURAL design, PREDICTION models, OPTICAL communications, COMMUNICATION models, ENERGY consumption

Prefabrication and Postfabrication Architecture Exploration for Partially Reconfigurable VLIW Processors.

Authors: Chattopadhyay, A. Ishebabi, H. Chen, X. et al.

Source: ACM Transactions on Embedded Computing Systems; Jul2008, Vol. 7 Issue 4, p40-40:31, 31p, 8 Diagrams, 13 Charts, 1 Graph

Subject Terms: APPLICATION-specific instruction-set processors, MICROPROCESSORS, ADAPTIVE computing systems, COMPUTER architecture, DATA pipelining

Pre- and Postfabrication Architecture Exploration for Partially Reconfigurable VLIW Processors.

Authors: CHATTOPADHYAY, A. ISHEBABI, H. CHEN, X. et al.

Source: ACM Transactions on Embedded Computing Systems; Jan2009, Vol. 8 Issue 2, p12-1-12-30, 30p, 13 Diagrams, 9 Charts, 1 Graph

Subject Terms: COMPUTER architecture, CENTRAL processing units, MICROPROCESSORS, DATA pipelining, COMPUTER input-output equipment