Search Results - acm: c.: computer system organization/c.1: ((procesov OR process) OR processes) architecture*

1

Synchronous byzantine agreement with nearly a cubic number of communication bits

Authors: Kowalski, Dariusz R. Mostefaoui, Achour Department of Computer Science Liverpool et al.

Contributors: Kowalski, Dariusz R. Mostefaoui, Achour Department of Computer Science Liverpool et al.

Source: ACM symposium on Principles of distributed computing (PODC'13) ; https://hal.science/hal-01151136 ; ACM symposium on Principles of distributed computing (PODC'13), Jul 2013, New-York, United States. pp.84-91, ⟨10.1145/2484239.2484271⟩

Subject Terms: Agreement problem, Synchronous distributed system, Byzantine process, Message-passing model, Round-based protocol, EIG, Consensus, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.4: Parallel Architectures/C.1.4.0: Distributed architectures, ACM: C.: Computer Systems Organization/C.2: COMPUTER-COMMUNICATION NETWORKS/C.2.4: Distributed Systems, ACM: D.: Software/D.4: OPERATING SYSTEMS/D.4.7: Organization and Design/D.4.7.1: Distributed systems, ACM: D.: Software/D.4: OPERATING SYSTEMS/D.4.5: Reliability/D.4.5.2: Fault-tolerance, ACM: D.: Software/D.4: OPERATING SYSTEMS/D.4.1: Process Management/D.4.1.0: Concurrency, ACM: D.: Software/D.4: OPERATING SYSTEMS/D.4.1: Process Management/D.4.1.5: Synchronization, [INFO]Computer Science [cs], [INFO.INFO-DC]Computer Science [cs]/Distributed, Parallel, and Cluster Computing [cs.DC], [INFO.INFO-DS]Computer Science [cs]/Data Structures and Algorithms [cs.DS]

Subject Geographic: New-York, United States

Availability: https://hal.science/hal-01151136
https://hal.science/hal-01151136v1/document
https://hal.science/hal-01151136v1/file/podc%20final.pdf
https://doi.org/10.1145/2484239.2484271

2

Synchronisation for Distributed Audio Rendering over Heterogeneous Devices, in HTML5

Authors: Lambert, Jean-Philippe Robaszkiewicz, Sébastien Schnell, Norbert et al.

Contributors: Lambert, Jean-Philippe Robaszkiewicz, Sébastien Schnell, Norbert et al.

Source: 2nd Web Audio Conference
https://hal.science/hal-01304889
2nd Web Audio Conference, Apr 2016, Atlanta, GA, United States
http://webaudio.gatech.edu/

Subject Terms: Synchronisation, HTML5, Web Audio API, Audio, Distributed, ACM: H.: Information Systems/H.5: INFORMATION INTERFACES AND PRESENTATION (e.g., HCI)/H.5.5: Sound and Music Computing, ACM: D.: Software/D.4: OPERATING SYSTEMS/D.4.1: Process Management/D.4.1.5: Synchronization, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.4: Parallel Architectures/C.1.4.0: Distributed architectures, ACM: D.: Software/D.4: OPERATING SYSTEMS/D.4.7: Organization and Design/D.4.7.4: Real-time systems and embedded systems, [INFO.INFO-WB]Computer Science [cs]/Web, [INFO.INFO-SD]Computer Science [cs]/Sound [cs.SD], [INFO.INFO-DC]Computer Science [cs]/Distributed, Parallel, and Cluster Computing [cs.DC]

Subject Geographic: Atlanta, GA, United States

Availability: https://hal.science/hal-01304889
https://hal.science/hal-01304889v1/document
https://hal.science/hal-01304889v1/file/wac16-lambert.pdf

3

Ghost Process: a Sound Basis to Implement Process Duplication, Migration and Checkpoint/Restart in Linux Clusters

Authors: Vallée, Geoffroy Lottiaux, Renaud Margery, David et al.

Contributors: Vallée, Geoffroy Lottiaux, Renaud Margery, David et al.

Source: https://inria.hal.science/inria-00000471 ; [Research Report] PI 1755, 2005, pp.16.

Subject Terms: Linux cluster, distributed system, operating system, single system image, process virtualization \\ Grappe de calculateurs Linux, système distribué, système à image unique, système d`exploitation, virtualisation de processus, ACM: D.: Software/D.4: OPERATING SYSTEMS, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES, [INFO.INFO-OS]Computer Science [cs]/Operating Systems [cs.OS]

Relation: Report N°: PI 1755

Availability: https://inria.hal.science/inria-00000471
https://inria.hal.science/inria-00000471/document
https://inria.hal.science/inria-00000471/file/PI-1755.pdf

4

TBES: Template-Based Exploration and Synthesis of Heterogeneous Multiprocessor Architectures on FPGA

Authors: Corre, Youenn Diguet, Jean-Philippe Heller, Dominique et al.

Contributors: Corre, Youenn Diguet, Jean-Philippe Heller, Dominique et al.

Source: ACM Transactions on Embedded Computing Systems. 15:1-27

Subject Terms: [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES, 13. Climate action, Electronic System Level, 0202 electrical engineering, electronic engineering, information engineering, ACM: B.: Hardware/B.5: REGISTER-TRANSFER-LEVEL IMPLEMENTATION, Multiprocessor, 02 engineering and technology, High-Level Synthesis, ACM: D.: Software/D.2: SOFTWARE ENGINEERING/D.2.2: Design Tools and Techniques, System-on-Chip

Access URL: https://hal.archives-ouvertes.fr/hal-01172103/document
https://dblp.uni-trier.de/db/journals/tecs/tecs15.html#CorreDHBL16
https://hal.archives-ouvertes.fr/hal-01172103
https://dl.acm.org/doi/10.1145/2816817
https://doi.org/10.1145/2816817

5

The Multiplicative Power of Consensus Numbers

Authors: Imbs, Damien Raynal, Michel As Scalable As Possible: foundations of large scale dynamic distributed systems (ASAP) et al.

Contributors: Imbs, Damien Raynal, Michel As Scalable As Possible: foundations of large scale dynamic distributed systems (ASAP) et al.

Source: https://inria.hal.science/inria-00454399 ; [Research Report] PI 1949, 2010, pp.17.

Subject Terms: Asynchronous processes, BG simulation, Consensus number, Distributed computability, Fault-Tolerance, Process crash failure, Reduction algorithm, t-Resilience, k-Set agreement, Shared memory system, Synchronization power, System model, Waitfreedom, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES, [INFO.INFO-OS]Computer Science [cs]/Operating Systems [cs.OS]

Relation: Report N°: PI 1949

Availability: https://inria.hal.science/inria-00454399
https://inria.hal.science/inria-00454399v2/document
https://inria.hal.science/inria-00454399v2/file/PI-1949.pdf

6

Adapting Application Mapping to Systematic Within-Die Process Variations on Chip Multiprocessors

Authors: Ding, Yang Kandemir, Mahmut Irwin, Mary Jane et al.

Contributors: Ding, Yang Kandemir, Mahmut Irwin, Mary Jane et al.

Source: HiPEAC 2009 - High Performance and Embedded Architectures and Compilers ; https://hal.inria.fr/inria-00446018 ; HiPEAC 2009 - High Performance and Embedded Architectures and Compilers, Jan 2009, Paphos, Cyprus. ⟨10.1007/978-3-540-92990-1_18⟩

Subject Terms: ACM: B.: Hardware/B.2: ARITHMETIC AND LOGIC STRUCTURES, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES, ACM: D.: Software/D.3: PROGRAMMING LANGUAGES/D.3.4: Processors, [INFO.INFO-OH]Computer Science [cs]/Other [cs.OH], [INFO.INFO-ES]Computer Science [cs]/Embedded Systems

Subject Geographic: Paphos, Cyprus

Relation: inria-00446018; https://hal.inria.fr/inria-00446018

Availability: https://hal.inria.fr/inria-00446018
https://doi.org/10.1007/978-3-540-92990-1_18

7

Illuminating the Dark or how to recover what should not be seen in FE-based classifiers

Authors: Carpov, Sergiu Fontaine, Caroline Ligier, Damien et al.

Contributors: Carpov, Sergiu Fontaine, Caroline Ligier, Damien et al.

Source: ISSN: 2299-0984 ; Proceedings on Privacy Enhancing Technologies ; https://hal.science/hal-02413588 ; Proceedings on Privacy Enhancing Technologies, 2020, 2020 (2), pp.5-23. ⟨10.2478/popets-2020-0015⟩ ; https://doi.org/10.2478/popets-2020-0015.

Subject Terms: Functional encryption, information leakage, privacy-preserving classification, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.3: Other Architecture Styles/C.1.3.7: Neural nets, ACM: D.: Software/D.4: OPERATING SYSTEMS/D.4.6: Security and Protection/D.4.6.2: Cryptographic controls, ACM: I.: Computing Methodologies/I.2: ARTIFICIAL INTELLIGENCE/I.2.6: Learning/I.2.6.6: Parameter learning, [INFO.INFO-CR]Computer Science [cs]/Cryptography and Security [cs.CR], [INFO.INFO-AI]Computer Science [cs]/Artificial Intelligence [cs.AI], [INFO.INFO-NE]Computer Science [cs]/Neural and Evolutionary Computing [cs.NE]

Availability: https://hal.science/hal-02413588
https://hal.science/hal-02413588v1/document
https://hal.science/hal-02413588v1/file/%5B22990984%20-%20Proceedings%20on%20Privacy%20Enhancing%20Technologies%5D%20Illuminating%20the%20Dark%20or%20how%20to%20recover%20what%20should%20not%20be%20seen%20in%20FE-based%20classifiers.pdf
https://doi.org/10.2478/popets-2020-0015

8

Hardware-Accelerated Dynamic Binary Translation

Authors: Rokicki, Simon Rohou, Erven Derrien, Steven et al.

Contributors: Rokicki, Simon Rohou, Erven Derrien, Steven et al.

Source: IEEE/ACM Design, Automation & Test in Europe Conference & Exhibition (DATE) ; https://inria.hal.science/hal-01423639 ; IEEE/ACM Design, Automation & Test in Europe Conference & Exhibition (DATE), Mar 2017, Lausanne, Switzerland ; https://www.date-conference.com/

Subject Terms: ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.3: Other Architecture Styles/C.1.3.5: Heterogeneous (hybrid) systems, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.3: Other Architecture Styles/C.1.3.0: Adaptable architectures, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.2: Multiple Data Stream Architectures (Multiprocessors)/C.1.2.4: Multiple-instruction-stream, multiple-data-stream processors (MIMD), ACM: D.: Software/D.3: PROGRAMMING LANGUAGES/D.3.4: Processors/D.3.4.0: Code generation, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [INFO.INFO-ES]Computer Science [cs]/Embedded Systems

Subject Geographic: Lausanne, Switzerland

Availability: https://inria.hal.science/hal-01423639
https://inria.hal.science/hal-01423639v1/document
https://inria.hal.science/hal-01423639v1/file/rokicki_DATE_cr.pdf

9

HARS: A Hardware-Assisted Runtime Software for embedded many-core architectures

Authors: Lhuillier, Y. Ojail, M. Guerre, A. et al.

Contributors: Lhuillier, Y. Ojail, M. Guerre, A. et al.

Source: ISSN: 1539-9087.

Subject Terms: B.5.0 [Register-Transfer-Level Implementation]: General, ACM: D.: Software/D.4: OPERATING SYSTEMS/D.4.7: Organization and Design/D.4.7.4: Real-time systems and embedded systems, ACM: D.: Software/D.4: OPERATING SYSTEMS/D.4.1: Process Management, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.4: Parallel Architectures, ACM: B.: Hardware/B.5: REGISTER-TRANSFER-LEVEL IMPLEMENTATION, [INFO]Computer Science [cs]

Availability: https://cea.hal.science/cea-01818892
https://doi.org/10.1145/2517311

10

Dynamic sharing of a multiple access channel

Authors: Bienkowski, Marcin Klonowski, Marek Korzeniowski, Miroslaw et al.

Contributors: Bienkowski, Marcin Klonowski, Marek Korzeniowski, Miroslaw et al.

Source: 27th International Symposium on Theoretical Aspects of Computer Science - STACS 2010
https://inria.hal.science/inria-00457096
27th International Symposium on Theoretical Aspects of Computer Science - STACS 2010, Inria Nancy Grand Est & Loria, Mar 2010, Nancy, France. pp.83-94

Subject Terms: distributed algorithms, multiple access channel, mutual exclusion, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.4: Parallel Architectures, ACM: C.: Computer Systems Organization/C.2: COMPUTER-COMMUNICATION NETWORKS/C.2.1: Network Architecture and Design, ACM: F.: Theory of Computation/F.2: ANALYSIS OF ALGORITHMS AND PROBLEM COMPLEXITY/F.2.2: Nonnumerical Algorithms and Problems, [INFO.INFO-DS]Computer Science [cs]/Data Structures and Algorithms [cs.DS]

Subject Geographic: Nancy, France

Relation: inria-00457096; https://inria.hal.science/inria-00457096; https://inria.hal.science/inria-00457096/document; https://inria.hal.science/inria-00457096/file/bienkowski.pdf

Availability: https://inria.hal.science/inria-00457096
https://inria.hal.science/inria-00457096/document
https://inria.hal.science/inria-00457096/file/bienkowski.pdf

11

NoC-Based Protection for SoC Time-Driven Attacks

Authors: Sepulveda, Martha Johanna Diguet, Jean-Philippe Strum, Marius et al.

Contributors: Sepulveda, Martha Johanna Diguet, Jean-Philippe Strum, Marius et al.

Source: IEEE Embedded Systems Letters. 7:7-10

Subject Terms: ACM: B.: Hardware/B.7: INTEGRATED CIRCUITS, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], Channel leakage, multiport memory, common bus, ACM: B.: Hardware/B.7: INTEGRATED CIRCUITS/B.7.1: Types and Design Styles/B.7.1.7: VLSI (very large scale integration), 02 engineering and technology, 3. Good health, Network On Chip, crossbar switch), Security, 0202 electrical engineering, electronic engineering, information engineering, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.2: Multiple Data Stream Architectures (Multiprocessors)/C.1.2.3: Interconnection architectures (e.g, [SPI.SIGNAL]Engineering Sciences [physics]/Signal and Image processing, [SPI.SIGNAL] Engineering Sciences [physics]/Signal and Image processing

Access URL: https://hal.archives-ouvertes.fr/hal-01083270
http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6994256
https://hal.inria.fr/hal-01253500
http://ieeexplore.ieee.org/document/6994256
https://ieeexplore.ieee.org/document/6994256
https://dblp.uni-trier.de/db/journals/esl/esl7.html#SepulvedaDSG15

12

Optimizing DDR-SDRAM Communications at C-level for Automatically-Generated Hardware Accelerators. An Experience with the Altera C2H HLS Tool.

Authors: Alias, Christophe Darte, Alain Plesco, Alexandru et al.

Contributors: Alias, Christophe Darte, Alain Plesco, Alexandru et al.

Source: https://inria.hal.science/inria-00482035 ; [Research Report] RR-7281, INRIA. 2010, pp.19.

Subject Terms: High-level synthesis, hardware accelerators, DDR-SDRAM, optimized communications, program transformation, reconfigurable architectures, FPGA, ACM: B.: Hardware/B.4: INPUT/OUTPUT AND DATA COMMUNICATIONS/B.4.1: Data Communications Devices/B.4.1.0: Processors, ACM: B.: Hardware/B.4: INPUT/OUTPUT AND DATA COMMUNICATIONS/B.4.2: Input/Output Devices/B.4.2.0: Channels and controllers, ACM: B.: Hardware/B.7: INTEGRATED CIRCUITS/B.7.1: Types and Design Styles/B.7.1.1: Algorithms implemented in hardware, ACM: B.: Hardware/B.7: INTEGRATED CIRCUITS/B.7.1: Types and Design Styles/B.7.1.3: Input/output circuits, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.3: Other Architecture Styles/C.1.3.0: Adaptable architectures, [INFO.INFO-ES]Computer Science [cs]/Embedded Systems, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [INFO.INFO-PL]Computer Science [cs]/Programming Languages [cs.PL]

Availability: https://inria.hal.science/inria-00482035
https://inria.hal.science/inria-00482035v1/document
https://inria.hal.science/inria-00482035v1/file/RR-7281.pdf

13

Towards Verified Faithful Simulation

Authors: Joloboff, Vania Monin, Jean-François Shi, Xiaomu et al.

Contributors: Joloboff, Vania Monin, Jean-François Shi, Xiaomu et al.

Source: Lecture Notes in Computer Science ISBN: 9783319259413

Access URL: https://inria.hal.science/hal-01241837v1
https://doi.org/10.1007/978-3-319-25942-0
https://inria.hal.science/hal-01242963v1

14

A Case for a Complexity-Effective, Width-partitioned Microarchitecture

Authors: Rochecouste, Olivier Pokam, Gilles Seznec, André et al.

Contributors: Rochecouste, Olivier Pokam, Gilles Seznec, André et al.

Source: https://inria.hal.science/inria-00000211 ; [Research Report] PI 1742, 2005, pp.27.

Subject Terms: Hardaware complexity, power consumption, superscalar processor, width-partitioned microarchitecture, register file, narrow-width operations, data-width predictor \\ Complexité matérielle, consommation électrique, processeur superscalaire, microarchitecture clusterisée, fichier de registres, opérations tronquées, prédicteur de largeur, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES, ACM: C.: Computer Systems Organization/C.3: SPECIAL-PURPOSE AND APPLICATION-BASED SYSTEMS, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

Relation: Report N°: PI 1742

Availability: https://inria.hal.science/inria-00000211
https://inria.hal.science/inria-00000211/document
https://inria.hal.science/inria-00000211/file/PI-1742.pdf

15

Scheduling issues on thermally-constrained processors

Authors: Michaud, Pierre Sazeides, Yiannakis Compilation, parallel architectures and system (CAPS) et al.

Contributors: Michaud, Pierre Sazeides, Yiannakis Compilation, parallel architectures and system (CAPS) et al.

Source: https://inria.hal.science/inria-00110507 ; [Research Report] PI 1822, 2006, pp.19.

Subject Terms: Multi-core processor, temperature, thread scheduling, time slice, activity migration, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

Relation: Report N°: PI 1822

Availability: https://inria.hal.science/inria-00110507
https://inria.hal.science/inria-00110507/document
https://inria.hal.science/inria-00110507/file/PI-1822.pdf

16

Accomodating Diversity in CMPs with Heterogeneous Frequencies

Authors: Bhadauria, Major Weaver, Vince Mckee, Sally A. et al.

Contributors: Bhadauria, Major Weaver, Vince Mckee, Sally A. et al.

Source: HiPEAC 2009 - High Performance and Embedded Architectures and Compilers ; https://hal.inria.fr/inria-00446283 ; HiPEAC 2009 - High Performance and Embedded Architectures and Compilers, Jan 2009, Paphos, Cyprus. ⟨10.1007/978-3-540-92990-1_19⟩

Subject Terms: ACM: B.: Hardware/B.2: ARITHMETIC AND LOGIC STRUCTURES, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES, ACM: D.: Software/D.3: PROGRAMMING LANGUAGES/D.3.4: Processors, [INFO.INFO-OH]Computer Science [cs]/Other [cs.OH], [INFO.INFO-ES]Computer Science [cs]/Embedded Systems

Subject Geographic: Paphos, Cyprus

Relation: inria-00446283; https://hal.inria.fr/inria-00446283

Availability: https://hal.inria.fr/inria-00446283
https://doi.org/10.1007/978-3-540-92990-1_19

Search Results - acm: c.: computer system organization/c.1: ((procesov OR process) OR processes) architecture*

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