Výsledky vyhledávání - acm: c.: computer system organizacion/c.1: processor architecture*

Distributed Architecture for Resource Management in Large Scale Grids

Autoři: Jeanvoine, Emmanuel Rilling, Louis Morin, Christine a další

Přispěvatelé: Jeanvoine, Emmanuel Rilling, Louis Morin, Christine a další

Zdroj: https://inria.hal.science/inria-00001066 ; [Research Report] PI 1775, 2006, pp.13.

Témata: Grid computing, distributed system, peer-to-peer overlay networks, resource allocation, self-healing \\ Grille de calcul, système distribué, réseaux logiques pair-à-pair, allocation de ressources, auto-réparation, ACM: C.: Computer Systems Organization/C.2: COMPUTER-COMMUNICATION NETWORKS/C.2.4: Distributed Systems, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.4: Parallel Architectures, [INFO.INFO-OH]Computer Science [cs]/Other [cs.OH]

Relation: Report N°: PI 1775

Dostupnost: https://inria.hal.science/inria-00001066
https://inria.hal.science/inria-00001066v1/document
https://inria.hal.science/inria-00001066v1/file/PI-1775.pdf

Real-time scheduling on heterogeneous system-on-chip architectures using an optimised artificial neural network

Autoři: Chillet, Daniel Eiche, Antoine Pillement, Sébastien a další

Přispěvatelé: Chillet, Daniel Eiche, Antoine Pillement, Sébastien a další

Zdroj: ISSN: 1383-7621 ; Journal of Systems Architecture ; https://inria.hal.science/hal-00650650 ; Journal of Systems Architecture, 2011, 57, pp.340-353. ⟨10.1016/j.sysarc.2011.01.004⟩.

Témata: Artificial neural network, Heterogeneous multi-processor architecture, Hopfield model, Inhibitor neurons, Task scheduling, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.3: Other Architecture Styles/C.1.3.7: Neural nets

Dostupnost: https://inria.hal.science/hal-00650650
https://doi.org/10.1016/j.sysarc.2011.01.004

Novel Architecture of Smart FFT Processor

Autoři: Teymourzadeh, Rozita University of California San Francisco (UC San Francisco) University of California (UC)

Přispěvatelé: Teymourzadeh, Rozita University of California San Francisco (UC San Francisco) University of California (UC)

Zdroj: https://hal.archives-ouvertes.fr/hal-01802071 ; 2014.

Témata: FFT, Digital Design, Processor, VLSI, Novel Architecture, Radix, Harmonic, ACM: D.: Software, ACM: B.: Hardware, ACM: C.: Computer Systems Organization, ACM: I.: Computing Methodologies, ACM: B.: Hardware/B.6: LOGIC DESIGN, ACM: B.: Hardware/B.5: REGISTER-TRANSFER-LEVEL IMPLEMENTATION, ACM: D.: Software/D.3: PROGRAMMING LANGUAGES, [INFO]Computer Science [cs], [INFO.INFO-AO]Computer Science [cs]/Computer Arithmetic, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [INFO.INFO-ES]Computer Science [cs]/Embedded Systems, [INFO.INFO-TS]Computer Science [cs]/Signal and Image Processing, [SPI]Engineering Sciences [physics], [SPI.SIGNAL]Engineering Sciences [physics]/Signal and Image processing, [SPI.TRON]Engineering Sciences [physics]/Electronics

Relation: hal-01802071; https://hal.archives-ouvertes.fr/hal-01802071; https://hal.archives-ouvertes.fr/hal-01802071/document; https://hal.archives-ouvertes.fr/hal-01802071/file/Novel%20Architecture%20of%20Smart%20FFT%20Processor_Draft.pdf

Dostupnost: https://hal.archives-ouvertes.fr/hal-01802071
https://hal.archives-ouvertes.fr/hal-01802071/document
https://hal.archives-ouvertes.fr/hal-01802071/file/Novel%20Architecture%20of%20Smart%20FFT%20Processor_Draft.pdf

Comparison of the Discriminatory Processor Sharing Policies

Autoři: Osipova, Natalia Models for the performance analysis and the control of networks (MAESTRO) Centre Inria d'Université Côte d'Azur a další

Přispěvatelé: Osipova, Natalia Models for the performance analysis and the control of networks (MAESTRO) Centre Inria d'Université Côte d'Azur a další

Zdroj: https://inria.hal.science/inria-00264111 ; [Research Report] RR-6475, INRIA. 2008, pp.19.

Témata: ACM: C.: Computer Systems Organization/C.2: COMPUTER-COMMUNICATION NETWORKS/C.2.2: Network Protocols, ACM: G.: Mathematics of Computing/G.3: PROBABILITY AND STATISTICS/G.3.8: Queueing theory, [INFO.INFO-MO]Computer Science [cs]/Modeling and Simulation, [INFO.INFO-NI]Computer Science [cs]/Networking and Internet Architecture [cs.NI]

Relation: info:eu-repo/semantics/altIdentifier/arxiv/0803.2129; ARXIV: 0803.2129

Dostupnost: https://inria.hal.science/inria-00264111
https://inria.hal.science/inria-00264111v4/document
https://inria.hal.science/inria-00264111v4/file/rr_6475_dps.pdf

TBES: Template-Based Exploration and Synthesis of Heterogeneous Multiprocessor Architectures on FPGA

Autoři: Corre, Youenn Diguet, Jean-Philippe Heller, Dominique a další

Přispěvatelé: Corre, Youenn Diguet, Jean-Philippe Heller, Dominique a další

Zdroj: ISSN: 1539-9087.

Témata: System-on-Chip, Multiprocessor, High-Level Synthesis, Electronic System Level, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES, ACM: B.: Hardware/B.5: REGISTER-TRANSFER-LEVEL IMPLEMENTATION, ACM: D.: Software/D.2: SOFTWARE ENGINEERING/D.2.2: Design Tools and Techniques, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

Dostupnost: https://hal.science/hal-01172103
https://hal.science/hal-01172103v1/document
https://hal.science/hal-01172103v1/file/Preprint_TECS_YC%20%283%29.pdf

Reconstruction of switching thresholds in piecewise-affine models of genetic regulatory networks

Autoři: Drulhe, Samuel Ferrari-Trecate, Giancarlo de Jong, Hidde a další

Přispěvatelé: Drulhe, Samuel Ferrari-Trecate, Giancarlo de Jong, Hidde a další

Zdroj: Hybrid Systems: Computation and Control, HSCC 2006 ; https://inria.hal.science/inria-00001225 ; Hybrid Systems: Computation and Control, HSCC 2006, Mar 2006, Santa Barbara, CA, USA, pp.184 - 199, ⟨10.1007/11730637⟩

Témata: Hybrid system, Genetic regulatory network, system identification, switching thresholds reconstruction, ACM: C.: Computer Systems Organization, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.3: Other Architecture Styles/C.1.3.5: Heterogeneous (hybrid) systems, ACM: I.: Computing Methodologies/I.6: SIMULATION AND MODELING/I.6.1: Simulation Theory/I.6.1.1: Systems theory, [SDV.OT]Life Sciences [q-bio]/Other [q-bio.OT]

Dostupnost: https://inria.hal.science/inria-00001225
https://inria.hal.science/inria-00001225v1/document
https://inria.hal.science/inria-00001225v1/file/LNCS_HSCC06.pdf
https://doi.org/10.1007/11730637

A Framework for Task Scheduling and Memory Partitioning for Multi-Processor System-on-Chip

Autoři: Salamy, Hassan Ramanujam, J. Department of Electrical and Computer Engineering - Louisiana State University (ECE) a další

Přispěvatelé: Salamy, Hassan Ramanujam, J. Department of Electrical and Computer Engineering - Louisiana State University (ECE) a další

Zdroj: HiPEAC 2009 - High Performance and Embedded Architectures and Compilers ; https://hal.inria.fr/inria-00446288 ; HiPEAC 2009 - High Performance and Embedded Architectures and Compilers, Jan 2009, Paphos, Cyprus. ⟨10.1007/978-3-540-92990-1_20⟩

Témata: ACM: B.: Hardware/B.2: ARITHMETIC AND LOGIC STRUCTURES, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES, ACM: D.: Software/D.3: PROGRAMMING LANGUAGES/D.3.4: Processors, [INFO.INFO-OH]Computer Science [cs]/Other [cs.OH], [INFO.INFO-ES]Computer Science [cs]/Embedded Systems

Geografické téma: Paphos, Cyprus

Relation: inria-00446288; https://hal.inria.fr/inria-00446288

Dostupnost: https://hal.inria.fr/inria-00446288
https://doi.org/10.1007/978-3-540-92990-1_20

Towards a New Processor Architecture. ; Vers une nouvelle Architecture de Processeurs

Autoři: Vincent, Pierre Landru, Jacques Ecole nationale supérieure Mines-Télécom Lille Douai (IMT Nord Europe) a další

Přispěvatelé: Vincent, Pierre Landru, Jacques Ecole nationale supérieure Mines-Télécom Lille Douai (IMT Nord Europe) a další

Zdroj: https://hal.science/hal-05117313 ; 2025.

Témata: silicon, parallel, serial, RISC, photonics, computer, optronics, optics, processor, fiber, laser, digital, silicium, parallèle, série, processeur, photonique, ordinateur, optronique, optique, numérique, fibre, ACM: B.: Hardware, ACM: C.: Computer Systems Organization, [INFO]Computer Science [cs], [PHYS]Physics [physics]

Dostupnost: https://hal.science/hal-05117313
https://hal.science/hal-05117313v2/document
https://hal.science/hal-05117313v2/file/frParalSerieRiscV1.pdf

Architecture des ordinateurs

Autoři: Lagadec, Loïc Pillement, Sébastien Tisserand, Arnaud a další

Přispěvatelé: Lagadec, Loïc Pillement, Sébastien Tisserand, Arnaud a další

Zdroj: https://inria.hal.science/hal-00819668 ; Loïc Lagadec and Sébastien Pillement and Arnaud Tisserand. Hermes, 32, pp.150, 2013, Technique et science informatique, 9782746245679.

Témata: ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

Dostupnost: https://inria.hal.science/hal-00819668

A Case for a Complexity-Effective, Width-partitioned Microarchitecture

Autoři: Rochecouste, Olivier Pokam, Gilles Seznec, André a další

Přispěvatelé: Rochecouste, Olivier Pokam, Gilles Seznec, André a další

Zdroj: https://inria.hal.science/inria-00000211 ; [Research Report] PI 1742, 2005, pp.27.

Témata: Hardaware complexity, power consumption, superscalar processor, width-partitioned microarchitecture, register file, narrow-width operations, data-width predictor \\ Complexité matérielle, consommation électrique, processeur superscalaire, microarchitecture clusterisée, fichier de registres, opérations tronquées, prédicteur de largeur, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES, ACM: C.: Computer Systems Organization/C.3: SPECIAL-PURPOSE AND APPLICATION-BASED SYSTEMS, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

Relation: Report N°: PI 1742

Dostupnost: https://inria.hal.science/inria-00000211
https://inria.hal.science/inria-00000211/document
https://inria.hal.science/inria-00000211/file/PI-1742.pdf

Scheduling issues on thermally-constrained processors

Autoři: Michaud, Pierre Sazeides, Yiannakis Compilation, parallel architectures and system (CAPS) a další

Přispěvatelé: Michaud, Pierre Sazeides, Yiannakis Compilation, parallel architectures and system (CAPS) a další

Zdroj: https://inria.hal.science/inria-00110507 ; [Research Report] PI 1822, 2006, pp.19.

Témata: Multi-core processor, temperature, thread scheduling, time slice, activity migration, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

Relation: Report N°: PI 1822

Dostupnost: https://inria.hal.science/inria-00110507
https://inria.hal.science/inria-00110507/document
https://inria.hal.science/inria-00110507/file/PI-1822.pdf

Batch Processor Sharing with Hyper-Exponential Service Time

Autoři: Osipova, Natalia Models for the performance analysis and the control of networks (MAESTRO) Centre Inria d'Université Côte d'Azur a další

Přispěvatelé: Osipova, Natalia Models for the performance analysis and the control of networks (MAESTRO) Centre Inria d'Université Côte d'Azur a další

Zdroj: https://inria.hal.science/inria-00144389 ; [Research Report] RR-6180, INRIA. 2007, pp.21.

Témata: Cauchy matrices, Batch Processor Sharing, Two Level Processor sharing, Hyper-Exponential distribution, Laplace transform, Communication Systems, ACM: C.: Computer Systems Organization/C.2: COMPUTER-COMMUNICATION NETWORKS/C.2.2: Network Protocols, [INFO.INFO-NI]Computer Science [cs]/Networking and Internet Architecture [cs.NI], [INFO.INFO-WB]Computer Science [cs]/Web

Relation: info:eu-repo/semantics/altIdentifier/arxiv/0705.0425; ARXIV: 0705.0425

Dostupnost: https://inria.hal.science/inria-00144389
https://inria.hal.science/inria-00144389v4/document
https://inria.hal.science/inria-00144389v4/file/rr-6180.pdf

Power Estimation of a C algorithm on a VLIW Processor

Autoři: Julien, Nathalie Senn, Eric Laurent, Johann a další

Přispěvatelé: Julien, Nathalie Senn, Eric Laurent, Johann a další

Zdroj: WCED ; https://hal.science/hal-00077336 ; 2002, pp 100

Témata: FLPA, DSP VLIW, Power consumption, Energy, Estimation, IEEE, ACM, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

Dostupnost: https://hal.science/hal-00077336
https://hal.science/hal-00077336v1/document
https://hal.science/hal-00077336v1/file/WCED_02.pdf

CASH Design Space Exploration

Autoři: He, Liqiang Dolbeau, Romain Seznec, André a další

Přispěvatelé: He, Liqiang Dolbeau, Romain Seznec, André a další

Zdroj: https://inria.hal.science/inria-00116799 ; [Research Report] PI 1815, 2006, pp.59.

Témata: CASH, design space exploration, performance, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

Relation: Report N°: PI 1815

Dostupnost: https://inria.hal.science/inria-00116799
https://inria.hal.science/inria-00116799/document
https://inria.hal.science/inria-00116799/file/PI-1815.pdf

From Scilab to Multicore Embedded Systems: Algorithms and Methodologies

Autoři: Goulas, George Alefragis, Panayiotis Voros, Nikolaos S. a další

Přispěvatelé: Goulas, George Alefragis, Panayiotis Voros, Nikolaos S. a další

Zdroj: Proceedings of the IEEE International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (IC-SAMOS 2012 ; https://inria.hal.science/hal-00752615 ; Proceedings of the IEEE International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (IC-SAMOS 2012, Jul 2012, Samos, Greece

Témata: ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.4: Parallel Architectures, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

Geografické téma: Samos, Greece

Dostupnost: https://inria.hal.science/hal-00752615

Decoupled Thermal Simulation

Autoři: Guntur, Surendra Michaud, Pierre Compilation, parallel architectures and system (CAPS) a další

Přispěvatelé: Guntur, Surendra Michaud, Pierre Compilation, parallel architectures and system (CAPS) a další

Zdroj: https://inria.hal.science/inria-00192779 ; [Research Report] PI 1871, 2007, pp.31.

Témata: Temperature-constrained processor, performance, energy, simulation, program phase reuse, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [INFO.INFO-PF]Computer Science [cs]/Performance [cs.PF]

Relation: Report N°: PI 1871

Dostupnost: https://inria.hal.science/inria-00192779
https://inria.hal.science/inria-00192779/document
https://inria.hal.science/inria-00192779/file/PI-1871.pdf

Periodic activity migration for fast sequential execution in future heterogeneous multicore processors

Autoři: Michaud, Pierre Compilation, parallel architectures and system (CAPS) Institut de Recherche en Informatique et Systèmes Aléatoires (IRISA) a další

Přispěvatelé: Michaud, Pierre Compilation, parallel architectures and system (CAPS) Institut de Recherche en Informatique et Systèmes Aléatoires (IRISA) a další

Zdroj: https://inria.hal.science/inria-00340566 ; [Research Report] PI 1909, 2008, pp.20.

Témata: Heterogeneous multicore processor, power consumption, heat flux, periodic activity migration, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

Relation: Report N°: PI 1909

Dostupnost: https://inria.hal.science/inria-00340566
https://inria.hal.science/inria-00340566/document
https://inria.hal.science/inria-00340566/file/PI-1909.pdf

On the advantage of time-varying diversity of workload on Functionally Asymmetric multi-core

Autoři: Aminot, A. Lhuillier, Y. Chateigner, A. a další

Přispěvatelé: Aminot, A. Lhuillier, Y. Chateigner, A. a další

Zdroj: ADAPT '14 Proceedings of International Workshop on Adaptive Self-tuning Computing Systems ; https://hal-cea.archives-ouvertes.fr/cea-01818890 ; ADAPT '14 Proceedings of International Workshop on Adaptive Self-tuning Computing Systems, Jan 2014, Vienna, Austria. pp.11-13, ⟨10.1145/2553062.2553068⟩

Témata: Functional Asymmetry, multi-core, power efficiency, SIMD, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.3: Other Architecture Styles/C.1.3.5: Heterogeneous (hybrid) systems, [INFO]Computer Science [cs]

Geografické téma: Vienna, Austria

Relation: cea-01818890; https://hal-cea.archives-ouvertes.fr/cea-01818890

Dostupnost: https://hal-cea.archives-ouvertes.fr/cea-01818890
https://doi.org/10.1145/2553062.2553068

Impact of Increasing Number of Neurons on Performance of Neuromorphic Architecture

Autoři: Shahsavari, Mahyar Boulet, Pierre Shahbahrami, Asadollah a další

Přispěvatelé: Shahsavari, Mahyar Boulet, Pierre Shahbahrami, Asadollah a další

Zdroj: CADS 2017 - 19th CSI International Symposium on Computer Architecture & Digital Systems ; https://hal.science/hal-01633418 ; CADS 2017 - 19th CSI International Symposium on Computer Architecture & Digital Systems, Dec 2017, Kish, Iran

Témata: ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.3: Other Architecture Styles/C.1.3.7: Neural nets, ACM: I.: Computing Methodologies/I.5: PATTERN RECOGNITION, [INFO.INFO-NE]Computer Science [cs]/Neural and Evolutionary Computing [cs.NE], [INFO.INFO-CV]Computer Science [cs]/Computer Vision and Pattern Recognition [cs.CV], [INFO.INFO-AI]Computer Science [cs]/Artificial Intelligence [cs.AI]

Geografické téma: Kish, Iran

Dostupnost: https://hal.science/hal-01633418
https://hal.science/hal-01633418v1/document
https://hal.science/hal-01633418v1/file/Sub61_shahsavari_CADS17.pdf

Minimizing Single-Usage Cache Pollution for Effective Cache Hierarchy Management

Autoři: Piquet, Thomas Rochecouste, Olivier Seznec, André a další

Přispěvatelé: Piquet, Thomas Rochecouste, Olivier Seznec, André a další

Témata: Computer Architecture, Memory Hierarchy, Cache Pollution, Single-Usage Data, Block-Usage Prediction, Hardware Prefetching, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES, ACM: B.: Hardware/B.3: MEMORY STRUCTURES, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], archi, info

Relation: https://hal.inria.fr/inria-00116611/file/PI-1826.pdf; https://hal.inria.fr/inria-00116611

Dostupnost: https://hal.inria.fr/inria-00116611/file/PI-1826.pdf
https://hal.inria.fr/inria-00116611