Suchergebnisse - acm: c.: computer system organizacion/c.1: processor architectural/c.1.4: parallel architecture*

Distributed Architecture for Resource Management in Large Scale Grids

Autoren: Jeanvoine, Emmanuel Rilling, Louis Morin, Christine et al.

Weitere Verfasser: Jeanvoine, Emmanuel Rilling, Louis Morin, Christine et al.

Quelle: https://inria.hal.science/inria-00001066 ; [Research Report] PI 1775, 2006, pp.13.

Schlagwörter: Grid computing, distributed system, peer-to-peer overlay networks, resource allocation, self-healing \\ Grille de calcul, système distribué, réseaux logiques pair-à-pair, allocation de ressources, auto-réparation, ACM: C.: Computer Systems Organization/C.2: COMPUTER-COMMUNICATION NETWORKS/C.2.4: Distributed Systems, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.4: Parallel Architectures, [INFO.INFO-OH]Computer Science [cs]/Other [cs.OH]

Relation: Report N°: PI 1775

Verfügbarkeit: https://inria.hal.science/inria-00001066
https://inria.hal.science/inria-00001066v1/document
https://inria.hal.science/inria-00001066v1/file/PI-1775.pdf

Towards a New Processor Architecture. ; Vers une nouvelle Architecture de Processeurs

Autoren: Vincent, Pierre Landru, Jacques Ecole nationale supérieure Mines-Télécom Lille Douai (IMT Nord Europe) et al.

Weitere Verfasser: Vincent, Pierre Landru, Jacques Ecole nationale supérieure Mines-Télécom Lille Douai (IMT Nord Europe) et al.

Quelle: https://hal.science/hal-05117313 ; 2025.

Schlagwörter: silicon, parallel, serial, RISC, photonics, computer, optronics, optics, processor, fiber, laser, digital, silicium, parallèle, série, processeur, photonique, ordinateur, optronique, optique, numérique, fibre, ACM: B.: Hardware, ACM: C.: Computer Systems Organization, [INFO]Computer Science [cs], [PHYS]Physics [physics]

Verfügbarkeit: https://hal.science/hal-05117313
https://hal.science/hal-05117313v2/document
https://hal.science/hal-05117313v2/file/frParalSerieRiscV1.pdf

Scheduling issues on thermally-constrained processors

Autoren: Michaud, Pierre Sazeides, Yiannakis Compilation, parallel architectures and system (CAPS) et al.

Weitere Verfasser: Michaud, Pierre Sazeides, Yiannakis Compilation, parallel architectures and system (CAPS) et al.

Quelle: https://inria.hal.science/inria-00110507 ; [Research Report] PI 1822, 2006, pp.19.

Schlagwörter: Multi-core processor, temperature, thread scheduling, time slice, activity migration, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

Relation: Report N°: PI 1822

Verfügbarkeit: https://inria.hal.science/inria-00110507
https://inria.hal.science/inria-00110507/document
https://inria.hal.science/inria-00110507/file/PI-1822.pdf

Periodic activity migration for fast sequential execution in future heterogeneous multicore processors

Autoren: Michaud, Pierre Compilation, parallel architectures and system (CAPS) Institut de Recherche en Informatique et Systèmes Aléatoires (IRISA) et al.

Weitere Verfasser: Michaud, Pierre Compilation, parallel architectures and system (CAPS) Institut de Recherche en Informatique et Systèmes Aléatoires (IRISA) et al.

Quelle: https://inria.hal.science/inria-00340566 ; [Research Report] PI 1909, 2008, pp.20.

Schlagwörter: Heterogeneous multicore processor, power consumption, heat flux, periodic activity migration, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

Relation: Report N°: PI 1909

Verfügbarkeit: https://inria.hal.science/inria-00340566
https://inria.hal.science/inria-00340566/document
https://inria.hal.science/inria-00340566/file/PI-1909.pdf

FLPA: A New Methodology for Processor Power Characterization

Autoren: Laurent, Johann Lab-STICC_UBS_CACS_MOCS Laboratoire des sciences et techniques de l'information, de la communication et de la connaissance (Lab-STICC) et al.

Weitere Verfasser: Laurent, Johann Lab-STICC_UBS_CACS_MOCS Laboratoire des sciences et techniques de l'information, de la communication et de la connaissance (Lab-STICC) et al.

Quelle: Design Automation Conference ; https://hal.science/hal-00077558 ; 2002, pp100

Schlagwörter: FLPA, Power characterization, C code, Energy, Estimation, DSP VLIW, IEEE, ACM, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

Verfügbarkeit: https://hal.science/hal-00077558

High Level Transforms for SIMD and Low-Level Computer Vision Algorithms

Autoren: Lacassagne, Lionel Etiemble, Daniel Zahraee, Hassan et al.

Weitere Verfasser: Lacassagne, Lionel Etiemble, Daniel Zahraee, Hassan et al.

Quelle: Symposium on Principles and Practice of Parallel Programming / WPMVP ; https://inria.hal.science/hal-01094906 ; Symposium on Principles and Practice of Parallel Programming / WPMVP, Feb 2014, Orlando, Florida, United States. pp.8, ⟨10.1145/2568058.2568067⟩ ; https://sites.google.com/site/ppopp2014/

Schlagwörter: Intel SSE & XeonPhi, SIMD, High Level Transforms, ARM Neon, IBM Altivec, code optimization, 2D stencil, low-level computer vision and image processing algorithms, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.1: Single Data Stream Architectures, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.4: Parallel Architectures, ACM: D.: Software/D.1: PROGRAMMING TECHNIQUES/D.1.3: Concurrent Programming/D.1.3.1: Parallel programming, ACM: D.: Software/D.3: PROGRAMMING LANGUAGES/D.3.4: Processors/D.3.4.1: Compilers, ACM: D.: Software/D.3: PROGRAMMING LANGUAGES/D.3.4: Processors/D.3.4.6: Optimization, ACM: I.: Computing Methodologies/I.4: IMAGE PROCESSING AND COMPUTER VISION/I.4.7: Feature Measurement, [INFO.INFO-DS]Computer Science [cs]/Data Structures and Algorithms [cs.DS], [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [INFO.INFO-SE]Computer Science [cs]/Software Engineering [cs.SE], [INFO.INFO-DM]Computer Science [cs]/Discrete Mathematics [cs.DM], [INFO.INFO-RB]Computer Science [cs]/Robotics [cs.RO], [INFO.INFO-TI]Computer Science [cs]/Image Processing [eess.IV], [INFO.INFO-TS]Computer Science [cs]/Signal and Image Processing, [INFO.INFO-CV]Computer Science [cs]/Computer Vision and Pattern Recognition [cs.CV], [SPI.AUTO]Engineering Sciences [physics]/Automatic, [SPI.SIGNAL]Engineering Sciences [physics]/Signal and Image processing, [INFO.INFO-AO]Computer Science [cs]/Computer Arithmetic, [INFO.INFO-DC]Computer Science [cs]/Distributed, Parallel, and Cluster Computing [cs.DC]

Geographisches Schlagwort: Orlando, Florida, United States

Verfügbarkeit: https://inria.hal.science/hal-01094906
https://inria.hal.science/hal-01094906v1/document
https://inria.hal.science/hal-01094906v1/file/simd-140122.pdf
https://doi.org/10.1145/2568058.2568067

From Scilab to Multicore Embedded Systems: Algorithms and Methodologies

Autoren: Goulas, George Alefragis, Panayiotis Voros, Nikolaos S. et al.

Weitere Verfasser: Goulas, George Alefragis, Panayiotis Voros, Nikolaos S. et al.

Quelle: Proceedings of the IEEE International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (IC-SAMOS 2012 ; https://inria.hal.science/hal-00752615 ; Proceedings of the IEEE International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (IC-SAMOS 2012, Jul 2012, Samos, Greece

Schlagwörter: ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.4: Parallel Architectures, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

Geographisches Schlagwort: Samos, Greece

Verfügbarkeit: https://inria.hal.science/hal-00752615

Implementing Wilson-Dirac Operator on the Cell Broadband Engine

Autoren: Ibrahim, Khaled Z. Bodin, François Compilation, parallel architectures and system (CAPS) et al.

Weitere Verfasser: Ibrahim, Khaled Z. Bodin, François Compilation, parallel architectures and system (CAPS) et al.

Quelle: https://inria.hal.science/inria-00203478 ; [Research Report] PI 1880, 2007, pp.23.

Schlagwörter: IBM Cell BE, Vectorization, SIMD, Lattice QCD, Parallel Algorithms, Wilson-Dirac, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

Relation: Report N°: PI 1880

Verfügbarkeit: https://inria.hal.science/inria-00203478
https://inria.hal.science/inria-00203478v1/document
https://inria.hal.science/inria-00203478v1/file/PI-1880.pdf

Architecture Studies and System Demonstrations of Optical Parallel Processor for AI and NI

Autoren: Lee, Sing H. Esener, Sadik C. CALIFORNIA UNIV SAN DIEGO LA JOLLA DEPT OF ELECTRICAL AND COMPUTER ENGINEERING

Weitere Verfasser: Lee, Sing H. Esener, Sadik C. CALIFORNIA UNIV SAN DIEGO LA JOLLA DEPT OF ELECTRICAL AND COMPUTER ENGINEERING

Quelle: DTIC AND NTIS

Schlagwörter: Electrooptical and Optoelectronic Devices, Computer Hardware, COMPUTER ARCHITECTURE, MULTIPROCESSORS, PARALLEL PROCESSORS, OPTICAL PROCESSING, ELECTROOPTICS, COMPUTER PROGRAMMING, NERVOUS SYSTEM, ARTIFICIAL INTELLIGENCE, DEMONSTRATIONS, ARCHITECTURE, INTELLIGENCE, OPTICAL EQUIPMENT, ALGORITHMS, PROTOTYPES

Dateibeschreibung: text/html

Relation: http://www.dtic.mil/docs/citations/ADA244170

Verfügbarkeit: http://www.dtic.mil/docs/citations/ADA244170
http://oai.dtic.mil/oai/oai?&verb=getRecord&metadataPrefix=html&identifier=ADA244170

Covariance tracking: architecture optimizations for embedded systems

Autoren: Romero, Andrés Lacassagne, Lionel Gouiffès, Michèle et al.

Weitere Verfasser: Romero, Andrés Lacassagne, Lionel Gouiffès, Michèle et al.

Quelle: ISSN: 1687-6172.

Schlagwörter: covariance-tracking, real-time image processing, SIMD, SSE, AVX, Neon, ACM: I.: Computing Methodologies/I.4: IMAGE PROCESSING AND COMPUTER VISION/I.4.8: Scene Analysis/I.4.8.2: Motion, ACM: I.: Computing Methodologies/I.4: IMAGE PROCESSING AND COMPUTER VISION/I.4.8: Scene Analysis/I.4.8.12: Tracking, ACM: I.: Computing Methodologies/I.4: IMAGE PROCESSING AND COMPUTER VISION/I.4.7: Feature Measurement/I.4.7.1: Invariants, ACM: I.: Computing Methodologies/I.4: IMAGE PROCESSING AND COMPUTER VISION/I.4.7: Feature Measurement/I.4.7.2: Moments, ACM: I.: Computing Methodologies/I.4: IMAGE PROCESSING AND COMPUTER VISION/I.4.7: Feature Measurement/I.4.7.5: Texture, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.4: Parallel Architectures/C.1.4.1: Mobile processors, ACM: D.: Software/D.3: PROGRAMMING LANGUAGES/D.3.4: Processors/D.3.4.6: Optimization, [INFO.INFO-DS]Computer Science [cs]/Data Structures and Algorithms [cs.DS], [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [SPI.AUTO]Engineering Sciences [physics]/Automatic, [SPI.SIGNAL]Engineering Sciences [physics]/Signal and Image processing, [INFO.INFO-AO]Computer Science [cs]/Computer Arithmetic, [INFO.INFO-DC]Computer Science [cs]/Distributed, Parallel, and Cluster Computing [cs.DC], [INFO.INFO-SE]Computer Science [cs]/Software Engineering [cs.SE], [INFO.INFO-DM]Computer Science [cs]/Discrete Mathematics [cs.DM], [INFO.INFO-RB]Computer Science [cs]/Robotics [cs.RO], [INFO.INFO-TI]Computer Science [cs]/Image Processing [eess.IV], [INFO.INFO-TS]Computer Science [cs]/Signal and Image Processing, [INFO.INFO-CV]Computer Science [cs]/Computer Vision and Pattern Recognition [cs.CV]

Verfügbarkeit: https://inria.hal.science/hal-01094903
https://inria.hal.science/hal-01094903v1/document
https://inria.hal.science/hal-01094903v1/file/Eurasip%202014-12.pdf
https://doi.org/10.1186/1687-6180-2014-175

A parallel pipelined relational query processor ; An architectural overview

Autoren: Gajski, Daniel Kim, Won Fushimi, Shinya

Quelle: ACM SIGARCH Computer Architecture News ; volume 12, issue 3, page 134-141 ; ISSN 0163-5964

Verfügbarkeit: https://doi.org/10.1145/773453.808175
https://dl.acm.org/doi/10.1145/773453.808175
https://dl.acm.org/doi/pdf/10.1145/773453.808175

Scientific Workflow Scheduling with Provenance Support in Multisite Cloud

Autoren: Liu, Ji Pacitti, Esther Valduriez, Patrick et al.

Weitere Verfasser: Liu, Ji Pacitti, Esther Valduriez, Patrick et al.

Quelle: 12th International Conference on Vector and Parallel Processing
VECPAR: Vector and Parallel Processing
https://hal-lirmm.ccsd.cnrs.fr/lirmm-01342190
VECPAR: Vector and Parallel Processing, Faculty of Engineering of the University of Porto, Portugal, Jun 2016, Porto, Portugal. pp.206-219, ⟨10.1007/978-3-319-61982-8_19⟩
http://vecpar.fe.up.pt/2016/

Schlagwörter: Scientific workflow, Scientific workflow management system, Parallel execution, Multisite cloud, Scheduling, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.4: Parallel Architectures/C.1.4.0: Distributed architectures, [INFO.INFO-DB]Computer Science [cs]/Databases [cs.DB]

Geographisches Schlagwort: Porto, Portugal

Time: Porto, Portugal

Relation: info:eu-repo/grantAgreement//689772/EU/HPC for Energy/HPC4E

Verfügbarkeit: https://hal-lirmm.ccsd.cnrs.fr/lirmm-01342190
https://hal-lirmm.ccsd.cnrs.fr/lirmm-01342190v1/document
https://hal-lirmm.ccsd.cnrs.fr/lirmm-01342190v1/file/VECPAR.pdf
https://doi.org/10.1007/978-3-319-61982-8_19

The K2 parallel processor ; architecture and hardware implementation

Autoren: Annaratone, Marco Fillo, Marco Nakabayashi, Kiyoshi et al.

Quelle: ACM SIGARCH Computer Architecture News ; volume 18, issue 2SI, page 92-101 ; ISSN 0163-5964

Verfügbarkeit: https://doi.org/10.1145/325096.325118
https://dl.acm.org/doi/10.1145/325096.325118
https://dl.acm.org/doi/pdf/10.1145/325096.325118

Parallel Evaluation of Hopfield Neural Networks

Autoren: Eiche, Antoine Chillet, Daniel Pillement, Sébastien et al.

Weitere Verfasser: Eiche, Antoine Chillet, Daniel Pillement, Sébastien et al.

Quelle: NCTA, International Conference on Neural Computation Theory and Applications ; https://inria.hal.science/hal-00650633 ; NCTA, International Conference on Neural Computation Theory and Applications, Oct 2011, Paris, France

Schlagwörter: ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.3: Other Architecture Styles/C.1.3.7: Neural nets

Geographisches Schlagwort: Paris, France

Verfügbarkeit: https://inria.hal.science/hal-00650633

Dynamic sharing of a multiple access channel

Autoren: Bienkowski, Marcin Klonowski, Marek Korzeniowski, Miroslaw et al.

Weitere Verfasser: Bienkowski, Marcin Klonowski, Marek Korzeniowski, Miroslaw et al.

Quelle: 27th International Symposium on Theoretical Aspects of Computer Science - STACS 2010
https://inria.hal.science/inria-00457096
27th International Symposium on Theoretical Aspects of Computer Science - STACS 2010, Inria Nancy Grand Est & Loria, Mar 2010, Nancy, France. pp.83-94

Schlagwörter: distributed algorithms, multiple access channel, mutual exclusion, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.4: Parallel Architectures, ACM: C.: Computer Systems Organization/C.2: COMPUTER-COMMUNICATION NETWORKS/C.2.1: Network Architecture and Design, ACM: F.: Theory of Computation/F.2: ANALYSIS OF ALGORITHMS AND PROBLEM COMPLEXITY/F.2.2: Nonnumerical Algorithms and Problems, [INFO.INFO-DS]Computer Science [cs]/Data Structures and Algorithms [cs.DS]

Geographisches Schlagwort: Nancy, France

Relation: inria-00457096; https://inria.hal.science/inria-00457096; https://inria.hal.science/inria-00457096/document; https://inria.hal.science/inria-00457096/file/bienkowski.pdf

Verfügbarkeit: https://inria.hal.science/inria-00457096
https://inria.hal.science/inria-00457096/document
https://inria.hal.science/inria-00457096/file/bienkowski.pdf

Parallel LDPC Decoding on the Cell/B.E. Processor

Autoren: Falcão, Gabriel Sousa, Leonel Silva, Vitor et al.

Weitere Verfasser: Falcão, Gabriel Sousa, Leonel Silva, Vitor et al.

Quelle: HiPEAC 2009 - High Performance and Embedded Architectures and Compilers ; https://hal.inria.fr/inria-00446368 ; HiPEAC 2009 - High Performance and Embedded Architectures and Compilers, Jan 2009, Paphos, Cyprus. ⟨10.1007/978-3-540-92990-1_28⟩

Schlagwörter: ACM: B.: Hardware/B.2: ARITHMETIC AND LOGIC STRUCTURES, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES, ACM: D.: Software/D.3: PROGRAMMING LANGUAGES/D.3.4: Processors, [INFO.INFO-OH]Computer Science [cs]/Other [cs.OH], [INFO.INFO-ES]Computer Science [cs]/Embedded Systems

Geographisches Schlagwort: Paphos, Cyprus

Relation: inria-00446368; https://hal.inria.fr/inria-00446368

Verfügbarkeit: https://hal.inria.fr/inria-00446368
https://doi.org/10.1007/978-3-540-92990-1_28

CASH Design Space Exploration

Autoren: He, Liqiang Dolbeau, Romain Seznec, André et al.

Weitere Verfasser: He, Liqiang Dolbeau, Romain Seznec, André et al.

Quelle: https://inria.hal.science/inria-00116799 ; [Research Report] PI 1815, 2006, pp.59.

Schlagwörter: CASH, design space exploration, performance, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

Relation: Report N°: PI 1815

Verfügbarkeit: https://inria.hal.science/inria-00116799
https://inria.hal.science/inria-00116799/document
https://inria.hal.science/inria-00116799/file/PI-1815.pdf

Contributions to Program Optimization and High-Level Synthesis ; Contributions à l'optimisation de programmes et à la synthèse de circuits haut-niveau

Autoren: Alias, Christophe CASH - Compilation and Analysis, Software and Hardware (CASH) Centre Inria de l'Université Grenoble Alpes et al.

Weitere Verfasser: Alias, Christophe CASH - Compilation and Analysis, Software and Hardware (CASH) Centre Inria de l'Université Grenoble Alpes et al.

Quelle: https://inria.hal.science/tel-02151877 ; Hardware Architecture [cs.AR]. ENS de Lyon, 2019.

Schlagwörter: High-Level Synthesis, Compilation Techniques, Automatic Parallelization, Compilation, Parallélisation automatique, Synthèse haut-niveau, FPGA, ACM: B.: Hardware, ACM: B.: Hardware/B.6: LOGIC DESIGN/B.6.3: Design Aids/B.6.3.0: Automatic synthesis, ACM: B.: Hardware/B.6: LOGIC DESIGN/B.6.3: Design Aids/B.6.3.2: Optimization, ACM: D.: Software/D.3: PROGRAMMING LANGUAGES/D.3.4: Processors/D.3.4.1: Compilers, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.4: Parallel Architectures, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [INFO.INFO-DC]Computer Science [cs]/Distributed, Parallel, and Cluster Computing [cs.DC], [INFO.INFO-PL]Computer Science [cs]/Programming Languages [cs.PL]

Verfügbarkeit: https://inria.hal.science/tel-02151877
https://inria.hal.science/tel-02151877v2/document
https://inria.hal.science/tel-02151877v2/file/hdr-alias.pdf

Appears in ACM Transactions on Computer System. Efficient Reuse Distance Analysis of Multicore Scaling for Loop-based Parallel Programs

Weitere Verfasser: The Pennsylvania State University CiteSeerX Archives

Quelle: http://maggini.eng.umd.edu/pub/sca-tr-2012.pdf.

Dateibeschreibung: application/pdf

Relation: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.258.3002

Verfügbarkeit: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.258.3002
http://maggini.eng.umd.edu/pub/sca-tr-2012.pdf

EdgeMORE: improving resource allocation with multiple options from tenants

Autoren: Araldo, Andrea Stefano, Alessandro, Di Di Stefano, Antonella et al.

Weitere Verfasser: Araldo, Andrea Stefano, Alessandro, Di Di Stefano, Antonella et al.

Quelle: CCNC 2020: 17th Consumer Communications & Networking Conference ; https://hal.science/hal-02459433 ; CCNC 2020: 17th Consumer Communications & Networking Conference, Jan 2020, Las Vegas, United States. pp.1-6, ⟨10.1109/CCNC46108.2020.9045173⟩

Schlagwörter: Cloud-edge offloading, Resource allocation, Edge computing, ACM: C.: Computer Systems Organization/C.2: COMPUTER-COMMUNICATION NETWORKS/C.2.1: Network Architecture and Design/C.2.1.3: Distributed networks, ACM: C.: Computer Systems Organization/C.2: COMPUTER-COMMUNICATION NETWORKS/C.2.4: Distributed Systems, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.4: Parallel Architectures/C.1.4.0: Distributed architectures, [INFO.INFO-NI]Computer Science [cs]/Networking and Internet Architecture [cs.NI]

Geographisches Schlagwort: Las Vegas, United States

Verfügbarkeit: https://hal.science/hal-02459433
https://hal.science/hal-02459433v1/document
https://hal.science/hal-02459433v1/file/_CCNC2020__EdgeMore_mproving_resource_allocation_with_multiple_options_from_tenants.pdf
https://doi.org/10.1109/CCNC46108.2020.9045173