Search Results - acm: c.: computer system organizacija/c.1: processor architektury/c.1.4: parallel architektury

TALL—a list processor for the Philco 2000 computer

Authors: Feldman, Julian

Source: Communications of the ACM. 5(9)

Subject Terms: Information and Computing Sciences, Information Systems, Information and computing sciences

File Description: application/pdf

Access URL: https://escholarship.org/uc/item/6qk36727
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Multiplication of Matrices of Arbitrary Shape on a Data Parallel Computer

Authors: Mathur, Kapil K. Johnsson, S. Lennart

Source: Mathur, Kapil K. and S. Lennart Johnsson. Multiplication of Matrices of Arbitrary Shape on a Data Parallel Computer. Harvard Computer Science Group Technical Report TR-01-92.

Access URL: http://nrs.harvard.edu/urn-3:HUL.InstRepos:23017262

Využití architektury TRIPS pro řešení výpočetně náročných úloh

Authors: Krutek, Roland Krumnikl, Michal Gaura, Jan

Contributors: Krutek, Roland Krumnikl, Michal Gaura, Jan

Subject Terms: TRIPS, Tera-op Reliable Intelligently Adaptive Processing System, EDGE, Explicit Data Graph Execution, procesorová architektura, paralelizmus, paralelní výpočty, polymorfní procesor, processor architecture, parallelism, parallel computation, polymorph processor

File Description: 1977663 bytes; application/pdf; application/octet-stream; text/plain; image/jpeg; downloadable_files_count: 5

Relation: OSD002; https://hdl.handle.net/10084/87594; S2724; KRU255_FEI_B2647_2612R025_2011

Availability: https://hdl.handle.net/10084/87594

Analysis of FPGA accelerator architecture for Fast Statistical Convolutional Neural Network in real time Emotional Recognition System.

Alternate Title: Analiza architektury akceleratora FPGA dla szybkiej statystycznej sieci splotowej w systemie rozpoznawania emocji w czasie rzeczywistym. (Polish)

Authors: Samson Immanuel, J. Manoj, G. Prince, Shajin et al.

Source: Przegląd Elektrotechniczny; 2021, Vol. 97 Issue 7, p132-134, 3p

Subject Terms: DEEP learning, CONVOLUTIONAL neural networks, ARTIFICIAL intelligence, APPLICATION-specific integrated circuits, FIELD programmable gate arrays, ALGORITHMS

Paralelní výpočetní architektury založené na numerické integraci ; Parallel Computer Systems Based on Numerical Integrations

Authors: Kraus, Michal Kunovský, Jiří Kubátová, Hana et al.

Contributors: Kraus, Michal Kunovský, Jiří Kubátová, Hana et al.

Subject Terms: numerická integrace, Taylorova řada, paralelní systém, propojovací sítě, integrátor, numerical integration, Taylor series, parallel system, interconnection networks, integrator

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Relation: KRAUS, M. Paralelní výpočetní architektury založené na numerické integraci [online]. Brno: Vysoké učení technické v Brně. Fakulta informačních technologií. .; 99804; http://hdl.handle.net/11012/63230

Availability: http://hdl.handle.net/11012/63230

Paralelní výpočetní architektury založené na numerické integraci

Parallel Computer Systems Based on Numerical Integrations

Authors: Kraus, Michal

Thesis Advisors: Kubátová, Hana, Kollár,, Ján, Kunovský, Jiří

Subject Terms: interconnection networks, propojovací sítě, paralelní systém, numerická integrace, integrator, parallel system, integrátor, numerical integration, Taylorova řada, Taylor series

Availability: http://www.nusl.cz/ntk/nusl-261227

Multi-core and Single-core Raspberry Pi Microprocessor's.

Alternate Title: Wielordzeniowe i jednordzeniowe mikroprocesory Raspberry Pi. (Polish)

Authors: SAINUDDIN, Nurulidayu MOHD SULTAN, Juwita AZUANI, Mohamed

Source: Przegląd Elektrotechniczny; 2023, Vol. 99 Issue 1, p38-43, 6p

Subject Terms: RASPBERRY Pi, CENTRAL processing units, MICROPROCESSORS, COMPUTER performance, COMPUTER multitasking, MULTICORE processors

PDES-A

Authors: Rahman, Shafiur Abu-Ghazaleh, Nael Najjar, Walid

Source: ACM Transactions on Modeling and Computer Simulation. 29(2)

Subject Terms: PDES, FPGA, accelerator, coprocessor, parallel simulation, Computation Theory and Mathematics, Information Systems, Operations Research

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Access URL: https://escholarship.org/uc/item/2z10p5n0
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Peephole optimalizátor pro konfigurovatelné architektury procesorů ; Peephole Optimizer for Configurable Processor Architectures

Authors: Ministr, Martin Masařík, Karel Křoustek, Jakub

Contributors: Ministr, Martin Masařík, Karel Křoustek, Jakub

Subject Terms: peephole optimalizátor, peephole optimalizace, LLVM, backend, překladač, mikroprocesorová architektura, popis architektury, peephole optimizer, peephole optimization, compiler, microprocessor architecture, architecture description

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Relation: MINISTR, M. Peephole optimalizátor pro konfigurovatelné architektury procesorů [online]. Brno: Vysoké učení technické v Brně. Fakulta informačních technologií. 2012.; 79137; http://hdl.handle.net/11012/52891

Availability: http://hdl.handle.net/11012/52891

Virtual Ways: Low-Cost Coherence for Instruction Set Extensions with Architecturally Visible Storage

Authors: Kluter, Theo Burri, Samuel Brisk, Philip et al.

Source: ACM Transactions on Architecture and Code Optimization. 11(2)

Subject Terms: Affordable and Clean Energy, Performance, Design, Experimentation, Instruction set extension, architecturally visible storage, memory coherence, memory consistence, Virtual Ways, Computer Software, Electrical and Electronic Engineering

Access URL: https://escholarship.org/uc/item/4x32223n

Návrh pokročilé architektury procesoru v jazyce VHDL

Authors: Slavík, Daniel Straka, Martin Šimek, Václav

Contributors: Slavík, Daniel Straka, Martin Šimek, Václav

Subject Terms: scalar, RAM, superscalar, návrh, design, procesor, cache, subscalar, VHDL, superskalární, processor, subskalární, skalární

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Access URL: http://hdl.handle.net/11012/54277

Architektura macierzy stosów do przetwarzania równoległego z wykorzystaniem odwrotnej notacji polskiej. (Polish)

Alternate Title: Stack matrix architecture for parallel processing using reverse Polish notation. (English)

Authors: GOŁKA, Łukasz SUSZYŃSKI, Robert POCZEKAJŁO, Paweł

Source: Przegląd Elektrotechniczny; 2025, Issue 10, p82-89, 8p

Subject Terms: PARALLEL processing, SIMD (Computer architecture), CENTRAL processing units, MATHEMATICAL notation

Communication efficient multi-processor FFT

Authors: Johnsson, S. Lennart Jacquemin, Michel Krawitz, Robert L.

Source: Johnsson, S. Lennart, Michel Jacquemin, and Robert L. Krawitz. 1991. Communication efficient multi-processor FFT. Harvard Computer Science Group Technical Report TR-25-91.

Relation: Harvard Computer Science Group Technical Report

Access URL: http://nrs.harvard.edu/urn-3:HUL.InstRepos:35059732

Automatické řízení výpočtu ve specializovaném výpočetním systému ; Specialized Computer System Automatic Control

Authors: Opálka, Jan Kunovský, Jiří Šátek, Václav

Contributors: Opálka, Jan Kunovský, Jiří Šátek, Václav

Subject Terms: derivace, diferenciální rovnice, Taylorova řada, mikroprocesor, numerická integrace, pevná řádová čárka, pohyblivá řádová čárka, integrátor, řadič, boothův algoritmus, paralelní architektury, derivation, diferential equnation, Taylor series, mikroprocessor, numeric integration, fixed point, floating point, integrator, controller, Booth algorithm, parallel architectures

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Relation: OPÁLKA, J. Automatické řízení výpočtu ve specializovaném výpočetním systému [online]. Brno: Vysoké učení technické v Brně. Fakulta informačních technologií. 2016.; 103587; http://hdl.handle.net/11012/69421

Availability: http://hdl.handle.net/11012/69421

NEC research & development

Authors: 日本電気株式会社

Source: 39(4);1998・10

Paralelní výpočetní architektury založené na numerické integraci

Authors: Kraus, Michal Kunovský, Jiří Kubátová, Hana et al.

Contributors: Kraus, Michal Kunovský, Jiří Kubátová, Hana et al.

Subject Terms: integrátor, propojovací sítě, parallel system, numerická integrace, numerical integration, Taylor series, integrator, Taylorova řada, paralelní systém, interconnection networks

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Access URL: http://hdl.handle.net/11012/63230

A Shift Selection Strategy for Parallel Shift-invert Spectrum Slicing in Symmetric Self-consistent Eigenvalue Computation

Authors: Williams-Young, DB Beckman, PG Yang, C

Source: ACM Transactions on Mathematical Software. 46(4)

Subject Terms: Eigenvalues, parallel eigenvalue algorithms, self-consistent field, shift-invert spectrum slicing, math.NA, cs.DC, cs.NA, physics.comp-ph, Numerical & Computational Mathematics, Computation Theory and Mathematics, Information Systems

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Access URL: https://escholarship.org/uc/item/5840h0mj
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Automatické řízení výpočtu ve specializovaném výpočetním systému

Specialized Computer System Automatic Control

Authors: Opálka, Jan

Thesis Advisors: Šátek, Václav, Kunovský, Jiří

Subject Terms: řadič, floating point, integrator, numeric integration, mikroprocessor, pohyblivá řádová čárka, derivace, parallel architectures, Taylor series, numerická integrace, paralelní architektury, diferential equnation, controller, Taylorova řada, mikroprocesor, pevná řádová čárka, derivation, diferenciální rovnice, Booth algorithm, boothův algoritmus, integrátor, fixed point

Availability: http://www.nusl.cz/ntk/nusl-363728

Distributed merge trees

Authors: Morozov, D Weber, GH

Source: ACM Sigplan Notices. 48(8)

Subject Terms: Information and Computing Sciences, Applied Computing, topological data analysis, feature extraction, merge tree computation, parallelization, hybrid parallelization approaches, Software Engineering

File Description: application/pdf

Access URL: https://escholarship.org/uc/item/49d568wd
https://escholarship.org/content/qt49d568wd/qt49d568wd.pdf

Papers Presented at the ACM SIGCSE Technical Symposium on Academic Education in Computer Science [held in Houston, Texas, November 16, 1970].

Authors: Association for Computing Machinery, New York, NY. Aiken, Robert M.

Source: SIGCSE Bulletin. Special Issue 2(3).

Peer Reviewed: N

Page Count: 132

Descriptors: Automation, Computer Assisted Instruction, Computer Programs, Computer Science Education, Computers, Conferences, Program Design, Programing, Programing Problems, Systems Development, Undergraduate Study

Journal Code: RIEDEC1971