Suchergebnisse - acm: c.: computer system organizacija/c.1: processor architekture/c.1.4: parallel architekture~

TALL—a list processor for the Philco 2000 computer

Autoren: Feldman, Julian

Quelle: Communications of the ACM. 5(9)

Schlagwörter: Information and Computing Sciences, Information Systems, Information and computing sciences

Dateibeschreibung: application/pdf

Zugangs-URL: https://escholarship.org/uc/item/6qk36727
https://escholarship.org/content/qt6qk36727/qt6qk36727.pdf

Multiplication of Matrices of Arbitrary Shape on a Data Parallel Computer

Autoren: Mathur, Kapil K. Johnsson, S. Lennart

Quelle: Mathur, Kapil K. and S. Lennart Johnsson. Multiplication of Matrices of Arbitrary Shape on a Data Parallel Computer. Harvard Computer Science Group Technical Report TR-01-92.

Zugangs-URL: http://nrs.harvard.edu/urn-3:HUL.InstRepos:23017262

Analiza parametrów czasowych architektury potokowej specjalizowanych procesorów sprzętowychThe parameters analysis for pipeline architekture of specialised hardware processor

Autoren: Wiatr, K.

Schlagwörter: systemy czasu rzeczywistego, architektury systemów wieloprocesorowych, układy programowalne, image processing systems, architecture hardware processors

Zugangs-URL: http://yadda.icm.edu.pl/baztech/element/bwmeta1.element.baztech-article-BWA1-0001-0487

Akcelerace algoritmů na architektuře Larrabee ; Algorithm Acceleration on Larrabee Platform

Autoren: Veselý, Ivo Zemčík, Pavel Seeman, Michal

Weitere Verfasser: Veselý, Ivo Zemčík, Pavel Seeman, Michal

Schlagwörter: Larrabee, počítačová grafika, zpracování obrazu, více-jádrové počítání, paralelní počítání, SIMD, GPGPU, syntéza hologramu, optické pole, computer graphics, image processing, many-core computing, parallel computing, hologram synthesis, optical field

Dateibeschreibung: application/pdf; text/html

Relation: VESELÝ, I. Akcelerace algoritmů na architektuře Larrabee [online]. Brno: Vysoké učení technické v Brně. Fakulta informačních technologií. 2010.; 34936; http://hdl.handle.net/11012/52800

Verfügbarkeit: http://hdl.handle.net/11012/52800

PDES-A

Autoren: Rahman, Shafiur Abu-Ghazaleh, Nael Najjar, Walid

Quelle: ACM Transactions on Modeling and Computer Simulation. 29(2)

Schlagwörter: PDES, FPGA, accelerator, coprocessor, parallel simulation, Computation Theory and Mathematics, Information Systems, Operations Research

Dateibeschreibung: application/pdf

Zugangs-URL: https://escholarship.org/uc/item/2z10p5n0
https://escholarship.org/content/qt2z10p5n0/qt2z10p5n0.pdf

Informace o architektuře pro optimalizace v překladači LLVM ; Architecture Information for LLVM Compiler Optimizations

Autoren: Svoboda, Jan Hruška, Tomáš Dolíhal, Luděk

Weitere Verfasser: Svoboda, Jan Hruška, Tomáš Dolíhal, Luděk

Schlagwörter: překladač, optimalizace, cenový model, procesor, architektura, Codasip, CodAL, LLVM, compiler, optimization, cost model, processor, architecture

Dateibeschreibung: application/pdf; text/html

Relation: SVOBODA, J. Informace o architektuře pro optimalizace v překladači LLVM [online]. Brno: Vysoké učení technické v Brně. Fakulta informačních technologií. 2020.; 129281; http://hdl.handle.net/11012/192463

Verfügbarkeit: http://hdl.handle.net/11012/192463

Otrazhenie rimskogo mifa v russkoj architekture XVIII veka [Riflessi del mito di Roma nell'architettura russa del XVIII sec.]

Autoren: GIULIANI, Rita C. DI MEO

Zugangs-URL: https://hdl.handle.net/11573/168174

EXPANSION OF THE ZONE OF PRACTICAL APPLICATION OF PLC WITH PARALLEL ARCHITECTURE ; ROZSZERZENIE STREFY PRAKTYCZNEGO ZASTOSOWANIA PLC O ARCHITEKTURĘ RÓWNOLEGŁĄ

Autoren: Tymchuk, Sergiy Piskarev, Oleksiy Miroshnyk, Oleksandr et al.

Quelle: Informatyka, Automatyka, Pomiary w Gospodarce i Ochronie Środowiska; Vol. 12 No. 3 (2022); 16-19 ; Informatyka, Automatyka, Pomiary w Gospodarce i Ochronie Środowiska; Tom 12 Nr 3 (2022); 16-19 ; 2391-6761 ; 2083-0157

Schlagwörter: programmable logic controllers, parallel architecture, software control system, programowalne sterowniki logiczne, architektura równoległa, programowy system sterowania

Dateibeschreibung: application/pdf

Relation: https://ph.pollub.pl/index.php/iapgos/article/view/2983/2726; https://ph.pollub.pl/index.php/iapgos/article/view/2983

Verfügbarkeit: https://ph.pollub.pl/index.php/iapgos/article/view/2983

Virtual Ways: Low-Cost Coherence for Instruction Set Extensions with Architecturally Visible Storage

Autoren: Kluter, Theo Burri, Samuel Brisk, Philip et al.

Quelle: ACM Transactions on Architecture and Code Optimization. 11(2)

Schlagwörter: Affordable and Clean Energy, Performance, Design, Experimentation, Instruction set extension, architecturally visible storage, memory coherence, memory consistence, Virtual Ways, Computer Software, Electrical and Electronic Engineering

Zugangs-URL: https://escholarship.org/uc/item/4x32223n

Communication efficient multi-processor FFT

Autoren: Johnsson, S. Lennart Jacquemin, Michel Krawitz, Robert L.

Quelle: Johnsson, S. Lennart, Michel Jacquemin, and Robert L. Krawitz. 1991. Communication efficient multi-processor FFT. Harvard Computer Science Group Technical Report TR-25-91.

Relation: Harvard Computer Science Group Technical Report

Zugangs-URL: http://nrs.harvard.edu/urn-3:HUL.InstRepos:35059732

NEC research & development

Autoren: 日本電気株式会社

Quelle: 39(4);1998・10

A Shift Selection Strategy for Parallel Shift-invert Spectrum Slicing in Symmetric Self-consistent Eigenvalue Computation

Autoren: Williams-Young, DB Beckman, PG Yang, C

Quelle: ACM Transactions on Mathematical Software. 46(4)

Schlagwörter: Eigenvalues, parallel eigenvalue algorithms, self-consistent field, shift-invert spectrum slicing, math.NA, cs.DC, cs.NA, physics.comp-ph, Numerical & Computational Mathematics, Computation Theory and Mathematics, Information Systems

Dateibeschreibung: application/pdf

Zugangs-URL: https://escholarship.org/uc/item/5840h0mj
https://escholarship.org/content/qt5840h0mj/qt5840h0mj.pdf

Distributed merge trees

Autoren: Morozov, D Weber, GH

Quelle: ACM Sigplan Notices. 48(8)

Schlagwörter: Information and Computing Sciences, Applied Computing, topological data analysis, feature extraction, merge tree computation, parallelization, hybrid parallelization approaches, Software Engineering

Dateibeschreibung: application/pdf

Zugangs-URL: https://escholarship.org/uc/item/49d568wd
https://escholarship.org/content/qt49d568wd/qt49d568wd.pdf

Papers Presented at the ACM SIGCSE Technical Symposium on Academic Education in Computer Science [held in Houston, Texas, November 16, 1970].

Autoren: Association for Computing Machinery, New York, NY. Aiken, Robert M.

Quelle: SIGCSE Bulletin. Special Issue 2(3).

Peer Reviewed: N

Page Count: 132

Descriptors: Automation, Computer Assisted Instruction, Computer Programs, Computer Science Education, Computers, Conferences, Program Design, Programing, Programing Problems, Systems Development, Undergraduate Study

Journal Code: RIEDEC1971

The Impact of Operating System Structure on Personal Computer Performance

Autoren: Chen, J. Bradley Endo, Yashuhiro Chan, Kee et al.

Quelle: Chen, J. Bradley, Yasohiro Endo, Kee Chan, David Mazieres, Antonio Dias, Margo Seltzer, and Michael D. Smith. 1995. The Impact of Operating System Structure on Personal Computer Performance. Harvard Computer Science Group Technical Report TR-09-95.

Dateibeschreibung: application/pdf

Zugangs-URL: http://nrs.harvard.edu/urn-3:HUL.InstRepos:24829608

Návrh paralelního soft-procesoru ; Design of Parallel Soft-processor

Autoren: Patera Adam Vítek Stanislav Veřtát Ivo

Weitere Verfasser: Patera Adam Vítek Stanislav Veřtát Ivo

Schlagwörter: Soft-mikroprocesor,CORDIC,UMA, Soft-microprocessor,CORDIC,UMA

Relation: http://hdl.handle.net/10467/73926

Verfügbarkeit: http://hdl.handle.net/10467/73926

Audio Processing on Field-Programmable Gate Arrays

Autoren: Sharum, Mitchell Calmon, Flavio

Weitere Verfasser: Sharum, Mitchell Calmon, Flavio

Quelle: Sharum, Mitchell. 2025. Audio Processing on Field-Programmable Gate Arrays. Bachelors Thesis, Harvard University Engineering and Applied Sciences.

Schlagwörter: Audio Processor, Digital Audio, Digital Signal Processing, Field-programmable Gate Array, RTL, SystemVerilog, Electrical engineering, Computer science

Dateibeschreibung: application/pdf; application/pdf

Zugangs-URL: https://dash.harvard.edu/handle/1/42719263

On the Transportation and Distribution of Data Structures in Parallel and Distributed Systems

Autoren: Fahmy, Amr Wagner, Robert A.

Quelle: Fahmy, Amr F. and Robert A. Wagner. 1995. On the Transportation and Distribution of Data Structures in Parallel and Distributed Systems. Harvard Computer Science Group Technical Report TR-27-95.

Dateibeschreibung: application/pdf

Zugangs-URL: http://nrs.harvard.edu/urn-3:HUL.InstRepos:26506440

Parallel variable selection for effective performance prediction

Autoren: Wang, J Yoo, W Sim, A et al.

Quelle: Proceedings - 2017 17th IEEE/ACM International Symposium on Cluster, Cloud and Grid Computing, CCGRID 2017

Schlagwörter: 46 Information and Computing Sciences (for-2020), 4603 Computer Vision and Multimedia Computation (for-2020)

Dateibeschreibung: application/pdf

Zugangs-URL: https://escholarship.org/uc/item/40d5t2hp
https://escholarship.org/content/qt40d5t2hp/qt40d5t2hp.pdf

Parallel fpga routing based on the operator formulation

Autoren: Moctar, Yehdhih Ouid Mohammed Brisk, Philip

Schlagwörter: Built Environment and Design, Architecture, Engineering, Electrical Engineering, Field Programmable Gate Array, Routing, Routing Resource Graph, Maze Expansion, Irregular Algorithm, Software Transactional Memory

Zugangs-URL: https://escholarship.org/uc/item/0jp9j4dj