Search Results - acm: c.: computer system organizacija/c.1: processor architectures/c.1.4: parallel architektury*
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1
Authors: Amenyo, John-Thones
Source: Journal of Educational Computing Research. 2012 47(4):351-370.
Peer Reviewed: Y
Page Count: 20
Descriptors: Educational Games, Computer Games, Computer Uses in Education, Programming, Information Science, Computer Science Education, Computer System Design, STEM Education, Professional Personnel, Training Methods, Instructional Materials, Educational Strategies, Computer Simulation, College Instruction
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Authors:
Source: ACM Transactions on Computing Education. Jan 2013 13(1).
Peer Reviewed: Y
Page Count: 12
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3
Authors:
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Subject Terms: peephole optimalizátor, peephole optimalizace, LLVM, backend, překladač, mikroprocesorová architektura, popis architektury, peephole optimizer, peephole optimization, compiler, microprocessor architecture, architecture description
File Description: text/html
Relation: MINISTR, M. Peephole optimalizátor pro konfigurovatelné architektury procesorů [online]. Brno: Vysoké učení technické v Brně. Fakulta informačních technologií. 2012.; 79137; http://hdl.handle.net/11012/52891
Availability: http://hdl.handle.net/11012/52891
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Authors: Feldman, Julian
Source: Communications of the ACM. 5(9)
Subject Terms: Information and Computing Sciences, Information Systems, Information and computing sciences
File Description: application/pdf
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5
Alternate Title: Wielordzeniowe i jednordzeniowe mikroprocesory Raspberry Pi. (Polish)
Authors:
Source: Przegląd Elektrotechniczny; 2023, Vol. 99 Issue 1, p38-43, 6p
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6
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Subject Terms: derivace, diferenciální rovnice, Taylorova řada, mikroprocesor, numerická integrace, pevná řádová čárka, pohyblivá řádová čárka, integrátor, řadič, boothův algoritmus, paralelní architektury, derivation, diferential equnation, Taylor series, mikroprocessor, numeric integration, fixed point, floating point, integrator, controller, Booth algorithm, parallel architectures
File Description: application/pdf; text/html
Relation: OPÁLKA, J. Automatické řízení výpočtu ve specializovaném výpočetním systému [online]. Brno: Vysoké učení technické v Brně. Fakulta informačních technologií. 2016.; 103587; http://hdl.handle.net/11012/69421
Availability: http://hdl.handle.net/11012/69421
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7
Authors:
Source: Scientific American. Oct 1987 257(4):66-74.
Peer Reviewed: N
Page Count: 9
Descriptors: Computer Software, Computers, Efficiency, Information Technology, Input Output, Input Output Devices, Problem Solving, Programing, Programing Languages, Science and Society, Systems Approach, Technological Advancement, Technology
Journal Code: CIJJAN1988
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8
Authors: Malik, Kshitiz
Source: ProQuest LLC. 2009Ph.D. Dissertation, University of Illinois at Urbana-Champaign.
Peer Reviewed: N
Page Count: 157
Descriptors: Computer System Design, Performance, Engineering
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9
Alternate Title: Analiza architektury akceleratora FPGA dla szybkiej statystycznej sieci splotowej w systemie rozpoznawania emocji w czasie rzeczywistym. (Polish)
Authors: et al.
Source: Przegląd Elektrotechniczny; 2021, Vol. 97 Issue 7, p132-134, 3p
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10
Authors: et al.
Source: ACM Transactions on Storage. 2(1)
Subject Terms: Affordable and Clean Energy, Data Format, Networking & Telecommunications
File Description: application/pdf
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11
Authors:
Source: Mathur, Kapil K. and S. Lennart Johnsson. Multiplication of Matrices of Arbitrary Shape on a Data Parallel Computer. Harvard Computer Science Group Technical Report TR-01-92.
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Authors: Ryan C. Bleile
Source: ProQuest LLC. 2021Ph.D. Dissertation, University of Oregon.
Peer Reviewed: N
Page Count: 200
Sponsoring Agency: US Department of Energy
Descriptors: Monte Carlo Methods, Computers, Computer Oriented Programs, Models, Algorithms, Data Collection, Computer Science, Client Server Architecture
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13
Authors:
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Subject Terms: matematická morfologie, morfologický filtr, obvodová implementace, algoritmus, FPGA, mathematical morphology, morphological filter, hardware implementation, algorithm
File Description: 157 s.; application/pdf
Relation: 36922; http://hdl.handle.net/11025/5152
Availability: http://hdl.handle.net/11025/5152
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14
Authors: 日本電気株式会社
Source: 39(4);1998・10
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Authors:
Contributors:
Subject Terms: TRIPS, Tera-op Reliable Intelligently Adaptive Processing System, EDGE, Explicit Data Graph Execution, procesorová architektura, paralelizmus, paralelní výpočty, polymorfní procesor, processor architecture, parallelism, parallel computation, polymorph processor
File Description: 1977663 bytes; application/pdf; application/octet-stream; text/plain; image/jpeg; downloadable_files_count: 5
Relation: OSD002; https://hdl.handle.net/10084/87594; S2724; KRU255_FEI_B2647_2612R025_2011
Availability: https://hdl.handle.net/10084/87594
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16
Authors:
Source: ACM Transactions on Mathematical Software. 46(4)
Subject Terms: Eigenvalues, parallel eigenvalue algorithms, self-consistent field, shift-invert spectrum slicing, math.NA, cs.DC, cs.NA, physics.comp-ph, Numerical & Computational Mathematics, Computation Theory and Mathematics, Information Systems
File Description: application/pdf
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17
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Subject Terms: Virtex-II Pro, transport triggered architectures, processor architectures, VLIW, přenosem spouštěné architektury, VHDL, COMBO6X, FPGA, architektury procesorů
File Description: application/pdf; text/html
Access URL: http://hdl.handle.net/11012/54028
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18
Authors:
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Subject Terms: přenosem spouštěné architektury, VLIW, architektury procesorů, VHDL, COMBO6X, FPGA, Virtex-II Pro, transport triggered architectures, processor architectures
File Description: application/pdf; text/html
Relation: MIKUŠEK, P. Implementace generického procesoru v FPGA [online]. Brno: Vysoké učení technické v Brně. Fakulta informačních technologií. .; 15302; http://hdl.handle.net/11012/54028
Availability: http://hdl.handle.net/11012/54028
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Source: ACM Sigplan Notices. 48(8)
Subject Terms: Information and Computing Sciences, Applied Computing, topological data analysis, feature extraction, merge tree computation, parallelization, hybrid parallelization approaches, Software Engineering
File Description: application/pdf
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20
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Subject Terms: scalar, RAM, superscalar, návrh, design, procesor, cache, subscalar, VHDL, superskalární, processor, subskalární, skalární
File Description: application/pdf; text/html
Access URL: http://hdl.handle.net/11012/54277
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