Search Results - acm: c.: computer system organizacija/c.1: processor architectures/c.1.4: parallel architecture~

L'architecture considérée sous le rapport de l'art, des moeurs et de la législation. Tome 1 / ; par C.-N. Ledoux. Tome premier, 1804

Authors: Ledoux, Claude-Nicolas, 1736-1806, Auteur du texte

Source: Bibliothèque nationale de France, département Réserve des livres rares, RES-V-25, 1804.

Relation: Notice d'ensemble : http://catalogue.bnf.fr/ark:/12148/cb30770251g; Notice d’oeuvre : http://catalogue.bnf.fr/ark:/12148/cb121212940; Notice du catalogue : http://catalogue.bnf.fr/ark:/12148/cb30770251g

Access URL: http://gallica.bnf.fr/ark:/12148/bpt6k1047050b

[Croquis de maisons et de détails d'architecture à Bourges] : [dessin] / [C. Meryon], 1852

Authors: Meryon, Charles, 1821-1868, Graveur

Source: Bibliothèque nationale de France, département Estampes et photographie, RESERVE FOL-B-6 (4), 1852.

Relation: Notice d'ensemble : http://catalogue.bnf.fr/ark:/12148/cb42129049v; Notice de recueil : http://catalogue.bnf.fr/ark:/12148/cb403476810; Appartient à : [Recueil. Oeuvre de Charles Meryon. Dessins]; Notice du catalogue : http://catalogue.bnf.fr/ark:/12148/cb42129049v

Access URL: http://gallica.bnf.fr/ark:/12148/btv1b550024734

Distributed Architecture for Resource Management in Large Scale Grids

Authors: Jeanvoine, Emmanuel Rilling, Louis Morin, Christine et al.

Contributors: Jeanvoine, Emmanuel Rilling, Louis Morin, Christine et al.

Source: https://inria.hal.science/inria-00001066 ; [Research Report] PI 1775, 2006, pp.13.

Subject Terms: Grid computing, distributed system, peer-to-peer overlay networks, resource allocation, self-healing \\ Grille de calcul, système distribué, réseaux logiques pair-à-pair, allocation de ressources, auto-réparation, ACM: C.: Computer Systems Organization/C.2: COMPUTER-COMMUNICATION NETWORKS/C.2.4: Distributed Systems, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.4: Parallel Architectures, [INFO.INFO-OH]Computer Science [cs]/Other [cs.OH]

Relation: Report N°: PI 1775

Availability: https://inria.hal.science/inria-00001066
https://inria.hal.science/inria-00001066v1/document
https://inria.hal.science/inria-00001066v1/file/PI-1775.pdf

Survey of Models and Architectures to Ensure Linked Data Access

Authors: Toure, Mahamadou Gandon, Fabien Guidedi, Kaladzavi et al.

Contributors: Toure, Mahamadou Gandon, Fabien Guidedi, Kaladzavi et al.

Source: https://inria.hal.science/hal-03956456 ; Inria & Université Côte d'Azur, CNRS, I3S. 2023, pp.23.

Subject Terms: Web of Data, Gossip protocol, graph replication, limited connectivity, semantic overlay, mobile contributor, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.4: Parallel Architectures/C.1.4.0: Distributed architectures, ACM: I.: Computing Methodologies/I.2: ARTIFICIAL INTELLIGENCE/I.2.4: Knowledge Representation Formalisms and Methods, [INFO.INFO-DS]Computer Science [cs]/Data Structures and Algorithms [cs.DS]

Availability: https://inria.hal.science/hal-03956456
https://inria.hal.science/hal-03956456v1/document
https://inria.hal.science/hal-03956456v1/file/MahamadouToureSurvey.pdf

Software Abstractions for Parallel Architectures ; Abstractions Logicielles pour Architectures Parallèles

Authors: Falcou, Joel Systèmes parallèles (LRI) (ParSys - LRI) Laboratoire de Recherche en Informatique (LRI) et al.

Contributors: Falcou, Joel Systèmes parallèles (LRI) (ParSys - LRI) Laboratoire de Recherche en Informatique (LRI) et al.

Source: https://inria.hal.science/tel-01111708 ; Distributed, Parallel, and Cluster Computing [cs.DC]. Universite de Paris 11, 2014.

Subject Terms: parallel programming, generic programming, generative programming, meta-programming, parallel skeletons, programmation parallèle, méta-programmation, programmation générative, programmation générique, squelettes parallèles, ACM: D.: Software/D.2: SOFTWARE ENGINEERING, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.4: Parallel Architectures, [INFO.INFO-DC]Computer Science [cs]/Distributed, Parallel, and Cluster Computing [cs.DC]

Availability: https://inria.hal.science/tel-01111708
https://inria.hal.science/tel-01111708v1/document
https://inria.hal.science/tel-01111708v1/file/Thesis.pdf

De l'architecture des forteresses, ou De l'art de fortifier les places, et de disposer les établissemens de tout genre, qui ont rapport à la guerre . Premiere partie. Essai sur la fortification... par C. F. Mandar.., 1801

Authors: Mandar, Charles François, 1757-1844, Auteur du texte

Source: Bibliothèque nationale de France, département Littérature et art, V-22465, 1801.

Relation: Notice du catalogue : http://catalogue.bnf.fr/ark:/12148/cb30870419q

Access URL: http://gallica.bnf.fr/ark:/12148/bpt6k9640257v

Notice sur la vie et les travaux du C. Antoine, architecte de l'ancienne Académie d'architecture, de la Société des sciences, lettres et arts de Paris, et membre de l'Institut national de France, lue dans la séance publique de l'Institut, du 8 vendémiaire an 12, par Joachim le Breton, secrétaire perpetuel de la classe des beaux-arts, et membre de celle d'histoire et de littérature ancienne, 1803

Source: Bibliothèque nationale de France, département Estampes et photographie, RESERVE 8-YA3-27 (50, 1396), 1803.

Relation: Notice de recueil : http://catalogue.bnf.fr/ark:/12148/cb44343928z; Appartient à : Collection Deloynes. Tome 50, pièces 1336 à 1396, Supplément au Tome V; Notice du catalogue : http://catalogue.bnf.fr/ark:/12148/cb443480249

Access URL: http://gallica.bnf.fr/ark:/12148/btv1b10537578r

Parameter Exploration to Improve Performance of Memristor-Based Neuromorphic Architectures

Authors: Mahyar Shahsavari Pierre Boulet Boulet, Pierre et al.

Contributors: Mahyar Shahsavari Pierre Boulet Boulet, Pierre et al.

Source: IEEE Transactions on Multi-Scale Computing Systems. 4:833-846

Subject Terms: [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], Neuromorphic Computing, 0301 basic medicine, [INFO.INFO-DC]Computer Science [cs]/Distributed, [INFO.INFO-AR] Computer Science [cs]/Hardware Architecture [cs.AR], ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.3: Other Architecture Styles/C.1.3.7: Neural nets, [INFO.INFO-NE] Computer Science [cs]/Neural and Evolutionary Computing [cs.NE], Unsupervised Learning, 02 engineering and technology, [INFO.INFO-NE]Computer Science [cs]/Neural and Evolutionary Computing [cs.NE], Memristor, Parallel, [INFO.INFO-ES] Computer Science [cs]/Embedded Systems, Spiking Neural Networks, 03 medical and health sciences, and Cluster Computing [cs.DC], Parameter Evaluations, [INFO.INFO-ET] Computer Science [cs]/Emerging Technologies [cs.ET], [INFO.INFO-DC] Computer Science [cs]/Distributed, Parallel, and Cluster Computing [cs.DC], 0202 electrical engineering, electronic engineering, information engineering, [INFO.INFO-ES]Computer Science [cs]/Embedded Systems, [INFO.INFO-ET]Computer Science [cs]/Emerging Technologies [cs.ET]

File Description: application/pdf

Access URL: https://hal.archives-ouvertes.fr/hal-01615032/file/TMSCSSI-2016-10-0051.R1-main.pdf
https://ieeexplore.ieee.org/document/8063353
https://hal.archives-ouvertes.fr/hal-01615032/document
https://jglobal.jst.go.jp/en/detail?JGLOBAL_ID=201902258056300336
https://dblp.uni-trier.de/db/journals/tmscs/tmscs4.html#ShahsavariB18
https://hal.archives-ouvertes.fr/hal-01615032
https://hal.science/hal-01615032v1/document
https://hal.science/hal-01615032v1
https://doi.org/10.1109/tmscs.2017.2761231

Towards a New Processor Architecture. ; Vers une nouvelle Architecture de Processeurs

Authors: Vincent, Pierre Landru, Jacques Ecole nationale supérieure Mines-Télécom Lille Douai (IMT Nord Europe) et al.

Contributors: Vincent, Pierre Landru, Jacques Ecole nationale supérieure Mines-Télécom Lille Douai (IMT Nord Europe) et al.

Source: https://hal.science/hal-05117313 ; 2025.

Subject Terms: silicon, parallel, serial, RISC, photonics, computer, optronics, optics, processor, fiber, laser, digital, silicium, parallèle, série, processeur, photonique, ordinateur, optronique, optique, numérique, fibre, ACM: B.: Hardware, ACM: C.: Computer Systems Organization, [INFO]Computer Science [cs], [PHYS]Physics [physics]

Availability: https://hal.science/hal-05117313
https://hal.science/hal-05117313v2/document
https://hal.science/hal-05117313v2/file/frParalSerieRiscV1.pdf

HARS: A Hardware-Assisted Runtime Software for embedded many-core architectures

Authors: Lhuillier, Y. Ojail, M. Guerre, A. et al.

Contributors: Lhuillier, Y. Ojail, M. Guerre, A. et al.

Source: ISSN: 1539-9087.

Subject Terms: B.5.0 [Register-Transfer-Level Implementation]: General, ACM: D.: Software/D.4: OPERATING SYSTEMS/D.4.7: Organization and Design/D.4.7.4: Real-time systems and embedded systems, ACM: D.: Software/D.4: OPERATING SYSTEMS/D.4.1: Process Management, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.4: Parallel Architectures, ACM: B.: Hardware/B.5: REGISTER-TRANSFER-LEVEL IMPLEMENTATION, [INFO]Computer Science [cs]

Availability: https://cea.hal.science/cea-01818892
https://doi.org/10.1145/2517311

EEA-Aware For Large-Scale Scientific Applications On Heterogeneous Architectures

Authors: Garcia Henao, John Anderson, John Anderson Garcia Henao Hernandez, Esteban Navaux, Philippe, O.A. et al.

Contributors: Garcia Henao, John Anderson, John Anderson Garcia Henao Hernandez, Esteban Navaux, Philippe, O.A. et al.

Source: ACM Student Research Competition at Supercomputing. The International Conference for High Performance Computing, Networking, Storage and Analysis ; https://hal.science/hal-01739585 ; ACM Student Research Competition at Supercomputing. The International Conference for High Performance Computing, Networking, Storage and Analysis, Nov 2016, Salt Lake City, Utah, United States

Subject Terms: Exascale Computing, Energy Aware, Power Capping, Energy Efficiency, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.4: Parallel Architectures, ACM: D.: Software/D.4: OPERATING SYSTEMS/D.4.8: Performance/D.4.8.2: Monitors, ACM: D.: Software/D.4: OPERATING SYSTEMS/D.4.8: Performance/D.4.8.1: Modeling and prediction, [INFO.INFO-DC]Computer Science [cs]/Distributed, Parallel, and Cluster Computing [cs.DC]

Subject Geographic: Salt Lake City, Utah, United States

Availability: https://hal.science/hal-01739585
https://hal.science/hal-01739585v1/document
https://hal.science/hal-01739585v1/file/01_EEAaware-SC16-JAGH-poster.pdf

A Processor Architecture with Effective Memory System for Sort-Last Parallel Rendering

Authors: Park, Woo-Chan Yoon, Duk-Ki Lee, Kil-Whan et al.

Source: Lecture Notes in Computer Science ; Architecture of Computing Systems - ARCS 2006 ; page 160-175 ; ISSN 0302-9743 1611-3349 ; ISBN 9783540327653 9783540327660

Availability: https://doi.org/10.1007/11682127_12
http://link.springer.com/content/pdf/10.1007/11682127_12

Embedded Runtime for Reconfigurable Dataflow Graphs on Manycore Architectures

Authors: Miomandre, Hugo Hascoët, Julien Desnos, Karol et al.

Contributors: Miomandre, Hugo Hascoët, Julien Desnos, Karol et al.

Source: PARMA-DITAM ; https://hal.science/hal-01704702 ; PARMA-DITAM, Jan 2018, Manchester, United Kingdom. ⟨10.1145/3183767.3183780⟩

Subject Terms: ACM: C.: Computer Systems Organization, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.4: Parallel Architectures, [INFO.INFO-ES]Computer Science [cs]/Embedded Systems

Subject Geographic: Manchester, United Kingdom

Availability: https://hal.science/hal-01704702
https://hal.science/hal-01704702v1/document
https://hal.science/hal-01704702v1/file/parma-ditam18.pdf
https://doi.org/10.1145/3183767.3183780

Architecture Studies and System Demonstrations of Optical Parallel Processor for AI and NI

Authors: Lee, Sing H. Esener, Sadik C. CALIFORNIA UNIV SAN DIEGO LA JOLLA DEPT OF ELECTRICAL AND COMPUTER ENGINEERING

Contributors: Lee, Sing H. Esener, Sadik C. CALIFORNIA UNIV SAN DIEGO LA JOLLA DEPT OF ELECTRICAL AND COMPUTER ENGINEERING

Source: DTIC AND NTIS

Subject Terms: Electrooptical and Optoelectronic Devices, Computer Hardware, COMPUTER ARCHITECTURE, MULTIPROCESSORS, PARALLEL PROCESSORS, OPTICAL PROCESSING, ELECTROOPTICS, COMPUTER PROGRAMMING, NERVOUS SYSTEM, ARTIFICIAL INTELLIGENCE, DEMONSTRATIONS, ARCHITECTURE, INTELLIGENCE, OPTICAL EQUIPMENT, ALGORITHMS, PROTOTYPES

File Description: text/html

Relation: http://www.dtic.mil/docs/citations/ADA244170

Availability: http://www.dtic.mil/docs/citations/ADA244170
http://oai.dtic.mil/oai/oai?&verb=getRecord&metadataPrefix=html&identifier=ADA244170

Covariance tracking: architecture optimizations for embedded systems

Authors: Romero, Andrés Lacassagne, Lionel Gouiffès, Michèle et al.

Contributors: Romero, Andrés Lacassagne, Lionel Gouiffès, Michèle et al.

Source: ISSN: 1687-6172.

Subject Terms: covariance-tracking, real-time image processing, SIMD, SSE, AVX, Neon, ACM: I.: Computing Methodologies/I.4: IMAGE PROCESSING AND COMPUTER VISION/I.4.8: Scene Analysis/I.4.8.2: Motion, ACM: I.: Computing Methodologies/I.4: IMAGE PROCESSING AND COMPUTER VISION/I.4.8: Scene Analysis/I.4.8.12: Tracking, ACM: I.: Computing Methodologies/I.4: IMAGE PROCESSING AND COMPUTER VISION/I.4.7: Feature Measurement/I.4.7.1: Invariants, ACM: I.: Computing Methodologies/I.4: IMAGE PROCESSING AND COMPUTER VISION/I.4.7: Feature Measurement/I.4.7.2: Moments, ACM: I.: Computing Methodologies/I.4: IMAGE PROCESSING AND COMPUTER VISION/I.4.7: Feature Measurement/I.4.7.5: Texture, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.4: Parallel Architectures/C.1.4.1: Mobile processors, ACM: D.: Software/D.3: PROGRAMMING LANGUAGES/D.3.4: Processors/D.3.4.6: Optimization, [INFO.INFO-DS]Computer Science [cs]/Data Structures and Algorithms [cs.DS], [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [SPI.AUTO]Engineering Sciences [physics]/Automatic, [SPI.SIGNAL]Engineering Sciences [physics]/Signal and Image processing, [INFO.INFO-AO]Computer Science [cs]/Computer Arithmetic, [INFO.INFO-DC]Computer Science [cs]/Distributed, Parallel, and Cluster Computing [cs.DC], [INFO.INFO-SE]Computer Science [cs]/Software Engineering [cs.SE], [INFO.INFO-DM]Computer Science [cs]/Discrete Mathematics [cs.DM], [INFO.INFO-RB]Computer Science [cs]/Robotics [cs.RO], [INFO.INFO-TI]Computer Science [cs]/Image Processing [eess.IV], [INFO.INFO-TS]Computer Science [cs]/Signal and Image Processing, [INFO.INFO-CV]Computer Science [cs]/Computer Vision and Pattern Recognition [cs.CV]

Availability: https://inria.hal.science/hal-01094903
https://inria.hal.science/hal-01094903v1/document
https://inria.hal.science/hal-01094903v1/file/Eurasip%202014-12.pdf
https://doi.org/10.1186/1687-6180-2014-175

A Parallel CNC System Architecture Based on Symmetric Multi-processor

Authors: Fu, Hongya Li, Cong Fu, Yunzhong

Source: 2016 Sixth International Conference on Instrumentation & Measurement, Computer, Communication and Control (IMCCC) ; page 634-637

Availability: https://doi.org/10.1109/imccc.2016.74
http://xplorestaging.ieee.org/ielx7/7774238/7774713/07774859.pdf?arnumber=7774859

Parallel image processing system-a modular architecture using dedicated image processing modules and a graphics processor

Authors: Rahman, S. Clarkson, T.G.

Source: IEEE TENCON'90: 1990 IEEE Region 10 Conference on Computer and Communication Systems. Conference Proceedings ; page 319-323

Availability: https://doi.org/10.1109/tencon.1990.152624
http://xplorestaging.ieee.org/ielx5/498/3989/00152624.pdf?arnumber=152624

Exploring Processor and Memory Architectures for Multimedia

Authors: Iranpour, Ali Lund University, Faculty of Engineering, LTH, Departments at LTH, Department of Computer Science, Parallel Systems, Lunds universitet, Lunds Tekniska Högskola, Institutioner vid LTH, Institutionen för datavetenskap, Parallella System, Originator Lund University, Faculty of Engineering, LTH, Departments at LTH, Department of Computer Science, Lunds universitet, Lunds Tekniska Högskola, Institutioner vid LTH, Institutionen för datavetenskap, Originator et al.

Contributors: Iranpour, Ali Lund University, Faculty of Engineering, LTH, Departments at LTH, Department of Computer Science, Parallel Systems, Lunds universitet, Lunds Tekniska Högskola, Institutioner vid LTH, Institutionen för datavetenskap, Parallella System, Originator Lund University, Faculty of Engineering, LTH, Departments at LTH, Department of Computer Science, Lunds universitet, Lunds Tekniska Högskola, Institutioner vid LTH, Institutionen för datavetenskap, Originator et al.

Subject Terms: Natural Sciences, Computer and Information Sciences, Computer Sciences, Naturvetenskap, Data- och informationsvetenskap (Datateknik), Datavetenskap (Datalogi)

File Description: electronic

Access URL: https://lucris.lub.lu.se/ws/files/5380095/2270093.pdf

6.823 Computer System Architecture, Spring 2002 ; Computer System Architecture

Authors: Asanovic, Krste Arvind, V. Devadas, Srinivas et al.

Contributors: Asanovic, Krste Arvind, V. Devadas, Srinivas et al.

Subject Terms: computer architecture, computer system architecture, hardware, hardware design, software, software design, instruction set design, processor micro-architecture, pipelining, cache memory, virtual memory, I/O, input/output, interrupts, superscalar architectures, VLIW machines, vector supercomputers, multithreaded architectures, symmetric multiprocessors, parallel computers

Subject Geographic: Spring 2002

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Relation: local: 6.823; http://hdl.handle.net/1721.1/35849

Availability: http://hdl.handle.net/1721.1/35849

Parallel LDPC Decoding on the Cell/B.E. Processor

Authors: Falcão, Gabriel Sousa, Leonel Silva, Vitor et al.

Contributors: Falcão, Gabriel Sousa, Leonel Silva, Vitor et al.

Source: HiPEAC 2009 - High Performance and Embedded Architectures and Compilers ; https://hal.inria.fr/inria-00446368 ; HiPEAC 2009 - High Performance and Embedded Architectures and Compilers, Jan 2009, Paphos, Cyprus. ⟨10.1007/978-3-540-92990-1_28⟩

Subject Terms: ACM: B.: Hardware/B.2: ARITHMETIC AND LOGIC STRUCTURES, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES, ACM: D.: Software/D.3: PROGRAMMING LANGUAGES/D.3.4: Processors, [INFO.INFO-OH]Computer Science [cs]/Other [cs.OH], [INFO.INFO-ES]Computer Science [cs]/Embedded Systems

Subject Geographic: Paphos, Cyprus

Relation: inria-00446368; https://hal.inria.fr/inria-00446368

Availability: https://hal.inria.fr/inria-00446368
https://doi.org/10.1007/978-3-540-92990-1_28