Search Results - acm: c.: computer system organizacija/c.1: processor architecture/c.1.4: parallel architecture*

An FPGA-based integrated environment for computer architecture.

Authors: Bulić, Patricio Guštin, Veselko Šonc, Damjan et al.

Source: Computer Applications in Engineering Education; Mar2013, Vol. 21 Issue 1, p26-35, 10p, 3 Color Photographs, 6 Diagrams

Subject Terms: FIELD programmable gate arrays, COMPUTER architecture, RISC microprocessors, DEBUGGING, COMPUTER organization, VHDL (Computer hardware description language), EDUCATION

Građa računala, arhitektura i organizacija računarskih sustava

Authors: Ribarić, Slobodan

Subject Terms: superskalarni procesori, GPU, organizacija računala, građa računala, arhitektura računarskih sustava, višeprocesorski SIMD i MIMD sustavi, višeprocesorski i paralelni sustavi, simultano višedretvene arhitekture procesora, višejezgreni procesori, multiprocesorske grafičke jedinice, multiprocessor and parallel systems, computer system architecture, computer architecture, parallel computer systems, multicore processors, grafički procesori, structure of a computer, arhitektura računala, multiprocessor graphics processing units, computer organization, simultaneous višedretvene architecture processors, SIMD and MIMD multiprocessor systems, multi-core processors, superscalar processors, paralelni računarski sustavi

Access URL: https://www.bib.irb.hr/566837

REALIZACIJA NASTAVE NA DALJINU IZ PREDMETA ARHITEKTURA I ORGANIZACIJA RAČUNARA PRIMENOM MOODLE OKRUŽENJA. (Bosnian)

Alternate Title: THE IMPLEMENTATION OF DISTANCE LEARNING IN THE SUBJECT COMPUTER ARCHITECTURE AND ORGANIZATION USING THE MOODLE ENVIRONMENT. (English)

Authors: Prokin, Dragana Dimić, Gabrijela Mićić, Divna

Source: Singidunum Journal of Applied Sciences; 2014 Supplement, p462-467, 6p

Procesor grafov ; A Graph Processor

Authors: Nedanovski, Tilen Bulić, Patricio

Contributors: Nedanovski, Tilen Bulić, Patricio

Subject Terms: računalniška arhitektura, računalniška organizacija, procesor, graf, computer architecture, computer organisation, processor, graph

File Description: application/pdf

Availability: https://repozitorij.uni-lj.si/IzpisGradiva.php?id=95089
https://repozitorij.uni-lj.si/Dokument.php?id=103616&dn=
https://hdl.handle.net/20.500.12556/RUL-95089

Evaluation of the Use of an Associative Processor in Communication Multiplexing.

Authors: HONEYWELL INC MINNEAPOLIS MINN SYSTEMS AND RESEARCH DIV Wald,L. D. Armstrong,T. R. et al.

Source: DTIC AND NTIS

Index Terms: Computer Programming and Software, Computer Hardware, Voice Communications, DATA PROCESSING, VOICE COMMUNICATIONS, ALGORITHMS, COMPUTER PROGRAMMING, MULTIPLEXING, INPUT OUTPUT DEVICES, SPEECH COMPRESSION., Text

URL: https://apps.dtic.mil/docs/citations/AD0758246

Uporaba heterogenih računalniških sistemov za molekulsko sidranje. (Slovenian)

Alternate Title: Employing heterogeneous computer systems for molecular docking. (English)

Authors: Sluga, Davor Erent, Tine Jukić, Marko et al.

Source: Electrotechnical Review / Elektrotehniski Vestnik; 2023, Vol. 90 Issue 1/2, p60-68, 9p

Subject Terms: COMPUTER architecture, SOFTWARE frameworks, PARALLEL algorithms, MOLECULAR docking, PROTEIN receptors, SUPERCOMPUTERS, POSE estimation (Computer vision)

Scientific Programming and Computer Architecture

Authors: Viswanath, Divakar

Subject Terms: C, C++, programming languages, processor, memory, network, high performance computing, computer science, engineering, super computing, Mobile and handheld device programming / Apps programming, Computer science, Information architecture

File Description: application/pdf

Relation: Scientific and Engineering Computation

Access URL: http://library.oapen.org/handle/20.500.12657/26041

A Novel Reconfigurable Architecture of a DSP Processor for Efficient Mapping of DSP Functions using Field Programmable DSP Arrays

Authors: Sinha, Amitabha Sarkar, Mitrava Acharyya, Soumojit et al.

Index Terms: Computer Science - Hardware Architecture, 68R01, text

URL: http://arxiv.org/abs/1306.0089

TALL—a list processor for the Philco 2000 computer

Authors: Feldman, Julian

Source: Communications of the ACM. 5(9)

Subject Terms: Information and Computing Sciences, Information Systems, Information and computing sciences

File Description: application/pdf

Access URL: https://escholarship.org/uc/item/6qk36727
https://escholarship.org/content/qt6qk36727/qt6qk36727.pdf

Hardware Architecture for Large Parallel Array of Random Feature Extractors applied to Image Recognition

Authors: Patil, Aakash Shen, Shanlan Yao, Enyi et al.

Index Terms: Computer Science - Emerging Technologies, Computer Science - Neural and Evolutionary Computing, C.3, C.5.4, I.5.5, text

URL: http://arxiv.org/abs/1512.07783

Scalable Architecture for a Room Temperature Solid-State Quantum Information Processor

Authors: Yao, Norman Jiang, Liang Gorshkov, Alexey et al.

Source: Yao, Norman Y., Liang Jiang, Alexey V. Gorshkov, Peter C. Maurer, Geza Giedke, J. Ignacio Cirac, Mikhail D. Lukin. 2012. Scalable architecture for a room temperature solid-state quantum information processor. Nature Communications 3(4): 800.

Subject Terms: physical sciences, atomic and molecular physics, nuclear-spin qubits, coupled electron, diamond, nitrogen, entanglement, spectroscopy, manipulation, computation, resolution, particles

File Description: application/pdf

Relation: http://arxiv.org/abs/1012.2864v1; Nature Communications

Access URL: http://nrs.harvard.edu/urn-3:HUL.InstRepos:8951184

Decision support in productive processes through DES and ABS in the Digital Twin era: a systematic literature review.

Authors: dos Santos, Carlos Henrique Montevechi, José Arnaldo Barra de Queiroz, José Antônio et al.

Source: International Journal of Production Research; Apr2022, Vol. 60 Issue 8, p2662-2681, 20p, 4 Diagrams, 3 Charts, 6 Graphs

Subject Terms: DISCRETE event simulation, DIGITAL computer simulation

A system architecture, processor, and communication protocol for secure implants

Authors: Strydis, Christos Seepers, Robert M. Peris-Lopez, Pedro et al.

Source: Strydis, C, Seepers, R M, Peris-Lopez, P, Siskos, D & Sourdis, I 2013, 'A system architecture, processor, and communication protocol for secure implants', ACM Transactions on Architecture and Code Optimization, vol. 10, no. 4, 57, pp. 1-23.

Index Terms: article

URL: https://pure.eur.nl/en/publications/fe980374-12db-4440-9565-3f31c8e892c8

Arhitektura RISC procesora ; RISC processor architecture

Authors: Rupčić, Leo Magdalenić, Ivan

Contributors: Rupčić, Leo Magdalenić, Ivan

Subject Terms: DRUŠTVENE ZNANOSTI. Informacijske i komunikacijske znanosti. Organizacija i informatika, SOCIAL SCIENCES. Information and Communication Sciences. Organization and Informatics, ahitektura, procesor, risc

File Description: application/pdf

Relation: https://zir.nsk.hr/islandora/object/foi:1266; https://urn.nsk.hr/urn:nbn:hr:211:196624; https://repozitorij.unizg.hr/islandora/object/foi:1266; https://repozitorij.unizg.hr/islandora/object/foi:1266/datastream/PDF

Availability: https://zir.nsk.hr/islandora/object/foi:1266
https://urn.nsk.hr/urn:nbn:hr:211:196624
https://repozitorij.unizg.hr/islandora/object/foi:1266
https://repozitorij.unizg.hr/islandora/object/foi:1266/datastream/PDF

CVC Verilog Compiler -- Fast Complex Language Compilers Can be Simple

Authors: Meyer, Steven

Index Terms: Computer Science - Programming Languages, D.3.4, B.6.3, text

URL: http://arxiv.org/abs/1603.08059

Parallel fpga routing based on the operator formulation

Authors: Moctar, Yehdhih Ouid Mohammed Brisk, Philip

Subject Terms: Built Environment and Design, Architecture, Engineering, Electrical Engineering, Field Programmable Gate Array, Routing, Routing Resource Graph, Maze Expansion, Irregular Algorithm, Software Transactional Memory

Access URL: https://escholarship.org/uc/item/0jp9j4dj

Scaling Deep Learning Computation over the Inter-Core Connected Intelligence Processor with T10

Authors: Liu, Yiqi Xue, Yuqi Cheng, Yu et al.

Index Terms: Computer Science - Distributed, Parallel, and Cluster Computing, Computer Science - Machine Learning, text

URL: http://arxiv.org/abs/2408.04808

Security requirement analysis of business processes.

Authors: Herrmann, Peter Herrmann, Gaby

Source: Electronic Commerce Research; Jul2006, Vol. 6 Issue 3/4, p305-335, 31p, 11 Diagrams, 2 Charts

Subject Terms: SECURITY systems, SECURITY management, INFORMATION technology, BUSINESS enterprise security, ELECTRONIC systems, INDUSTRIAL management

Multiplication of Matrices of Arbitrary Shape on a Data Parallel Computer

Authors: Mathur, Kapil K. Johnsson, S. Lennart

Source: Mathur, Kapil K. and S. Lennart Johnsson. Multiplication of Matrices of Arbitrary Shape on a Data Parallel Computer. Harvard Computer Science Group Technical Report TR-01-92.

Access URL: http://nrs.harvard.edu/urn-3:HUL.InstRepos:23017262

Classification-design-optimization integrated picking robots: a review.

Authors: Xiang, Jingyang Wang, Lianguo Li, Li et al.

Source: Journal of Intelligent Manufacturing; Oct2024, Vol. 35 Issue 7, p2979-3002, 24p

Subject Terms: ENERGY consumption, ROBOT design & construction, ROBOTS, KINEMATICS, RESEARCH & development, ORDER picking systems