Search Results - acm: c.: computer system organizacie/c.1: processor architectural/c.1.4: parallel architectural~

Parallel Computation for Distributed Parameter System form Vector Processor to ADENA Computer / 分布定数系の並列演算

Authors: Tatsuo NOGI 野木 達夫

Source: 計測と制御 / Journal of The Society of Instrument and Control Engineers. 1983, 22(4):340

Architectural requirements for a multipurpose natural language processor in the clinical environment.

Authors: Friedman C Johnson SB Forman B et al.

Source: Proceedings. Symposium on Computer Applications in Medical Care [Proc Annu Symp Comput Appl Med Care] 1995, pp. 347-51.

Publication Type: Journal Article; Research Support, Non-U.S. Gov't; Research Support, U.S. Gov't, P.H.S.

Journal Info: Publisher: American Medical Informatics Association (Amia) Country of Publication: United States NLM ID: 8113685 Publication Model: Print Cited Medium: Print ISSN: 0195-4210 (Print) Linking ISSN: 01954210 NLM ISO Abbreviation: Proc Annu Symp Comput Appl Med Care Subsets: MEDLINE

MeSH Terms: Computer Systems* , Natural Language Processing*, Hospital Information Systems ; Radiology Information Systems

A Survey of Techniques for Architecting and Managing Asymmetric Multicore Processors.

Authors: MITTAL, SPARSH¹ (AUTHOR) mittals@ornl.gov

Source: ACM Computing Surveys. Feb2016, Vol. 48 Issue 3, p45:1-45:38. 38p. 2 Diagrams, 6 Charts.

Subject Terms: *MULTICORE processors, *COMPUTER architecture, *COMPUTER systems, *PARALLEL processing, *HETEROGENEITY, *AMDAHL'S law, *VIRTUAL machine systems

Architectural Support for Efficient Data Movement in Disaggregated Systems

Authors: Giannoula, Christina Huang, Kailong Tang, Jonathan et al.

Index Terms: Computer Science - Hardware Architecture, Computer Science - Distributed, Parallel, and Cluster Computing, Computer Science - Performance, text

URL: http://arxiv.org/abs/2301.09674

DaeMon: Architectural Support for Efficient Data Movement in Disaggregated Systems

Authors: Giannoula, Christina Huang, Kailong Tang, Jonathan et al.

Index Terms: Computer Science - Hardware Architecture, Computer Science - Distributed, Parallel, and Cluster Computing, Computer Science - Performance, text

URL: http://arxiv.org/abs/2301.00414

Efficient parallel architecture for highly coupled real-time linear system applications

Authors: Carroll, Chester C Homaifar, Abdollah Barua, Soumavo

Subject Terms: Computer Operations And Hardware

Access URL: https://ntrs.nasa.gov/citations/19880010631

Exploring Processor and Memory Architectures for Multimedia

Authors: Iranpour, Ali Lund University, Faculty of Engineering, LTH, Departments at LTH, Department of Computer Science, Parallel Systems, Lunds universitet, Lunds Tekniska Högskola, Institutioner vid LTH, Institutionen för datavetenskap, Parallella System, Originator Lund University, Faculty of Engineering, LTH, Departments at LTH, Department of Computer Science, Lunds universitet, Lunds Tekniska Högskola, Institutioner vid LTH, Institutionen för datavetenskap, Originator et al.

Contributors: Iranpour, Ali Lund University, Faculty of Engineering, LTH, Departments at LTH, Department of Computer Science, Parallel Systems, Lunds universitet, Lunds Tekniska Högskola, Institutioner vid LTH, Institutionen för datavetenskap, Parallella System, Originator Lund University, Faculty of Engineering, LTH, Departments at LTH, Department of Computer Science, Lunds universitet, Lunds Tekniska Högskola, Institutioner vid LTH, Institutionen för datavetenskap, Originator et al.

Subject Terms: Natural Sciences, Computer and Information Sciences, Computer Sciences, Naturvetenskap, Data- och informationsvetenskap (Datateknik), Datavetenskap (Datalogi)

File Description: electronic

Access URL: https://lucris.lub.lu.se/ws/files/5380095/2270093.pdf

A processor array module for distributed, massively parallel, embedded computing

Authors: Bengtsson, Lars Nilsson, Kenneth Svensson, Bertil

Source: Microprocessing and Microprogramming. 38(1-5):529-537

Subject Terms: Parallel Processing, Distributed Embedded Systems, Massive Parallelism, Learning Systems, Real-time Computer Systems, Optical Communication

File Description: print

Access URL: https://urn.kb.se/resolve?urn=urn:nbn:se:hh:diva-18833

An Evaluation of Architectural Platforms for Parallel Navier-Stokes Computations

Authors: Jayasimha, D. N Hayder, M. E Pillay, S. K

Subject Terms: Computer Programming And Software

Access URL: https://ntrs.nasa.gov/citations/19960022703

Soylent: a word processor with a crowd inside

Authors: Massachusetts Institute of Technology. Computer Science and Artificial Intelligence Laboratory Bernstein, Michael S Little, Greg et al.

Source: MIT web domain

Index Terms: Article, http://purl.org/eprint/type/ConferencePaper

URL: https://hdl.handle.net/1721.1/134275
10.1145/2791285
Communications of the ACM

Quantitative Analysis of Coat-color Patterns in BALB/c ⇔ C57BL/6 Mouse Chimeras by Means of a Computer-Based Color Image Processor System

Authors: Jutaro TAKAHASHI Sang-Yong KIM Yasuhisa YASUDA et al.

Source: Journal of Reproduction and Development. 1995, 41(1):47

Architectural support for efficient on-chip parallel execution

Authors: Brown, Jeffery Alan

Subject Terms: UCSD Dissertations, Academic Computer science. (Discipline)

File Description: application/pdf

Access URL: https://escholarship.org/uc/item/0r1593xh
https://escholarship.org/content/qt0r1593xh/qt0r1593xh.pdf

Swarm Processor System: hardware process scheduler based energy efficient multi-core system

Authors: Sang-Min Lee Seung Hun Kim Won Seob Jeong et al.

Source: IEICE Electronics Express. 2014, 11(14):20140424

Confidential computing for population-scale genome-wide association studies with SECRET-GWAS.

Authors: Rosenblum J Dong J Narayanasamy S

Source: Nature computational science [Nat Comput Sci] 2025 Sep; Vol. 5 (9), pp. 825-835. Date of Electronic Publication: 2025 Sep 12.

Publication Type: Journal Article

Journal Info: Publisher: Springer Nature Country of Publication: United States NLM ID: 101775476 Publication Model: Print-Electronic Cited Medium: Internet ISSN: 2662-8457 (Electronic) Linking ISSN: 26628457 NLM ISO Abbreviation: Nat Comput Sci Subsets: MEDLINE

MeSH Terms: Genome-Wide Association Study*/methods , Computer Security* , Confidentiality*, Humans ; Logistic Models ; Algorithms ; Software ; Genomics

Efficient Reuse Distance Analysis of Multicore Scaling for Loop-Based Parallel Programs.

Authors: MENG-JU WU DONALD YEUNG

Source: ACM Transactions on Computer Systems. Feb2013, Vol. 31 Issue 1, p1:1-1:37. 37p.

Subject Terms: *PARALLEL programming, *MULTICORE processors, *CACHE memory, *LOOPS (Group theory), *COMPUTER storage devices, *COMPUTER memory management

An Overview of Parallel Processors and Processing.

Authors: Tse-Yun Feng¹

Source: ACM Computing Surveys. Mar77, Vol. 9 Issue 1, p1-2. 2p.

Subject Terms: *MULTIPROCESSORS, *COMPUTER architecture, *PARALLEL processing, *DATA pipelining, *COMPUTERS, *LARGE scale integration of circuits

Reviews & Products: ACM Computing Surveys (Periodical)

Automatic design of application-specific reconfigurable processor extensions with UPaK synthesis kernel

Authors: Wolinski, Christophe Kuchcinski, Krzysztof Raffin, Erwan et al.

Contributors: Wolinski, Christophe Kuchcinski, Krzysztof Raffin, Erwan et al.

Source: ACM Transactions on Design Automation of Electronic Systems. 15(1)

Subject Terms: Natural Sciences, Computer and Information Sciences, Computer Sciences, Naturvetenskap, Data- och informationsvetenskap (Datateknik), Datavetenskap (Datalogi)

Convolutional Decoding on Deep-pipelined SIMD Processor with Flexible Parallel Memory

Authors: Wang, Jian Karlsson, Andréas Sohl, Joar et al.

Source: ePUMA Digital System Design (DSD), 2012. :529-532

Subject Terms: convolutional codes, decoding, parallel processing, random-access storage, CEVA TeakLike III, PowerPC AltiVec, TI C54x, VLIW architecture, assembly programming, communication signal processing, compiler design, conflict free parallel data access, convolutional decoding, deep-pipelined SIMD processor, ePUMA1 platform, flexible parallel memory, media signal processing, memory access latency, parallel processor architecture, pipeline parallel memory, short vector SIMD machine, single instruction multiple data architecture, soft decision Viterbi algorithm, vector data permutation limit, vector permutation instruction, Computer architecture, Convolution, Convolutional codes, Decoding, Measurement, Vectors, Viterbi algorithm, Convolutional decoding, Parallel memory, SIMD, Viterbi, ePUMA

File Description: print

Access URL: https://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-100380

MBASIC batch processor architectural overview

Authors: Reynolds, S. M

Source: The Deep Space Network.

Subject Terms: Computer Operations And Hardware

Relation: The deep space network

Access URL: https://ntrs.nasa.gov/citations/19790007843

Bulk-synchronous parallel computing on the CELL processor

Authors: Johansson, Daniel Eriksson, Mattias Kessler, Christoph

Source: PARS-2007 21. PARS - Workshop, Hamburg, Germany, May 31-Jun 1, 2007. GI/ITG-Fachgruppe Parallel-Algorithmen, -Rechnerstrukturen und -Systemsoftware PARS.,2007.

Subject Terms: multicore processor architecture, parallel programming, bulk-synchronous parallelism, TECHNOLOGY, Information technology, Computer science, TEKNIKVETENSKAP, Informationsteknik, Datavetenskap

File Description: print

Access URL: https://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-40732