Suchergebnisse - acm: c.: computer system organisation/c.1: processor architekture/c.1.4: parallel architecture~

An Overview of Parallel Processors and Processing.

Autoren: Tse-Yun Feng¹

Quelle: ACM Computing Surveys. Mar77, Vol. 9 Issue 1, p1-2. 2p.

Schlagwörter: *MULTIPROCESSORS, *COMPUTER architecture, *PARALLEL processing, *COMPUTERS, DATA pipelining, LARGE scale integration of circuits

Reviews & Products: ACM Computing Surveys (Periodical)

Pipelined computations of B-spline curve.

Autoren: Wang, C.-H. Liu, H.-Y. Wen, R.-S.

Quelle: IEEE Transactions on Systems, Man & Cybernetics. 1992, Vol. 22 Issue 2, p327-331. 5p.

Analiza parametrów czasowych architektury potokowej specjalizowanych procesorów sprzętowychThe parameters analysis for pipeline architekture of specialised hardware processor

Autoren: Wiatr, K.

Schlagwörter: systemy czasu rzeczywistego, architektury systemów wieloprocesorowych, układy programowalne, image processing systems, architecture hardware processors

Zugangs-URL: http://yadda.icm.edu.pl/baztech/element/bwmeta1.element.baztech-article-BWA1-0001-0487

Can Traditional Programming Bridge the Ninja Performance Gap for Parallel Computing Applications?

Autoren: Satish, Nadathur Kim, Changkyu Chhugani, Jatin et al.

Quelle: Communications of the ACM. May2015, Vol. 58 Issue 5, p77-86. 10p. 2 Diagrams, 1 Chart, 9 Graphs.

Schlagwörter: *PARALLEL programming, *C++, PERFORMANCE, PARALLEL programs (Computer programs), MULTICORE processors, SIMD (Computer architecture)

A Survey of Techniques for Architecting and Managing Asymmetric Multicore Processors.

Autoren: MITTAL, SPARSH¹ (AUTHOR) mittals@ornl.gov

Quelle: ACM Computing Surveys. Feb2016, Vol. 48 Issue 3, p45:1-45:38. 38p. 2 Diagrams, 6 Charts.

Schlagwörter: *COMPUTER architecture, *COMPUTER systems, *PARALLEL processing, *VIRTUAL machine systems, MULTICORE processors, HETEROGENEITY, AMDAHL'S law

Associative and Parallel Processors.

Autoren: Thurber, Kenneth J. Wald, Leon D.

Quelle: ACM Computing Surveys. Dec75, Vol. 7 Issue 4, p215-255. 41p.

Schlagwörter: *COMPUTER architecture, *COMPUTER software, *PARALLEL processing, *COMPUTER systems, ARRAY processors, ILLIAC computer

The Connection Machine model CM-1 architecture.

Autoren: Kahle, B.A. Hillis, W.D.

Quelle: IEEE Transactions on Systems, Man & Cybernetics. 1989, Vol. 19 Issue 4, p707-713. 7p.

Associate Processor Architecture -- A Survey.

Autoren: S. S. Yau, Gordon J. H. S. Fung, Gordon J.

Quelle: ACM Computing Surveys. Mar77, Vol. 9 Issue 1, p3-27. 25p.

Schlagwörter: *MULTIPROCESSORS, *INTEGRATED circuits, *PARALLEL processing, *COMPUTERS, *COMPUTER architecture, *DISTRIBUTED computing

Informace o architektuře pro optimalizace v překladači LLVM ; Architecture Information for LLVM Compiler Optimizations

Autoren: Svoboda, Jan Hruška, Tomáš Dolíhal, Luděk

Weitere Verfasser: Svoboda, Jan Hruška, Tomáš Dolíhal, Luděk

Schlagwörter: překladač, optimalizace, cenový model, procesor, architektura, Codasip, CodAL, LLVM, compiler, optimization, cost model, processor, architecture

Dateibeschreibung: application/pdf; text/html

Relation: SVOBODA, J. Informace o architektuře pro optimalizace v překladači LLVM [online]. Brno: Vysoké učení technické v Brně. Fakulta informačních technologií. 2020.; 129281; http://hdl.handle.net/11012/192463

Verfügbarkeit: http://hdl.handle.net/11012/192463

Adaptation of an acoustic propagation model to the parallel architecture of a graphics processor

Autoren: Ey, Emanuel Felisberto, P. Sapientia

Weitere Verfasser: Ey, Emanuel Felisberto, P. Sapientia

Quelle: urn:tid:202485617

Schlagwörter: Underwater acoustics, Acoustic propagation modeling, High-performance computing, Open CL, Parallel computing

Dateibeschreibung: application/pdf

Verfügbarkeit: http://hdl.handle.net/10400.1/4990

The STAMPede Approach to Thread-Level Speculation.

Autoren: Steffan, J. Gregory Colohan, Christopher Zhai, Antonia et al.

Quelle: ACM Transactions on Computer Systems. Aug2005, Vol. 23 Issue 3, p253-300. 48p.

Schlagwörter: *COMPUTER architecture, *MULTIPROCESSORS, *MULTIMEDIA systems, *COMPUTERS, *COMPUTER systems, ELECTRONIC systems

EXPANSION OF THE ZONE OF PRACTICAL APPLICATION OF PLC WITH PARALLEL ARCHITECTURE ; ROZSZERZENIE STREFY PRAKTYCZNEGO ZASTOSOWANIA PLC O ARCHITEKTURĘ RÓWNOLEGŁĄ

Autoren: Tymchuk, Sergiy Piskarev, Oleksiy Miroshnyk, Oleksandr et al.

Quelle: Informatyka, Automatyka, Pomiary w Gospodarce i Ochronie Środowiska; Vol. 12 No. 3 (2022); 16-19 ; Informatyka, Automatyka, Pomiary w Gospodarce i Ochronie Środowiska; Tom 12 Nr 3 (2022); 16-19 ; 2391-6761 ; 2083-0157

Schlagwörter: programmable logic controllers, parallel architecture, software control system, programowalne sterowniki logiczne, architektura równoległa, programowy system sterowania

Dateibeschreibung: application/pdf

Relation: https://ph.pollub.pl/index.php/iapgos/article/view/2983/2726; https://ph.pollub.pl/index.php/iapgos/article/view/2983

Verfügbarkeit: https://ph.pollub.pl/index.php/iapgos/article/view/2983

A B-tree parallel processor for information retrieval.

Autoren: Hurson, A R Miller, L L

Quelle: International Journal of Mini & Microcomputers. 1987, Vol. 9 Issue 1, p6-10. 5p.

Schlagwörter: *Information retrieval, *Personal computers, Architecture

Can Parallel Algorithms Enhance Serial Implementations?

Autoren: Vishkin, Uzi¹ vishkin@unijacs.umd.edu

Quelle: Communications of the ACM. Sep96, Vol. 39 Issue 9, p88-91. 4p.

Schlagwörter: *COMPUTER software, *COMPUTER architecture, *COMPUTER science, *MULTIPROCESSORS, *PARALLEL programming, PARALLEL computers

Parallel generation of architecture on the GPU.

Autoren: Steinberger, Markus Kenzel, Michael Kainz, Bernhard et al.

Quelle: Computer Graphics Forum. May2014, Vol. 33 Issue 2, p73-82. 10p.

Schlagwörter: *COMPUTER architecture, *STOCHASTIC analysis, PARALLEL computers, GRAPHICS processing units, SHAPE recognition (Computer vision), CENTRAL processing units

Cyfrowy komórkowy system telekomunikacyjny (Faza 2) - Architektura sieci (GSM 03.02) PN-ETS 300 522 = Digital cellular telecommunications system (Phase 2); Network architekture (GSM 03.02) = Système de télécommunications numériques cellulaire (Phase 2); Architecture du réseau (GSM 03.02) = Zellulares digitales Funkkommunikationssystem (Phase 2); Netzwerkaufbau (GSM 03.02) / Polski Komitet Normalizacyjny.
Digital cellular telecommunications system (Phase 2); Network architekture (GSM 03.02)
PN-ETS 300 522:1998
Système de télécommunications numériques cellulaire (Phase 2); Architecture du réseau (GSM 03.02)
Zellulares digitales Funkkommunikationssystem (Phase 2); Netzwerkaufbau (GSM 03.02)

Weitere Verfasser: Polska. Polski Komitet Normalizacyjny. Instytucja sprawcza,Wydawca Instytucja sprawcza,Wydawca pbl

Zugangs-URL: http://katalog.nukat.edu.pl/lib/item?id=chamo:5357742&theme=nukat

Managing Burstiness and Scalability in Event-Driven Models on the SpiNNaker Neuromimetic System.

Autoren: Rast, Alexander Navaridas, Javier Jin, Xin et al.

Quelle: International Journal of Parallel Programming. Dec2012, Vol. 40 Issue 6, p553-582. 30p. 3 Color Photographs, 5 Diagrams, 7 Graphs.

Schlagwörter: *COMPUTER networks, *SCALABILITY, *ARTIFICIAL neural networks, *COMPUTER input-output equipment, EVENT driven systems (Computer science), COMPUTER simulation of integrated circuits, ADAPTIVE computing systems, DIGITAL computer simulation

Automatic Determination of Grain Size for Efficient Parallel Processing.

Autoren: McGregor, John D. Riehl, Arthur M. McCreary, C. et al.

Quelle: Communications of the ACM. Sep89, Vol. 32 Issue 9, p1073-1078. 6p. 15 Diagrams.

Schlagwörter: *PARALLEL processing, *COMPUTER programming, *ALGORITHMS, *MULTIPROCESSORS, *PARALLEL programming, PARALLEL computers

Automatically Accelerating Non-Numerical Programs by Architecture-Compiler Co-Design.

Autoren: Campanoni, Simone Brownell, Kevin Kanev, Svilen et al.

Quelle: Communications of the ACM. Dec2017, Vol. 60 Issue 12, p88-97. 10p. 4 Diagrams, 1 Chart, 3 Graphs.

Schlagwörter: *COMPUTER architecture, PARALLEL computer software, PARALLELIZING compilers, MICROPROCESSOR design & construction, MULTICORE processors

Akcelerace algoritmů na architektuře Larrabee ; Algorithm Acceleration on Larrabee Platform

Autoren: Veselý, Ivo Zemčík, Pavel Seeman, Michal

Weitere Verfasser: Veselý, Ivo Zemčík, Pavel Seeman, Michal

Schlagwörter: Larrabee, počítačová grafika, zpracování obrazu, více-jádrové počítání, paralelní počítání, SIMD, GPGPU, syntéza hologramu, optické pole, computer graphics, image processing, many-core computing, parallel computing, hologram synthesis, optical field

Dateibeschreibung: application/pdf; text/html

Relation: VESELÝ, I. Akcelerace algoritmů na architektuře Larrabee [online]. Brno: Vysoké učení technické v Brně. Fakulta informačních technologií. 2010.; 34936; http://hdl.handle.net/11012/52800

Verfügbarkeit: http://hdl.handle.net/11012/52800