Search Results - acm: c.: computer system organisation/c.1: processor architecture

Distributed Architecture for Resource Management in Large Scale Grids

Authors: Jeanvoine, Emmanuel Rilling, Louis Morin, Christine et al.

Contributors: Jeanvoine, Emmanuel Rilling, Louis Morin, Christine et al.

Source: https://inria.hal.science/inria-00001066 ; [Research Report] PI 1775, 2006, pp.13.

Subject Terms: Grid computing, distributed system, peer-to-peer overlay networks, resource allocation, self-healing \\ Grille de calcul, système distribué, réseaux logiques pair-à-pair, allocation de ressources, auto-réparation, ACM: C.: Computer Systems Organization/C.2: COMPUTER-COMMUNICATION NETWORKS/C.2.4: Distributed Systems, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.4: Parallel Architectures, [INFO.INFO-OH]Computer Science [cs]/Other [cs.OH]

Relation: Report N°: PI 1775

Availability: https://inria.hal.science/inria-00001066
https://inria.hal.science/inria-00001066v1/document
https://inria.hal.science/inria-00001066v1/file/PI-1775.pdf

Real-time scheduling on heterogeneous system-on-chip architectures using an optimised artificial neural network

Authors: Chillet, Daniel Eiche, Antoine Pillement, Sébastien et al.

Contributors: Chillet, Daniel Eiche, Antoine Pillement, Sébastien et al.

Source: ISSN: 1383-7621 ; Journal of Systems Architecture ; https://inria.hal.science/hal-00650650 ; Journal of Systems Architecture, 2011, 57, pp.340-353. ⟨10.1016/j.sysarc.2011.01.004⟩.

Subject Terms: Artificial neural network, Heterogeneous multi-processor architecture, Hopfield model, Inhibitor neurons, Task scheduling, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.3: Other Architecture Styles/C.1.3.7: Neural nets

Availability: https://inria.hal.science/hal-00650650
https://doi.org/10.1016/j.sysarc.2011.01.004

Novel Architecture of Smart FFT Processor

Authors: Teymourzadeh, Rozita University of California San Francisco (UC San Francisco) University of California (UC)

Contributors: Teymourzadeh, Rozita University of California San Francisco (UC San Francisco) University of California (UC)

Source: https://hal.archives-ouvertes.fr/hal-01802071 ; 2014.

Subject Terms: FFT, Digital Design, Processor, VLSI, Novel Architecture, Radix, Harmonic, ACM: D.: Software, ACM: B.: Hardware, ACM: C.: Computer Systems Organization, ACM: I.: Computing Methodologies, ACM: B.: Hardware/B.6: LOGIC DESIGN, ACM: B.: Hardware/B.5: REGISTER-TRANSFER-LEVEL IMPLEMENTATION, ACM: D.: Software/D.3: PROGRAMMING LANGUAGES, [INFO]Computer Science [cs], [INFO.INFO-AO]Computer Science [cs]/Computer Arithmetic, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [INFO.INFO-ES]Computer Science [cs]/Embedded Systems, [INFO.INFO-TS]Computer Science [cs]/Signal and Image Processing, [SPI]Engineering Sciences [physics], [SPI.SIGNAL]Engineering Sciences [physics]/Signal and Image processing, [SPI.TRON]Engineering Sciences [physics]/Electronics

Relation: hal-01802071; https://hal.archives-ouvertes.fr/hal-01802071; https://hal.archives-ouvertes.fr/hal-01802071/document; https://hal.archives-ouvertes.fr/hal-01802071/file/Novel%20Architecture%20of%20Smart%20FFT%20Processor_Draft.pdf

Availability: https://hal.archives-ouvertes.fr/hal-01802071
https://hal.archives-ouvertes.fr/hal-01802071/document
https://hal.archives-ouvertes.fr/hal-01802071/file/Novel%20Architecture%20of%20Smart%20FFT%20Processor_Draft.pdf

Comparison of the Discriminatory Processor Sharing Policies

Authors: Osipova, Natalia Models for the performance analysis and the control of networks (MAESTRO) Centre Inria d'Université Côte d'Azur et al.

Contributors: Osipova, Natalia Models for the performance analysis and the control of networks (MAESTRO) Centre Inria d'Université Côte d'Azur et al.

Source: https://inria.hal.science/inria-00264111 ; [Research Report] RR-6475, INRIA. 2008, pp.19.

Subject Terms: ACM: C.: Computer Systems Organization/C.2: COMPUTER-COMMUNICATION NETWORKS/C.2.2: Network Protocols, ACM: G.: Mathematics of Computing/G.3: PROBABILITY AND STATISTICS/G.3.8: Queueing theory, [INFO.INFO-MO]Computer Science [cs]/Modeling and Simulation, [INFO.INFO-NI]Computer Science [cs]/Networking and Internet Architecture [cs.NI]

Relation: info:eu-repo/semantics/altIdentifier/arxiv/0803.2129; ARXIV: 0803.2129

Availability: https://inria.hal.science/inria-00264111
https://inria.hal.science/inria-00264111v4/document
https://inria.hal.science/inria-00264111v4/file/rr_6475_dps.pdf

TBES: Template-Based Exploration and Synthesis of Heterogeneous Multiprocessor Architectures on FPGA

Authors: Corre, Youenn Diguet, Jean-Philippe Heller, Dominique et al.

Contributors: Corre, Youenn Diguet, Jean-Philippe Heller, Dominique et al.

Source: ISSN: 1539-9087.

Subject Terms: System-on-Chip, Multiprocessor, High-Level Synthesis, Electronic System Level, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES, ACM: B.: Hardware/B.5: REGISTER-TRANSFER-LEVEL IMPLEMENTATION, ACM: D.: Software/D.2: SOFTWARE ENGINEERING/D.2.2: Design Tools and Techniques, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

Availability: https://hal.science/hal-01172103
https://hal.science/hal-01172103v1/document
https://hal.science/hal-01172103v1/file/Preprint_TECS_YC%20%283%29.pdf

Reconstruction of switching thresholds in piecewise-affine models of genetic regulatory networks

Authors: Drulhe, Samuel Ferrari-Trecate, Giancarlo de Jong, Hidde et al.

Contributors: Drulhe, Samuel Ferrari-Trecate, Giancarlo de Jong, Hidde et al.

Source: Hybrid Systems: Computation and Control, HSCC 2006 ; https://inria.hal.science/inria-00001225 ; Hybrid Systems: Computation and Control, HSCC 2006, Mar 2006, Santa Barbara, CA, USA, pp.184 - 199, ⟨10.1007/11730637⟩

Subject Terms: Hybrid system, Genetic regulatory network, system identification, switching thresholds reconstruction, ACM: C.: Computer Systems Organization, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.3: Other Architecture Styles/C.1.3.5: Heterogeneous (hybrid) systems, ACM: I.: Computing Methodologies/I.6: SIMULATION AND MODELING/I.6.1: Simulation Theory/I.6.1.1: Systems theory, [SDV.OT]Life Sciences [q-bio]/Other [q-bio.OT]

Availability: https://inria.hal.science/inria-00001225
https://inria.hal.science/inria-00001225v1/document
https://inria.hal.science/inria-00001225v1/file/LNCS_HSCC06.pdf
https://doi.org/10.1007/11730637

A Framework for Task Scheduling and Memory Partitioning for Multi-Processor System-on-Chip

Authors: Salamy, Hassan Ramanujam, J. Department of Electrical and Computer Engineering - Louisiana State University (ECE) et al.

Contributors: Salamy, Hassan Ramanujam, J. Department of Electrical and Computer Engineering - Louisiana State University (ECE) et al.

Source: HiPEAC 2009 - High Performance and Embedded Architectures and Compilers ; https://hal.inria.fr/inria-00446288 ; HiPEAC 2009 - High Performance and Embedded Architectures and Compilers, Jan 2009, Paphos, Cyprus. ⟨10.1007/978-3-540-92990-1_20⟩

Subject Terms: ACM: B.: Hardware/B.2: ARITHMETIC AND LOGIC STRUCTURES, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES, ACM: D.: Software/D.3: PROGRAMMING LANGUAGES/D.3.4: Processors, [INFO.INFO-OH]Computer Science [cs]/Other [cs.OH], [INFO.INFO-ES]Computer Science [cs]/Embedded Systems

Subject Geographic: Paphos, Cyprus

Relation: inria-00446288; https://hal.inria.fr/inria-00446288

Availability: https://hal.inria.fr/inria-00446288
https://doi.org/10.1007/978-3-540-92990-1_20

Towards a New Processor Architecture. ; Vers une nouvelle Architecture de Processeurs

Authors: Vincent, Pierre Landru, Jacques Ecole nationale supérieure Mines-Télécom Lille Douai (IMT Nord Europe) et al.

Contributors: Vincent, Pierre Landru, Jacques Ecole nationale supérieure Mines-Télécom Lille Douai (IMT Nord Europe) et al.

Source: https://hal.science/hal-05117313 ; 2025.

Subject Terms: silicon, parallel, serial, RISC, photonics, computer, optronics, optics, processor, fiber, laser, digital, silicium, parallèle, série, processeur, photonique, ordinateur, optronique, optique, numérique, fibre, ACM: B.: Hardware, ACM: C.: Computer Systems Organization, [INFO]Computer Science [cs], [PHYS]Physics [physics]

Availability: https://hal.science/hal-05117313
https://hal.science/hal-05117313v2/document
https://hal.science/hal-05117313v2/file/frParalSerieRiscV1.pdf

Architecture des ordinateurs

Authors: Lagadec, Loïc Pillement, Sébastien Tisserand, Arnaud et al.

Contributors: Lagadec, Loïc Pillement, Sébastien Tisserand, Arnaud et al.

Subject Terms: [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [INFO.INFO-AR] Computer Science [cs]/Hardware Architecture [cs.AR], ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES

Access URL: https://inria.hal.science/hal-00819668v1

A continuation-based noninterruptible multithreading processor architecture.

Authors: Amamiya, Satoshi Amamiya, Makoto Hasegawa, Ryuzo et al.

Source: Journal of Supercomputing; Feb2009, Vol. 47 Issue 2, p228-252, 25p, 18 Diagrams, 1 Chart, 10 Graphs

Subject Terms: INTEGRATED circuits, SIMULTANEOUS multithreading processors, COMPUTER architecture, COMPUTERS, COMPUTER operating systems, COMPUTER software, COMPUTER programming

Architectures of Flexible Symmetric Key Crypto Engines-A Survey: From Hardware Coprocessor to Multi-Crypto-Processor System on Chip.

Authors: BOSSUET, LILIAN GRAND, MICHAEL GASPAR, LUBOS et al.

Source: ACM Computing Surveys; Aug2013, Vol. 45 Issue 4, p41-41:32, 32p, 9 Diagrams, 3 Charts, 2 Graphs

Subject Terms: CRYPTOGRAPHY research, COMPUTER network security, COMPUTER architecture, FAULT-tolerant computing, FAULT tolerance (Engineering), RELIABILITY in engineering

On-Chip Memory Architecture Exploration Framework for DSP Processor-Based Embedded System on Chip.

Authors: Kumar, T. S. Rajesh Govindarajan, R. Ravikumar, C. P.

Source: ACM Transactions on Embedded Computing Systems; Mar2012, Vol. 11 Issue 1, p1-25, 25p

Subject Terms: SYSTEMS on a chip, COMPUTER storage devices, COMPUTER architecture, DIGITAL signal processing, EMBEDDED computer systems, PERFORMANCE evaluation, PERSONAL computers

Configurable simulator for computer architecture and organization.

Authors: Radivojevic, Zaharije Stanisavljevic, Zarko Punt, Marija

Source: Computer Applications in Engineering Education; Sep2018, Vol. 26 Issue 5, p1711-1724, 14p, 10 Diagrams, 2 Charts, 2 Graphs

Subject Terms: COMPUTER architecture, STUDENTS, COMPUTER systems, MICROPROGRAMMING, COMPUTER programming

A Case for a Complexity-Effective, Width-partitioned Microarchitecture

Authors: Rochecouste, Olivier Pokam, Gilles Seznec, André et al.

Contributors: Rochecouste, Olivier Pokam, Gilles Seznec, André et al.

Source: https://inria.hal.science/inria-00000211 ; [Research Report] PI 1742, 2005, pp.27.

Subject Terms: Hardaware complexity, power consumption, superscalar processor, width-partitioned microarchitecture, register file, narrow-width operations, data-width predictor \\ Complexité matérielle, consommation électrique, processeur superscalaire, microarchitecture clusterisée, fichier de registres, opérations tronquées, prédicteur de largeur, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES, ACM: C.: Computer Systems Organization/C.3: SPECIAL-PURPOSE AND APPLICATION-BASED SYSTEMS, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

Relation: Report N°: PI 1742

Availability: https://inria.hal.science/inria-00000211
https://inria.hal.science/inria-00000211/document
https://inria.hal.science/inria-00000211/file/PI-1742.pdf

System-on-chip implementation of the whole advanced encryption standard processor using reduced XOR-based sum-of-product operations.

Authors: Hsiao, S.-F. Chen, M.-C. Tsai, M.-Y et al.

Source: IEE Proceedings -- Information Security; Oct2005, Vol. 152 Issue 1, p21-30, 10p, 4 Diagrams, 6 Charts

Subject Terms: COMPUTER input-output equipment, SYSTEMS design, ALGORITHMS, DATA protection, ARRAY processors, APPLICATION-specific integrated circuits

A Novel Approach to Multiagent based Scheduling for Multicore Architecture.

Authors: Muneeswari, G. Ahila, A. Sobitha Shunmuganathan, K. L.

Source: GSTF Journal on Computing; 2011, Vol. 1 Issue 2, p184-189, 6p

Subject Terms: MULTICORE processors, PARALLEL computers, COMPUTER operating systems, MULTIAGENT systems, ALGORITHMS

Scheduling issues on thermally-constrained processors

Authors: Michaud, Pierre Sazeides, Yiannakis Compilation, parallel architectures and system (CAPS) et al.

Contributors: Michaud, Pierre Sazeides, Yiannakis Compilation, parallel architectures and system (CAPS) et al.

Source: https://inria.hal.science/inria-00110507 ; [Research Report] PI 1822, 2006, pp.19.

Subject Terms: Multi-core processor, temperature, thread scheduling, time slice, activity migration, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

Relation: Report N°: PI 1822

Availability: https://inria.hal.science/inria-00110507
https://inria.hal.science/inria-00110507/document
https://inria.hal.science/inria-00110507/file/PI-1822.pdf

Impact of on-chip network parameters on NUCA cache performances.

Authors: Bardine, A. Comparetti, M. Foglia, P. et al.

Source: IET Computers & Digital Techniques (Institution of Engineering & Technology); Sep2009, Vol. 3 Issue 5, p501-512, 12p, 3 Diagrams, 2 Charts, 7 Graphs

Subject Terms: NETWORK routers, COMPUTER architecture, SYSTEMS development, COMPUTER systems, COMPUTER network architectures

Batch Processor Sharing with Hyper-Exponential Service Time

Authors: Osipova, Natalia Models for the performance analysis and the control of networks (MAESTRO) Centre Inria d'Université Côte d'Azur et al.

Contributors: Osipova, Natalia Models for the performance analysis and the control of networks (MAESTRO) Centre Inria d'Université Côte d'Azur et al.

Source: https://inria.hal.science/inria-00144389 ; [Research Report] RR-6180, INRIA. 2007, pp.21.

Subject Terms: Cauchy matrices, Batch Processor Sharing, Two Level Processor sharing, Hyper-Exponential distribution, Laplace transform, Communication Systems, ACM: C.: Computer Systems Organization/C.2: COMPUTER-COMMUNICATION NETWORKS/C.2.2: Network Protocols, [INFO.INFO-NI]Computer Science [cs]/Networking and Internet Architecture [cs.NI], [INFO.INFO-WB]Computer Science [cs]/Web

Relation: info:eu-repo/semantics/altIdentifier/arxiv/0705.0425; ARXIV: 0705.0425

Availability: https://inria.hal.science/inria-00144389
https://inria.hal.science/inria-00144389v4/document
https://inria.hal.science/inria-00144389v4/file/rr-6180.pdf

Power Estimation of a C algorithm on a VLIW Processor

Authors: Julien, Nathalie Senn, Eric Laurent, Johann et al.

Contributors: Julien, Nathalie Senn, Eric Laurent, Johann et al.

Source: WCED ; https://hal.science/hal-00077336 ; 2002, pp 100

Subject Terms: FLPA, DSP VLIW, Power consumption, Energy, Estimation, IEEE, ACM, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

Availability: https://hal.science/hal-00077336
https://hal.science/hal-00077336v1/document
https://hal.science/hal-00077336v1/file/WCED_02.pdf