Search Results - acm: c.: computer system organisation/c.1: processor architecture/c.1.4: parallel architecture*

Distributed Architecture for Resource Management in Large Scale Grids

Authors: Jeanvoine, Emmanuel Rilling, Louis Morin, Christine et al.

Contributors: Jeanvoine, Emmanuel Rilling, Louis Morin, Christine et al.

Source: https://inria.hal.science/inria-00001066 ; [Research Report] PI 1775, 2006, pp.13.

Subject Terms: Grid computing, distributed system, peer-to-peer overlay networks, resource allocation, self-healing \\ Grille de calcul, système distribué, réseaux logiques pair-à-pair, allocation de ressources, auto-réparation, ACM: C.: Computer Systems Organization/C.2: COMPUTER-COMMUNICATION NETWORKS/C.2.4: Distributed Systems, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.4: Parallel Architectures, [INFO.INFO-OH]Computer Science [cs]/Other [cs.OH]

Relation: Report N°: PI 1775

Availability: https://inria.hal.science/inria-00001066
https://inria.hal.science/inria-00001066v1/document
https://inria.hal.science/inria-00001066v1/file/PI-1775.pdf

Towards a New Processor Architecture. ; Vers une nouvelle Architecture de Processeurs

Authors: Vincent, Pierre Landru, Jacques Ecole nationale supérieure Mines-Télécom Lille Douai (IMT Nord Europe) et al.

Contributors: Vincent, Pierre Landru, Jacques Ecole nationale supérieure Mines-Télécom Lille Douai (IMT Nord Europe) et al.

Source: https://hal.science/hal-05117313 ; 2025.

Subject Terms: silicon, parallel, serial, RISC, photonics, computer, optronics, optics, processor, fiber, laser, digital, silicium, parallèle, série, processeur, photonique, ordinateur, optronique, optique, numérique, fibre, ACM: B.: Hardware, ACM: C.: Computer Systems Organization, [INFO]Computer Science [cs], [PHYS]Physics [physics]

Availability: https://hal.science/hal-05117313
https://hal.science/hal-05117313v2/document
https://hal.science/hal-05117313v2/file/frParalSerieRiscV1.pdf

A Novel Approach to Multiagent based Scheduling for Multicore Architecture.

Authors: Muneeswari, G. Ahila, A. Sobitha Shunmuganathan, K. L.

Source: GSTF Journal on Computing; 2011, Vol. 1 Issue 2, p184-189, 6p

Subject Terms: MULTICORE processors, PARALLEL computers, COMPUTER operating systems, MULTIAGENT systems, ALGORITHMS

A continuation-based noninterruptible multithreading processor architecture.

Authors: Amamiya, Satoshi Amamiya, Makoto Hasegawa, Ryuzo et al.

Source: Journal of Supercomputing; Feb2009, Vol. 47 Issue 2, p228-252, 25p, 18 Diagrams, 1 Chart, 10 Graphs

Subject Terms: INTEGRATED circuits, SIMULTANEOUS multithreading processors, COMPUTER architecture, COMPUTERS, COMPUTER operating systems, COMPUTER software, COMPUTER programming

Processing while routing: a network-on-chip-based parallel system.

Authors: Fernandes, S. R. Oliveira, B. C. Costa, M. et al.

Source: IET Computers & Digital Techniques (Institution of Engineering & Technology); Sep2009, Vol. 3 Issue 5, p525-538, 14p, 9 Diagrams, 2 Charts, 10 Graphs

Subject Terms: COMPUTER architecture, NETWORK routers, SYSTEMS development, COMPUTER input-output equipment, COMPUTER systems

High Level Transforms for SIMD and Low-Level Computer Vision Algorithms

Authors: Lacassagne, Lionel Etiemble, Daniel Zahraee, Hassan et al.

Contributors: Lacassagne, Lionel Etiemble, Daniel Zahraee, Hassan et al.

Source: Symposium on Principles and Practice of Parallel Programming / WPMVP ; https://inria.hal.science/hal-01094906 ; Symposium on Principles and Practice of Parallel Programming / WPMVP, Feb 2014, Orlando, Florida, United States. pp.8, ⟨10.1145/2568058.2568067⟩ ; https://sites.google.com/site/ppopp2014/

Subject Terms: Intel SSE & XeonPhi, SIMD, High Level Transforms, ARM Neon, IBM Altivec, code optimization, 2D stencil, low-level computer vision and image processing algorithms, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.1: Single Data Stream Architectures, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.4: Parallel Architectures, ACM: D.: Software/D.1: PROGRAMMING TECHNIQUES/D.1.3: Concurrent Programming/D.1.3.1: Parallel programming, ACM: D.: Software/D.3: PROGRAMMING LANGUAGES/D.3.4: Processors/D.3.4.1: Compilers, ACM: D.: Software/D.3: PROGRAMMING LANGUAGES/D.3.4: Processors/D.3.4.6: Optimization, ACM: I.: Computing Methodologies/I.4: IMAGE PROCESSING AND COMPUTER VISION/I.4.7: Feature Measurement, [INFO.INFO-DS]Computer Science [cs]/Data Structures and Algorithms [cs.DS], [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [INFO.INFO-SE]Computer Science [cs]/Software Engineering [cs.SE], [INFO.INFO-DM]Computer Science [cs]/Discrete Mathematics [cs.DM], [INFO.INFO-RB]Computer Science [cs]/Robotics [cs.RO], [INFO.INFO-TI]Computer Science [cs]/Image Processing [eess.IV], [INFO.INFO-TS]Computer Science [cs]/Signal and Image Processing, [INFO.INFO-CV]Computer Science [cs]/Computer Vision and Pattern Recognition [cs.CV], [SPI.AUTO]Engineering Sciences [physics]/Automatic, [SPI.SIGNAL]Engineering Sciences [physics]/Signal and Image processing, [INFO.INFO-AO]Computer Science [cs]/Computer Arithmetic, [INFO.INFO-DC]Computer Science [cs]/Distributed, Parallel, and Cluster Computing [cs.DC]

Subject Geographic: Orlando, Florida, United States

Availability: https://inria.hal.science/hal-01094906
https://inria.hal.science/hal-01094906v1/document
https://inria.hal.science/hal-01094906v1/file/simd-140122.pdf
https://doi.org/10.1145/2568058.2568067

From Scilab to Multicore Embedded Systems: Algorithms and Methodologies

Authors: Goulas, George Alefragis, Panayiotis Voros, Nikolaos S. et al.

Contributors: Goulas, George Alefragis, Panayiotis Voros, Nikolaos S. et al.

Source: Proceedings of the IEEE International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (IC-SAMOS 2012 ; https://inria.hal.science/hal-00752615 ; Proceedings of the IEEE International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (IC-SAMOS 2012, Jul 2012, Samos, Greece

Subject Terms: ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.4: Parallel Architectures, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

Subject Geographic: Samos, Greece

Availability: https://inria.hal.science/hal-00752615

Architecture Studies and System Demonstrations of Optical Parallel Processor for AI and NI

Authors: Lee, Sing H. Esener, Sadik C. CALIFORNIA UNIV SAN DIEGO LA JOLLA DEPT OF ELECTRICAL AND COMPUTER ENGINEERING

Contributors: Lee, Sing H. Esener, Sadik C. CALIFORNIA UNIV SAN DIEGO LA JOLLA DEPT OF ELECTRICAL AND COMPUTER ENGINEERING

Source: DTIC AND NTIS

Subject Terms: Electrooptical and Optoelectronic Devices, Computer Hardware, COMPUTER ARCHITECTURE, MULTIPROCESSORS, PARALLEL PROCESSORS, OPTICAL PROCESSING, ELECTROOPTICS, COMPUTER PROGRAMMING, NERVOUS SYSTEM, ARTIFICIAL INTELLIGENCE, DEMONSTRATIONS, ARCHITECTURE, INTELLIGENCE, OPTICAL EQUIPMENT, ALGORITHMS, PROTOTYPES

File Description: text/html

Relation: http://www.dtic.mil/docs/citations/ADA244170

Availability: http://www.dtic.mil/docs/citations/ADA244170
http://oai.dtic.mil/oai/oai?&verb=getRecord&metadataPrefix=html&identifier=ADA244170

Covariance tracking: architecture optimizations for embedded systems

Authors: Romero, Andrés Lacassagne, Lionel Gouiffès, Michèle et al.

Contributors: Romero, Andrés Lacassagne, Lionel Gouiffès, Michèle et al.

Source: ISSN: 1687-6172.

Subject Terms: covariance-tracking, real-time image processing, SIMD, SSE, AVX, Neon, ACM: I.: Computing Methodologies/I.4: IMAGE PROCESSING AND COMPUTER VISION/I.4.8: Scene Analysis/I.4.8.2: Motion, ACM: I.: Computing Methodologies/I.4: IMAGE PROCESSING AND COMPUTER VISION/I.4.8: Scene Analysis/I.4.8.12: Tracking, ACM: I.: Computing Methodologies/I.4: IMAGE PROCESSING AND COMPUTER VISION/I.4.7: Feature Measurement/I.4.7.1: Invariants, ACM: I.: Computing Methodologies/I.4: IMAGE PROCESSING AND COMPUTER VISION/I.4.7: Feature Measurement/I.4.7.2: Moments, ACM: I.: Computing Methodologies/I.4: IMAGE PROCESSING AND COMPUTER VISION/I.4.7: Feature Measurement/I.4.7.5: Texture, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.4: Parallel Architectures/C.1.4.1: Mobile processors, ACM: D.: Software/D.3: PROGRAMMING LANGUAGES/D.3.4: Processors/D.3.4.6: Optimization, [INFO.INFO-DS]Computer Science [cs]/Data Structures and Algorithms [cs.DS], [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [SPI.AUTO]Engineering Sciences [physics]/Automatic, [SPI.SIGNAL]Engineering Sciences [physics]/Signal and Image processing, [INFO.INFO-AO]Computer Science [cs]/Computer Arithmetic, [INFO.INFO-DC]Computer Science [cs]/Distributed, Parallel, and Cluster Computing [cs.DC], [INFO.INFO-SE]Computer Science [cs]/Software Engineering [cs.SE], [INFO.INFO-DM]Computer Science [cs]/Discrete Mathematics [cs.DM], [INFO.INFO-RB]Computer Science [cs]/Robotics [cs.RO], [INFO.INFO-TI]Computer Science [cs]/Image Processing [eess.IV], [INFO.INFO-TS]Computer Science [cs]/Signal and Image Processing, [INFO.INFO-CV]Computer Science [cs]/Computer Vision and Pattern Recognition [cs.CV]

Availability: https://inria.hal.science/hal-01094903
https://inria.hal.science/hal-01094903v1/document
https://inria.hal.science/hal-01094903v1/file/Eurasip%202014-12.pdf
https://doi.org/10.1186/1687-6180-2014-175

Implementing Wilson-Dirac Operator on the Cell Broadband Engine

Authors: Ibrahim, Khaled Z. Bodin, François Compilation, parallel architectures and system (CAPS) et al.

Contributors: Ibrahim, Khaled Z. Bodin, François Compilation, parallel architectures and system (CAPS) et al.

Source: https://inria.hal.science/inria-00203478 ; [Research Report] PI 1880, 2007, pp.23.

Subject Terms: IBM Cell BE, Vectorization, SIMD, Lattice QCD, Parallel Algorithms, Wilson-Dirac, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

Relation: Report N°: PI 1880

Availability: https://inria.hal.science/inria-00203478
https://inria.hal.science/inria-00203478v1/document
https://inria.hal.science/inria-00203478v1/file/PI-1880.pdf

Parallel Evaluation of Hopfield Neural Networks

Authors: Eiche, Antoine Chillet, Daniel Pillement, Sébastien et al.

Contributors: Eiche, Antoine Chillet, Daniel Pillement, Sébastien et al.

Source: NCTA, International Conference on Neural Computation Theory and Applications ; https://inria.hal.science/hal-00650633 ; NCTA, International Conference on Neural Computation Theory and Applications, Oct 2011, Paris, France

Subject Terms: ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.3: Other Architecture Styles/C.1.3.7: Neural nets

Subject Geographic: Paris, France

Availability: https://inria.hal.science/hal-00650633

Top Picks in Computer Architecture from Conferences in 2018.

Authors: Dwarkadas, Sandhya

Source: IEEE Micro; May-Jun2019, Vol. 39 Issue 3, p6-10, 5p

Subject Terms: COMPUTER architecture, ORDER picking systems, MESSAGE authentication codes, PARALLEL computers, RANDOM access memory

A Parallel System Architecture Based on Dynamically Configurable Shared Memory Clusters.

Authors: Tudruj, Marek Masko, Łukasz

Source: Parallel Processing & Applied Mathematics (9783540437925); 2006, p51-61, 11p

Dynamic sharing of a multiple access channel

Authors: Bienkowski, Marcin Klonowski, Marek Korzeniowski, Miroslaw et al.

Contributors: Bienkowski, Marcin Klonowski, Marek Korzeniowski, Miroslaw et al.

Source: 27th International Symposium on Theoretical Aspects of Computer Science - STACS 2010
https://inria.hal.science/inria-00457096
27th International Symposium on Theoretical Aspects of Computer Science - STACS 2010, Inria Nancy Grand Est & Loria, Mar 2010, Nancy, France. pp.83-94

Subject Terms: distributed algorithms, multiple access channel, mutual exclusion, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.4: Parallel Architectures, ACM: C.: Computer Systems Organization/C.2: COMPUTER-COMMUNICATION NETWORKS/C.2.1: Network Architecture and Design, ACM: F.: Theory of Computation/F.2: ANALYSIS OF ALGORITHMS AND PROBLEM COMPLEXITY/F.2.2: Nonnumerical Algorithms and Problems, [INFO.INFO-DS]Computer Science [cs]/Data Structures and Algorithms [cs.DS]

Subject Geographic: Nancy, France

Relation: inria-00457096; https://inria.hal.science/inria-00457096; https://inria.hal.science/inria-00457096/document; https://inria.hal.science/inria-00457096/file/bienkowski.pdf

Availability: https://inria.hal.science/inria-00457096
https://inria.hal.science/inria-00457096/document
https://inria.hal.science/inria-00457096/file/bienkowski.pdf

Parameter Exploration to Improve Performance of Memristor-Based Neuromorphic Architectures

Authors: Mahyar Shahsavari Pierre Boulet Boulet, Pierre et al.

Contributors: Mahyar Shahsavari Pierre Boulet Boulet, Pierre et al.

Source: IEEE Transactions on Multi-Scale Computing Systems. 4:833-846

Subject Terms: [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], Neuromorphic Computing, 0301 basic medicine, [INFO.INFO-DC]Computer Science [cs]/Distributed, [INFO.INFO-AR] Computer Science [cs]/Hardware Architecture [cs.AR], ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.3: Other Architecture Styles/C.1.3.7: Neural nets, [INFO.INFO-NE] Computer Science [cs]/Neural and Evolutionary Computing [cs.NE], Unsupervised Learning, 02 engineering and technology, [INFO.INFO-NE]Computer Science [cs]/Neural and Evolutionary Computing [cs.NE], Memristor, Parallel, [INFO.INFO-ES] Computer Science [cs]/Embedded Systems, Spiking Neural Networks, 03 medical and health sciences, and Cluster Computing [cs.DC], Parameter Evaluations, [INFO.INFO-ET] Computer Science [cs]/Emerging Technologies [cs.ET], [INFO.INFO-DC] Computer Science [cs]/Distributed, Parallel, and Cluster Computing [cs.DC], 0202 electrical engineering, electronic engineering, information engineering, [INFO.INFO-ES]Computer Science [cs]/Embedded Systems, [INFO.INFO-ET]Computer Science [cs]/Emerging Technologies [cs.ET]

File Description: application/pdf

Access URL: https://hal.archives-ouvertes.fr/hal-01615032/file/TMSCSSI-2016-10-0051.R1-main.pdf
https://ieeexplore.ieee.org/document/8063353
https://hal.archives-ouvertes.fr/hal-01615032/document
https://jglobal.jst.go.jp/en/detail?JGLOBAL_ID=201902258056300336
https://dblp.uni-trier.de/db/journals/tmscs/tmscs4.html#ShahsavariB18
https://hal.archives-ouvertes.fr/hal-01615032
https://hal.science/hal-01615032v1/document
https://hal.science/hal-01615032v1
https://doi.org/10.1109/tmscs.2017.2761231

The Bulk Multicore Architecture for Improved Programmability. (cover story)

Authors: TORRELAS, JOSEP CEZE, LUIS TUCK, JAMES et al.

Source: Communications of the ACM; Dec2009, Vol. 52 Issue 12, p58-65, 8p, 1 Color Photograph, 7 Diagrams

Subject Terms: COMPUTER architecture, MULTIPROCESSORS, MICROPROCESSOR programming, PARALLEL processing, PARALLEL programming, SCALABILITY

Scientific Workflow Scheduling with Provenance Support in Multisite Cloud

Authors: Liu, Ji Pacitti, Esther Valduriez, Patrick et al.

Contributors: Liu, Ji Pacitti, Esther Valduriez, Patrick et al.

Source: 12th International Conference on Vector and Parallel Processing
VECPAR: Vector and Parallel Processing
https://hal-lirmm.ccsd.cnrs.fr/lirmm-01342190
VECPAR: Vector and Parallel Processing, Faculty of Engineering of the University of Porto, Portugal, Jun 2016, Porto, Portugal. pp.206-219, ⟨10.1007/978-3-319-61982-8_19⟩
http://vecpar.fe.up.pt/2016/

Subject Terms: Scientific workflow, Scientific workflow management system, Parallel execution, Multisite cloud, Scheduling, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.4: Parallel Architectures/C.1.4.0: Distributed architectures, [INFO.INFO-DB]Computer Science [cs]/Databases [cs.DB]

Subject Geographic: Porto, Portugal

Time: Porto, Portugal

Relation: info:eu-repo/grantAgreement//689772/EU/HPC for Energy/HPC4E

Availability: https://hal-lirmm.ccsd.cnrs.fr/lirmm-01342190
https://hal-lirmm.ccsd.cnrs.fr/lirmm-01342190v1/document
https://hal-lirmm.ccsd.cnrs.fr/lirmm-01342190v1/file/VECPAR.pdf
https://doi.org/10.1007/978-3-319-61982-8_19

6.823 Computer System Architecture, Spring 2002 ; Computer System Architecture

Authors: Asanovic, Krste Arvind, V. Devadas, Srinivas et al.

Contributors: Asanovic, Krste Arvind, V. Devadas, Srinivas et al.

Subject Terms: computer architecture, computer system architecture, hardware, hardware design, software, software design, instruction set design, processor micro-architecture, pipelining, cache memory, virtual memory, I/O, input/output, interrupts, superscalar architectures, VLIW machines, vector supercomputers, multithreaded architectures, symmetric multiprocessors, parallel computers

Subject Geographic: Spring 2002

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Relation: local: 6.823; http://hdl.handle.net/1721.1/35849

Availability: http://hdl.handle.net/1721.1/35849

CASH Design Space Exploration

Authors: He, Liqiang Dolbeau, Romain Seznec, André et al.

Contributors: He, Liqiang Dolbeau, Romain Seznec, André et al.

Source: https://inria.hal.science/inria-00116799 ; [Research Report] PI 1815, 2006, pp.59.

Subject Terms: CASH, design space exploration, performance, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

Relation: Report N°: PI 1815

Availability: https://inria.hal.science/inria-00116799
https://inria.hal.science/inria-00116799/document
https://inria.hal.science/inria-00116799/file/PI-1815.pdf

On-Chip Memory Architecture Exploration Framework for DSP Processor-Based Embedded System on Chip.

Authors: Kumar, T. S. Rajesh Govindarajan, R. Ravikumar, C. P.

Source: ACM Transactions on Embedded Computing Systems; Mar2012, Vol. 11 Issue 1, p1-25, 25p

Subject Terms: SYSTEMS on a chip, COMPUTER storage devices, COMPUTER architecture, DIGITAL signal processing, EMBEDDED computer systems, PERFORMANCE evaluation, PERSONAL computers