Search Results - acm: c.: computer system organisation/c.1: processor architectural/c.1.4: parallel architecture~

HMP-ASIPs: heterogeneous multi-pipeline application-specific instruction-set processors.

Authors: Radhakrishnan, S. Guo, H. Parameswaran, S. et al.

Source: IET Computers & Digital Techniques (Institution of Engineering & Technology); Jan2009, Vol. 3 Issue 1, p94-108, 15p, 13 Diagrams, 4 Charts, 3 Graphs

Subject Terms: COMPUTER architecture, ARCHITECTURAL designs, ARCHITECTURE, INDUSTRIAL design, SET (Computer network protocol)

A Parallel System Architecture Based on Dynamically Configurable Shared Memory Clusters.

Authors: Tudruj, Marek Masko, Łukasz

Source: Parallel Processing & Applied Mathematics (9783540437925); 2006, p51-61, 11p

Exploiting Timing Error Resilience in Processor Architecture.

Authors: SARTORI, JOHN KUMAR, RAKESH

Source: ACM Transactions on Embedded Computing Systems; May2013 Supplement 2, Vol. 12, p1-25, 25p

Subject Terms: COMPLEMENTARY metal oxide semiconductor design & construction, MACRO processors, COMPUTER architecture, ERROR rates, ERRORS, MOORE'S law, INDUSTRIAL costs

A Novel Approach to Multiagent based Scheduling for Multicore Architecture.

Authors: Muneeswari, G. Ahila, A. Sobitha Shunmuganathan, K. L.

Source: GSTF Journal on Computing; 2011, Vol. 1 Issue 2, p184-189, 6p

Subject Terms: MULTICORE processors, PARALLEL computers, COMPUTER operating systems, MULTIAGENT systems, ALGORITHMS

Reliability aware throughput management of chip multi-processor architecture via thread migration.

Authors: Pouyan, Fatemeh Azarpeyvand, Ali Safari, Saeed et al.

Source: Journal of Supercomputing; Apr2016, Vol. 72 Issue 4, p1363-1380, 18p

Subject Terms: SIMULTANEOUS multithreading processors, COMPUTER architecture, SOFT errors, MINIATURE electronic equipment, PARALLEL processing, MULTIPROCESSORS

Hardware Architectural Support for Control Systems and Sensor Processing.

Authors: VYAS, SUDHANSHU GUPTE, ADWAIT GILL, CHRISTOPHER D. et al.

Source: ACM Transactions on Embedded Computing Systems; Sep2013, Vol. 13 Issue 2, p1-25, 25p

Subject Terms: COMPUTER input-output equipment, COMPUTER architecture, AUTOMATIC control systems, SENSOR networks, DIGITAL signal processing, ALGORITHMS, PID controllers

Processor Design for Soft Errors: Challenges and State of the Art.

Authors: LI, TUO AMBROSE, JUDE ANGELO RAGEL, ROSHAN et al.

Source: ACM Computing Surveys; Dec2016, Vol. 49 Issue 3, p1-44, 44p, 3 Diagrams, 4 Charts, 1 Graph

Subject Terms: SOFT errors, MICROPROCESSOR design & construction, ERROR rates, COMPUTER architecture, DATA, ERROR detection (Information theory)

Top Picks in Computer Architecture from Conferences in 2018.

Authors: Dwarkadas, Sandhya

Source: IEEE Micro; May-Jun2019, Vol. 39 Issue 3, p6-10, 5p

Subject Terms: COMPUTER architecture, ORDER picking systems, MESSAGE authentication codes, PARALLEL computers, RANDOM access memory

A simultaneous multithreading processor architecture with predictable timing behavior.

Authors: Siqueira, Hadley Magno Kreutz, Marcio Eduardo

Source: Design Automation for Embedded Systems; Mar2020, Vol. 24 Issue 1, p45-62, 18p

Subject Terms: SIMULTANEOUS multithreading processors, COMPUTER systems, CYBER physical systems, DETERMINISTIC algorithms, ARCHITECTURAL design, SYSTEMS engineering

Distributed Architecture for Resource Management in Large Scale Grids

Authors: Jeanvoine, Emmanuel Rilling, Louis Morin, Christine et al.

Contributors: Jeanvoine, Emmanuel Rilling, Louis Morin, Christine et al.

Source: https://inria.hal.science/inria-00001066 ; [Research Report] PI 1775, 2006, pp.13.

Subject Terms: Grid computing, distributed system, peer-to-peer overlay networks, resource allocation, self-healing \\ Grille de calcul, système distribué, réseaux logiques pair-à-pair, allocation de ressources, auto-réparation, ACM: C.: Computer Systems Organization/C.2: COMPUTER-COMMUNICATION NETWORKS/C.2.4: Distributed Systems, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.4: Parallel Architectures, [INFO.INFO-OH]Computer Science [cs]/Other [cs.OH]

Relation: Report N°: PI 1775

Availability: https://inria.hal.science/inria-00001066
https://inria.hal.science/inria-00001066v1/document
https://inria.hal.science/inria-00001066v1/file/PI-1775.pdf

Efficient Breadth-First Search on the Cell/BE Processor.

Authors: Scarpazza, Daniele Paolo Villa, Oreste Petrini, Fabrizio

Source: IEEE Transactions on Parallel & Distributed Systems; Oct2008, Vol. 19 Issue 10, p1381-1395, 28p, 3 Black and White Photographs, 5 Charts, 8 Graphs

Subject Terms: MICROPROCESSORS, PARALLEL computer software, COMPUTER software development, BROADBAND communication systems, SOFTWARE architecture, PROGRAM transformation, PARALLEL programs (Computer programs), COMPUTER system design & construction, ALGORITHMS, SYSTEMS software, INTEGRATED circuits, COMPUTER software

Evolvable multi-processor: a novel MPSoC architecture with evolvable task decomposition and scheduling.

Authors: Vakili, S. Fakhraie, S. M. Mohammadi, S.

Source: IET Computers & Digital Techniques (Institution of Engineering & Technology); Mar2010, Vol. 4 Issue 2, p143-156, 14p, 7 Diagrams, 4 Charts, 1 Graph

Subject Terms: SYSTEMS on a chip, COMPUTER systems, COMPUTER engineering, COMPUTER software development, FAULT-tolerant computing

STICKER-IM: A 65 nm Computing-in-Memory NN Processor Using Block-Wise Sparsity Optimization and Inter/Intra-Macro Data Reuse.

Authors: Yue, Jinshan Liu, Yongpan Yuan, Zhe et al.

Source: IEEE Journal of Solid-State Circuits; Aug2022, Vol. 57 Issue 8, p2560-2573, 14p

Subject Terms: MACRO processors, ENERGY consumption, SYSTEM integration, VIDEO coding, ARCHITECTURAL design, COMPUTER architecture

Computer utterances: Sequence and event in digital architecture.

Authors: Miranda, Pablo

Source: International Journal of Architectural Computing; Dec2017, Vol. 15 Issue 4, p268-284, 17p

Subject Terms: ARCHITECTURE & technology, HYPERSURFACE architecture, COMPUTERS in architecture, COMPUTER-aided design, ARCHITECTURAL design

Lightweight Chip Multi-Threading (LCMT): Maximizing Fine-Grained Parallelism On-Chip.

Authors: Li, Sheng Kuntz, Shannon Brockman, Jay et al.

Source: IEEE Transactions on Parallel & Distributed Systems; Jul2011, Vol. 22 Issue 7, p1178-1191, 0p

Subject Terms: INTEGRATED circuits, SIMULTANEOUS multithreading processors, PARALLEL algorithms, SIMULATION methods & models, PERFORMANCE evaluation, MULTICORE processors, SYNCHRONIZATION, COMPUTER software, COMPUTER architecture

Multiprocessor platform-based design for multimedia.

Authors: Ammari, A. C. Jemai, A.

Source: IET Computers & Digital Techniques (Institution of Engineering & Technology); Jan2009, Vol. 3 Issue 1, p52-61, 10p, 5 Diagrams, 2 Charts, 2 Graphs

Subject Terms: EMBEDDED computer systems, ARCHITECTURAL designs, COMPUTER architecture, SYSTEMS design, INTEGRATED circuits, APPLICATION-specific integrated circuits

A Survey on Memory-centric Computer Architectures.

Authors: GEBREGIORGIS, ANTENEH HOANG ANH DU NGUYEN JINTAO YU et al.

Source: ACM Journal on Emerging Technologies in Computing Systems; Oct2022, Vol. 18 Issue 4, p1-50, 50p

Subject Terms: COMPUTER architecture, INTERNET surveys, PARALLEL processing

Towards a New Processor Architecture. ; Vers une nouvelle Architecture de Processeurs

Authors: Vincent, Pierre Landru, Jacques Ecole nationale supérieure Mines-Télécom Lille Douai (IMT Nord Europe) et al.

Contributors: Vincent, Pierre Landru, Jacques Ecole nationale supérieure Mines-Télécom Lille Douai (IMT Nord Europe) et al.

Source: https://hal.science/hal-05117313 ; 2025.

Subject Terms: silicon, parallel, serial, RISC, photonics, computer, optronics, optics, processor, fiber, laser, digital, silicium, parallèle, série, processeur, photonique, ordinateur, optronique, optique, numérique, fibre, ACM: B.: Hardware, ACM: C.: Computer Systems Organization, [INFO]Computer Science [cs], [PHYS]Physics [physics]

Availability: https://hal.science/hal-05117313
https://hal.science/hal-05117313v2/document
https://hal.science/hal-05117313v2/file/frParalSerieRiscV1.pdf

How to solve the current memory access and data transfer bottlenecks: at the processor architecture or at the compiler level?

Authors: Catthoor, F. Dutt, N.D. Kozyrakis, C.E.

Source: Proceedings Design, Automation & Test in Europe Conference & Exhibition 2000 (Cat. No. PR00537); 2000, p426-433, 8p

HPC Systems in the Next Decade – What to Expect, When, Where.

Authors: Doglioni, C. Kim, D. Stewart, G.A. et al.

Source: EPJ Web of Conferences; 11/16/2020, Vol. 245, p1-10, 10p

Subject Terms: HIGH performance computing, COMPUTER architecture, WORKFLOW management, COMPUTER software development, INFORMATION retrieval