Search Results - acm: c.: computer system organisation/c.1: processor architectural/c.1.4: parallel architectural~

HMP-ASIPs: heterogeneous multi-pipeline application-specific instruction-set processors.

Authors: Radhakrishnan, S. Guo, H. Parameswaran, S. et al.

Source: IET Computers & Digital Techniques (Institution of Engineering & Technology); Jan2009, Vol. 3 Issue 1, p94-108, 15p, 13 Diagrams, 4 Charts, 3 Graphs

Subject Terms: COMPUTER architecture, ARCHITECTURAL designs, ARCHITECTURE, INDUSTRIAL design, SET (Computer network protocol)

XPXM/C: a taxonomy of processor coupling techniques.

Authors: Artym, R. Mason, J.S.

Source: IEE Proceedings: Part E: Computers & Digital Techniques; May1988, Vol. 135 Issue 3, p173-180, 8p

A Parallel System Architecture Based on Dynamically Configurable Shared Memory Clusters.

Authors: Tudruj, Marek Masko, Łukasz

Source: Parallel Processing & Applied Mathematics (9783540437925); 2006, p51-61, 11p

Dynamic Thermal Management via Architectural Adaptation.

Authors: Jayaseelan, Ramkumar Mitra, Tulika

Source: DAC: Annual ACM/IEEE Design Automation Conference; Jul2009, p484-489, 6p, 3 Diagrams, 4 Graphs

Subject Terms: INTEGRATED circuit design, INTEGRATED circuit verification, SYSTEMS development, SYSTEMS engineering, COMPUTER systems, PARALLEL programming, TEMPERATURE measurements

Hardware Architectural Support for Control Systems and Sensor Processing.

Authors: VYAS, SUDHANSHU GUPTE, ADWAIT GILL, CHRISTOPHER D. et al.

Source: ACM Transactions on Embedded Computing Systems; Sep2013, Vol. 13 Issue 2, p1-25, 25p

Subject Terms: COMPUTER input-output equipment, COMPUTER architecture, AUTOMATIC control systems, SENSOR networks, DIGITAL signal processing, ALGORITHMS, PID controllers

Micro-architectural simulation of embedded core heterogeneity with gem5 and McPAT

Authors: Endo, F.A. Couroussé, Damien Charles, H.-P. et al.

Contributors: Endo, F.A. Couroussé, Damien Charles, H.-P. et al.

Source: RAPIDO '15 Proceedings of the 2015 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools ; https://cea.hal.science/cea-01818887 ; RAPIDO '15 Proceedings of the 2015 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools, Jan 2015, Amsterdam, Netherlands. ⟨10.1145/2693433.2693440⟩

Subject Terms: ACM: I.: Computing Methodologies/I.6: SIMULATION AND MODELING/I.6.7: Simulation Support Systems, ACM: I.: Computing Methodologies/I.6: SIMULATION AND MODELING/I.6.7: Simulation Support Systems/I.6.7.0: Environments, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.1: Single Data Stream Architectures, [INFO]Computer Science [cs]

Subject Geographic: Amsterdam, Netherlands

Availability: https://cea.hal.science/cea-01818887
https://doi.org/10.1145/2693433.2693440

Processor Design for Soft Errors: Challenges and State of the Art.

Authors: LI, TUO AMBROSE, JUDE ANGELO RAGEL, ROSHAN et al.

Source: ACM Computing Surveys; Dec2016, Vol. 49 Issue 3, p1-44, 44p, 3 Diagrams, 4 Charts, 1 Graph

Subject Terms: SOFT errors, MICROPROCESSOR design & construction, ERROR rates, COMPUTER architecture, DATA, ERROR detection (Information theory)

Synchronisation and Load Balancing for Parallel Hierarchical Radiosity of Complex Scenes on a Heterogeneous Computer Network.

Authors: Meneveaux, Daniel Bouatouch, Kadi

Source: Computer Graphics Forum; Dec99, Vol. 18 Issue 4, p201, 12p, 1 Black and White Photograph, 7 Charts

Subject Terms: RADIOSITY, PARALLEL algorithms, COMPUTER networks

Using an Architectural Knowledge Base to Generate Code for Parallel Computers.

Authors: McGregor, John D. Riehl, Arthur M. Terrano, Anthony E. et al.

Source: Communications of the ACM; Sep89, Vol. 32 Issue 9, p1065-1072, 8p, 8 Diagrams

Subject Terms: PARALLEL computers, PROGRAMMING languages, ARTIFICIAL intelligence, COMPUTERS, COMPUTER software, SOURCE code

A simultaneous multithreading processor architecture with predictable timing behavior.

Authors: Siqueira, Hadley Magno Kreutz, Marcio Eduardo

Source: Design Automation for Embedded Systems; Mar2020, Vol. 24 Issue 1, p45-62, 18p

Subject Terms: SIMULTANEOUS multithreading processors, COMPUTER systems, CYBER physical systems, DETERMINISTIC algorithms, ARCHITECTURAL design, SYSTEMS engineering

A Novel Approach to Multiagent based Scheduling for Multicore Architecture.

Authors: Muneeswari, G. Ahila, A. Sobitha Shunmuganathan, K. L.

Source: GSTF Journal on Computing; 2011, Vol. 1 Issue 2, p184-189, 6p

Subject Terms: MULTICORE processors, PARALLEL computers, COMPUTER operating systems, MULTIAGENT systems, ALGORITHMS

VirtualSoC: A Research Tool for Modern MPSoCs.

Authors: BORTOLOTTI, DANIELE MARONGIU, ANDREA BENINI, LUCA

Source: ACM Transactions on Embedded Computing Systems; Oct2016, Vol. 16 Issue 1, p1-27, 27p

Subject Terms: COMPUTER system design & construction, HIGH performance computing, EMBEDDED computer systems, COMPUTER simulation, COMPUTER operating systems, CENTRAL processing units

Exploiting Timing Error Resilience in Processor Architecture.

Authors: SARTORI, JOHN KUMAR, RAKESH

Source: ACM Transactions on Embedded Computing Systems; May2013 Supplement 2, Vol. 12, p1-25, 25p

Subject Terms: COMPLEMENTARY metal oxide semiconductor design & construction, MACRO processors, COMPUTER architecture, ERROR rates, ERRORS, MOORE'S law, INDUSTRIAL costs

STICKER-IM: A 65 nm Computing-in-Memory NN Processor Using Block-Wise Sparsity Optimization and Inter/Intra-Macro Data Reuse.

Authors: Yue, Jinshan Liu, Yongpan Yuan, Zhe et al.

Source: IEEE Journal of Solid-State Circuits; Aug2022, Vol. 57 Issue 8, p2560-2573, 14p

Subject Terms: MACRO processors, ENERGY consumption, SYSTEM integration, VIDEO coding, ARCHITECTURAL design, COMPUTER architecture

All-optical Linear Array with a Reconfigurable Pipelined Bus System (OLARPBS) optical bus parallel computing model.

Authors: d'Auriol, Brian

Source: Journal of Supercomputing; Feb2016, Vol. 72 Issue 2, p753-769, 17p

Subject Terms: ADAPTIVE computing systems, PARALLEL algorithms, COMPUTER scheduling, COMPUTER buses, ELECTRONIC data processing, INFORMATION storage & retrieval systems

Architectural support for task scheduling: hardware scheduling for dataflow on NUMA systems.

Authors: Khan, Behram Goodman, Daniel Khan, Salman et al.

Source: Journal of Supercomputing; Jun2015, Vol. 71 Issue 6, p2309-2338, 30p

Subject Terms: DATA flow computing, NON-uniform memory access, COMPUTER software, QUEUEING networks, FIRST in, first out (Queuing theory)

Efficient Breadth-First Search on the Cell/BE Processor.

Authors: Scarpazza, Daniele Paolo Villa, Oreste Petrini, Fabrizio

Source: IEEE Transactions on Parallel & Distributed Systems; Oct2008, Vol. 19 Issue 10, p1381-1395, 28p, 3 Black and White Photographs, 5 Charts, 8 Graphs

Subject Terms: MICROPROCESSORS, PARALLEL computer software, COMPUTER software development, BROADBAND communication systems, SOFTWARE architecture, PROGRAM transformation, PARALLEL programs (Computer programs), COMPUTER system design & construction, ALGORITHMS, SYSTEMS software, INTEGRATED circuits, COMPUTER software

Reliability aware throughput management of chip multi-processor architecture via thread migration.

Authors: Pouyan, Fatemeh Azarpeyvand, Ali Safari, Saeed et al.

Source: Journal of Supercomputing; Apr2016, Vol. 72 Issue 4, p1363-1380, 18p

Subject Terms: SIMULTANEOUS multithreading processors, COMPUTER architecture, SOFT errors, MINIATURE electronic equipment, PARALLEL processing, MULTIPROCESSORS

Analysis of a parallel grace hash join implementation on The Cell Processor.

Authors: Mach, Werner Schikuta, Erich Pittl, Benedikt

Source: 2014 International Conference on High Performance Computing & Simulation (HPCS); 2014, p1018-1022, 5p

Evolvable multi-processor: a novel MPSoC architecture with evolvable task decomposition and scheduling.

Authors: Vakili, S. Fakhraie, S. M. Mohammadi, S.

Source: IET Computers & Digital Techniques (Institution of Engineering & Technology); Mar2010, Vol. 4 Issue 2, p143-156, 14p, 7 Diagrams, 4 Charts, 1 Graph

Subject Terms: SYSTEMS on a chip, COMPUTER systems, COMPUTER engineering, COMPUTER software development, FAULT-tolerant computing