Výsledky vyhledávání - acm: c.: computer system organisation/c.1: processor architectural*

Micro-architectural simulation of embedded core heterogeneity with gem5 and McPAT

Autoři: Endo, F.A. Couroussé, Damien Charles, H.-P. a další

Přispěvatelé: Endo, F.A. Couroussé, Damien Charles, H.-P. a další

Zdroj: RAPIDO '15 Proceedings of the 2015 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools ; https://cea.hal.science/cea-01818887 ; RAPIDO '15 Proceedings of the 2015 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools, Jan 2015, Amsterdam, Netherlands. ⟨10.1145/2693433.2693440⟩

Témata: ACM: I.: Computing Methodologies/I.6: SIMULATION AND MODELING/I.6.7: Simulation Support Systems, ACM: I.: Computing Methodologies/I.6: SIMULATION AND MODELING/I.6.7: Simulation Support Systems/I.6.7.0: Environments, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.1: Single Data Stream Architectures, [INFO]Computer Science [cs]

Geografické téma: Amsterdam, Netherlands

Dostupnost: https://cea.hal.science/cea-01818887
https://doi.org/10.1145/2693433.2693440

Processor Design for Soft Errors: Challenges and State of the Art.

Autoři: LI, TUO AMBROSE, JUDE ANGELO RAGEL, ROSHAN a další

Zdroj: ACM Computing Surveys; Dec2016, Vol. 49 Issue 3, p1-44, 44p, 3 Diagrams, 4 Charts, 1 Graph

Témata: SOFT errors, MICROPROCESSOR design & construction, ERROR rates, COMPUTER architecture, DATA, ERROR detection (Information theory)

XPXM/C: a taxonomy of processor coupling techniques.

Autoři: Artym, R. Mason, J.S.

Zdroj: IEE Proceedings: Part E: Computers & Digital Techniques; May1988, Vol. 135 Issue 3, p173-180, 8p

Hardware Architectural Support for Control Systems and Sensor Processing.

Autoři: VYAS, SUDHANSHU GUPTE, ADWAIT GILL, CHRISTOPHER D. a další

Zdroj: ACM Transactions on Embedded Computing Systems; Sep2013, Vol. 13 Issue 2, p1-25, 25p

Témata: COMPUTER input-output equipment, COMPUTER architecture, AUTOMATIC control systems, SENSOR networks, DIGITAL signal processing, ALGORITHMS, PID controllers

HMP-ASIPs: heterogeneous multi-pipeline application-specific instruction-set processors.

Autoři: Radhakrishnan, S. Guo, H. Parameswaran, S. a další

Zdroj: IET Computers & Digital Techniques (Institution of Engineering & Technology); Jan2009, Vol. 3 Issue 1, p94-108, 15p, 13 Diagrams, 4 Charts, 3 Graphs

Témata: COMPUTER architecture, ARCHITECTURAL designs, ARCHITECTURE, INDUSTRIAL design, SET (Computer network protocol)

Exploiting Timing Error Resilience in Processor Architecture.

Autoři: SARTORI, JOHN KUMAR, RAKESH

Zdroj: ACM Transactions on Embedded Computing Systems; May2013 Supplement 2, Vol. 12, p1-25, 25p

Témata: COMPLEMENTARY metal oxide semiconductor design & construction, MACRO processors, COMPUTER architecture, ERROR rates, ERRORS, MOORE'S law, INDUSTRIAL costs

STICKER-IM: A 65 nm Computing-in-Memory NN Processor Using Block-Wise Sparsity Optimization and Inter/Intra-Macro Data Reuse.

Autoři: Yue, Jinshan Liu, Yongpan Yuan, Zhe a další

Zdroj: IEEE Journal of Solid-State Circuits; Aug2022, Vol. 57 Issue 8, p2560-2573, 14p

Témata: MACRO processors, ENERGY consumption, SYSTEM integration, VIDEO coding, ARCHITECTURAL design, COMPUTER architecture

Architectural Frameworks for Security and Reliability of MPSoCs.

Autoři: Patel, Krutartha Parameswaran, Sri Ragel, Roshan G.

Zdroj: IEEE Transactions on Very Large Scale Integration (VLSI) Systems; Sep2011, Vol. 19 Issue 9, p1641-1654, 14p

Témata: INTEGRATED circuit design, MULTIPROCESSORS, INTEGRATED passive components, RELIABILITY in engineering, APPLICATION-specific integrated circuits, COMPUTER software security, COMPUTER architecture, APPLICATION software

Scalable techniques for system-level cosimulation and coestimation.

Autoři: Lajolo, M. Passerone, C. Lavagno, L.

Zdroj: IEE Proceedings -- Computers & Digital Techniques; Jul2003, Vol. 150 Issue 4, p227, 12p

Témata: COMPUTER simulation, COMPUTER software, COMPUTER engineering

System-on-chip implementation of the whole advanced encryption standard processor using reduced XOR-based sum-of-product operations.

Autoři: Hsiao, S.-F. Chen, M.-C. Tsai, M.-Y a další

Zdroj: IEE Proceedings -- Information Security; Oct2005, Vol. 152 Issue 1, p21-30, 10p, 4 Diagrams, 6 Charts

Témata: COMPUTER input-output equipment, SYSTEMS design, ALGORITHMS, DATA protection, ARRAY processors, APPLICATION-specific integrated circuits

Predictive Thermal Management for Chip Multiprocessors Using Co-designed Virtual Machines

Autoři: Khan, Omer Kundu, Sandip Department of Electrical and Computer Engineering - University of Massachusetts (ECE) a další

Přispěvatelé: Khan, Omer Kundu, Sandip Department of Electrical and Computer Engineering - University of Massachusetts (ECE) a další

Zdroj: HiPEAC 2009 - High Performance and Embedded Architectures and Compilers ; https://hal.inria.fr/inria-00446303 ; HiPEAC 2009 - High Performance and Embedded Architectures and Compilers, Jan 2009, Paphos, Cyprus. ⟨10.1007/978-3-540-92990-1_22⟩

Témata: ACM: B.: Hardware/B.2: ARITHMETIC AND LOGIC STRUCTURES, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES, ACM: D.: Software/D.3: PROGRAMMING LANGUAGES/D.3.4: Processors, [INFO.INFO-OH]Computer Science [cs]/Other [cs.OH], [INFO.INFO-ES]Computer Science [cs]/Embedded Systems

Geografické téma: Paphos, Cyprus

Relation: inria-00446303; https://hal.inria.fr/inria-00446303

Dostupnost: https://hal.inria.fr/inria-00446303
https://doi.org/10.1007/978-3-540-92990-1_22

Development an efficient AXI-interconnect unit between set of customized peripheral devices and an implemented dual-core RISC-V processor.

Autoři: Emil, Demyana Hamdy, Mohammed Nagib, Gihan

Zdroj: Journal of Supercomputing; Oct2023, Vol. 79 Issue 15, p17000-17019, 20p

Témata: TELECOMMUNICATION equipment, COMPUTER systems, ARCHITECTURAL design, MULTICORE processors, TAIGAS, CACHE memory

A Framework for Task Scheduling and Memory Partitioning for Multi-Processor System-on-Chip

Autoři: Salamy, Hassan Ramanujam, J. Department of Electrical and Computer Engineering - Louisiana State University (ECE) a další

Přispěvatelé: Salamy, Hassan Ramanujam, J. Department of Electrical and Computer Engineering - Louisiana State University (ECE) a další

Zdroj: HiPEAC 2009 - High Performance and Embedded Architectures and Compilers ; https://hal.inria.fr/inria-00446288 ; HiPEAC 2009 - High Performance and Embedded Architectures and Compilers, Jan 2009, Paphos, Cyprus. ⟨10.1007/978-3-540-92990-1_20⟩

Témata: ACM: B.: Hardware/B.2: ARITHMETIC AND LOGIC STRUCTURES, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES, ACM: D.: Software/D.3: PROGRAMMING LANGUAGES/D.3.4: Processors, [INFO.INFO-OH]Computer Science [cs]/Other [cs.OH], [INFO.INFO-ES]Computer Science [cs]/Embedded Systems

Geografické téma: Paphos, Cyprus

Relation: inria-00446288; https://hal.inria.fr/inria-00446288

Dostupnost: https://hal.inria.fr/inria-00446288
https://doi.org/10.1007/978-3-540-92990-1_20

Architectural considerations for a self-timed decoupled processor.

Autoři: Richardson, W.F. Brunvand, E.

Zdroj: IEE Proceedings -- Computers & Digital Techniques; Sep1996, Vol. 143 Issue 5, p251-257, 7p

Scheduling issues on thermally-constrained processors

Autoři: Michaud, Pierre Sazeides, Yiannakis Compilation, parallel architectures and system (CAPS) a další

Přispěvatelé: Michaud, Pierre Sazeides, Yiannakis Compilation, parallel architectures and system (CAPS) a další

Zdroj: https://inria.hal.science/inria-00110507 ; [Research Report] PI 1822, 2006, pp.19.

Témata: Multi-core processor, temperature, thread scheduling, time slice, activity migration, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

Relation: Report N°: PI 1822

Dostupnost: https://inria.hal.science/inria-00110507
https://inria.hal.science/inria-00110507/document
https://inria.hal.science/inria-00110507/file/PI-1822.pdf

Communication Based Proactive Link Power Management

Autoři: Muralidhara, Sai Prashanth Kandemir, Mahmut Department of Computer Science and Engineering University Park a další

Přispěvatelé: Muralidhara, Sai Prashanth Kandemir, Mahmut Department of Computer Science and Engineering University Park a další

Zdroj: HiPEAC 2009 - High Performance and Embedded Architectures and Compilers ; https://hal.inria.fr/inria-00445984 ; HiPEAC 2009 - High Performance and Embedded Architectures and Compilers, Jan 2009, Paphos, Cyprus. ⟨10.1007/978-3-540-92990-1_16⟩

Témata: ACM: B.: Hardware/B.2: ARITHMETIC AND LOGIC STRUCTURES, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES, ACM: D.: Software/D.3: PROGRAMMING LANGUAGES/D.3.4: Processors, [INFO.INFO-OH]Computer Science [cs]/Other [cs.OH], [INFO.INFO-ES]Computer Science [cs]/Embedded Systems

Geografické téma: Paphos, Cyprus

Relation: inria-00445984; https://hal.inria.fr/inria-00445984

Dostupnost: https://hal.inria.fr/inria-00445984
https://doi.org/10.1007/978-3-540-92990-1_16

Teaching computer architecture by designing and simulating processors from their bits and bytes.

Autoři: Doğan, Mustafa Öztoprak, Kasım Tolun, Mehmet Reşit

Zdroj: PeerJ Computer Science; Feb2024, p1-25, 25p

Témata: COMPUTER architecture, COMPUTER engineering, ARCHES, ARCHITECTURAL design, VERILOG (Computer hardware description language), COMPUTER hardware description languages, MICROPROCESSORS

Architectural and Protocol Exploration for 3D Optical Network-on-Chip ; Exploration architecturale et protocolaire pour un réseaux 3D optique sur puce

Autoři: Luo, Jiating Energy Efficient Computing ArchItectures with Embedded Reconfigurable Resources (CAIRN) Inria Rennes – Bretagne Atlantique a další

Přispěvatelé: Luo, Jiating Energy Efficient Computing ArchItectures with Embedded Reconfigurable Resources (CAIRN) Inria Rennes – Bretagne Atlantique a další

Zdroj: https://inria.hal.science/tel-01956255 ; Hardware Architecture [cs.AR]. Université de Rennes 1 [UR1], 2018. English. ⟨NNT : ⟩.

Témata: Network on chip NoC, Réseau sur puce NoC, ACM: C.: Computer Systems Organization/C.2: COMPUTER-COMMUNICATION NETWORKS/C.2.1: Network Architecture and Design, ACM: D.: Software/D.4: OPERATING SYSTEMS, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [INFO.INFO-ET]Computer Science [cs]/Emerging Technologies [cs.ET]

Dostupnost: https://inria.hal.science/tel-01956255
https://inria.hal.science/tel-01956255v1/document
https://inria.hal.science/tel-01956255v1/file/These_Jiating_fin.pdf

Periodic activity migration for fast sequential execution in future heterogeneous multicore processors

Autoři: Michaud, Pierre Compilation, parallel architectures and system (CAPS) Institut de Recherche en Informatique et Systèmes Aléatoires (IRISA) a další

Přispěvatelé: Michaud, Pierre Compilation, parallel architectures and system (CAPS) Institut de Recherche en Informatique et Systèmes Aléatoires (IRISA) a další

Zdroj: https://inria.hal.science/inria-00340566 ; [Research Report] PI 1909, 2008, pp.20.

Témata: Heterogeneous multicore processor, power consumption, heat flux, periodic activity migration, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

Relation: Report N°: PI 1909

Dostupnost: https://inria.hal.science/inria-00340566
https://inria.hal.science/inria-00340566/document
https://inria.hal.science/inria-00340566/file/PI-1909.pdf

Scheduling Analysis from Architectural Models of Embedded Multi-Processor Systems

Autoři: Rubini, Stéphane Fotsing, Christian Singhoff, Frank a další

Přispěvatelé: Rubini, Stéphane Fotsing, Christian Singhoff, Frank a další

Zdroj: ISSN: 1551-3688 ; ACM SIGBED Review ; https://hal.univ-brest.fr/hal-00983407 ; ACM SIGBED Review, 2014, 11 (1.

Témata: [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [INFO.INFO-ES]Computer Science [cs]/Embedded Systems

Dostupnost: https://hal.univ-brest.fr/hal-00983407
https://hal.univ-brest.fr/hal-00983407v1/document
https://hal.univ-brest.fr/hal-00983407v1/file/ewili.pdf