Search Results - acm: c.: computer (systems OR system) organization/c.1: processor architecture

1

COCOR: Training and Assessing Rotation Invariance in Object and Human (Pose) Detection Tasks

Authors: Ly, Rottana Vaufreydaz, Dominique Castelli, Eric et al.

Contributors: Ly, Rottana Vaufreydaz, Dominique Castelli, Eric et al.

Source: The 13th Conference on Information Technology and its Applications (CITA2024)
The 13th Conference on Information Technology and its Applications (CITA2024), Jul 2024, Da Nang City, Vietnam

Subject Terms: Pose detection, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.3: Other Architecture Styles/C.1.3.7: Neural nets, Object detection, Rotation invariance evaluation, ACM: I.: Computing Methodologies/I.5: PATTERN RECOGNITION/I.5.4: Applications/I.5.4.0: Computer vision, [INFO]Computer Science [cs], Human detection, [INFO.INFO-AI]Computer Science [cs]/Artificial Intelligence [cs.AI]

Access URL: https://hal.science/hal-04706818

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2

Survey of Models and Architectures to Ensure Linked Data Access

Authors: Toure, Mahamadou Gandon, Fabien Guidedi, Kaladzavi et al.

Contributors: Toure, Mahamadou Gandon, Fabien Guidedi, Kaladzavi et al.

Source: https://inria.hal.science/hal-03956456 ; Inria & Université Côte d'Azur, CNRS, I3S. 2023, pp.23.

Subject Terms: Web of Data, Gossip protocol, graph replication, limited connectivity, semantic overlay, mobile contributor, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.4: Parallel Architectures/C.1.4.0: Distributed architectures, ACM: I.: Computing Methodologies/I.2: ARTIFICIAL INTELLIGENCE/I.2.4: Knowledge Representation Formalisms and Methods, [INFO.INFO-DS]Computer Science [cs]/Data Structures and Algorithms [cs.DS]

Availability: https://inria.hal.science/hal-03956456
https://inria.hal.science/hal-03956456v1/document
https://inria.hal.science/hal-03956456v1/file/MahamadouToureSurvey.pdf

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3

Parameter Exploration to Improve Performance of Memristor-Based Neuromorphic Architectures

Authors: Mahyar Shahsavari Pierre Boulet Boulet, Pierre et al.

Contributors: Mahyar Shahsavari Pierre Boulet Boulet, Pierre et al.

Source: IEEE Transactions on Multi-Scale Computing Systems. 4:833-846

File Description: application/pdf

Access URL: https://hal.archives-ouvertes.fr/hal-01615032/file/TMSCSSI-2016-10-0051.R1-main.pdf
https://ieeexplore.ieee.org/document/8063353
https://hal.archives-ouvertes.fr/hal-01615032/document
https://jglobal.jst.go.jp/en/detail?JGLOBAL_ID=201902258056300336
https://dblp.uni-trier.de/db/journals/tmscs/tmscs4.html#ShahsavariB18
https://hal.archives-ouvertes.fr/hal-01615032
https://hal.science/hal-01615032v1/document
https://hal.science/hal-01615032v1
https://doi.org/10.1109/tmscs.2017.2761231

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4

TBES: Template-Based Exploration and Synthesis of Heterogeneous Multiprocessor Architectures on FPGA

Authors: Corre, Youenn Diguet, Jean-Philippe Heller, Dominique et al.

Contributors: Corre, Youenn Diguet, Jean-Philippe Heller, Dominique et al.

Source: ACM Transactions on Embedded Computing Systems. 15:1-27

Subject Terms: [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES, 13. Climate action, Electronic System Level, 0202 electrical engineering, electronic engineering, information engineering, ACM: B.: Hardware/B.5: REGISTER-TRANSFER-LEVEL IMPLEMENTATION, Multiprocessor, 02 engineering and technology, High-Level Synthesis, ACM: D.: Software/D.2: SOFTWARE ENGINEERING/D.2.2: Design Tools and Techniques, System-on-Chip

Access URL: https://hal.archives-ouvertes.fr/hal-01172103/document
https://dblp.uni-trier.de/db/journals/tecs/tecs15.html#CorreDHBL16
https://hal.archives-ouvertes.fr/hal-01172103
https://dl.acm.org/doi/10.1145/2816817
https://doi.org/10.1145/2816817

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5

ALIBERT: A PRETRAINED LANGUAGE MODEL FOR FRENCH BIOMEDICAL TEXT ; AliBERT: UN MODÈLE DE LANGAGE PRÉ-ENTRAÎNÉ POUR LES TEXTES BIOMÉDICAUX EN FRANÇAIS

Authors: Berhe, Aman Draznieks, Guillaume Martenot, Vincent et al.

Contributors: Berhe, Aman Draznieks, Guillaume Martenot, Vincent et al.

Source: https://hal.science/hal-03911564 ; 2023.

Subject Terms: ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.3: Other Architecture Styles/C.1.3.7: Neural nets, ACM: F.: Theory of Computation/F.1: COMPUTATION BY ABSTRACT DEVICES/F.1.1: Models of Computation, ACM: F.: Theory of Computation/F.1: COMPUTATION BY ABSTRACT DEVICES/F.1.1: Models of Computation/F.1.1.4: Self-modifying machines (e.g., neural networks), ACM: I.: Computing Methodologies/I.2: ARTIFICIAL INTELLIGENCE, ACM: I.: Computing Methodologies/I.2: ARTIFICIAL INTELLIGENCE/I.2.4: Knowledge Representation Formalisms and Methods, ACM: I.: Computing Methodologies/I.2: ARTIFICIAL INTELLIGENCE/I.2.6: Learning, ACM: I.: Computing Methodologies/I.2: ARTIFICIAL INTELLIGENCE/I.2.7: Natural Language Processing, ACM: I.: Computing Methodologies/I.6: SIMULATION AND MODELING/I.6.5: Model Development, ACM: I.: Computing Methodologies/I.7: DOCUMENT AND TEXT PROCESSING, [INFO.INFO-AI]Computer Science [cs]/Artificial Intelligence [cs.AI], [INFO.INFO-BI]Computer Science [cs]/Bioinformatics [q-bio.QM], [INFO.INFO-CL]Computer Science [cs]/Computation and Language [cs.CL], [INFO.INFO-LG]Computer Science [cs]/Machine Learning [cs.LG], [INFO.INFO-TT]Computer Science [cs]/Document and Text Processing

Availability: https://hal.science/hal-03911564
https://hal.science/hal-03911564v2/document
https://hal.science/hal-03911564v2/file/AliBERT_HAL_V2.pdf

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6

Impact of Increasing Number of Neurons on Performance of Neuromorphic Architecture

Authors: Shahsavari, Mahyar Boulet, Pierre Shahbahrami, Asadollah et al.

Contributors: Shahsavari, Mahyar Boulet, Pierre Shahbahrami, Asadollah et al.

Source: CADS 2017 - 19th CSI International Symposium on Computer Architecture & Digital Systems ; https://hal.science/hal-01633418 ; CADS 2017 - 19th CSI International Symposium on Computer Architecture & Digital Systems, Dec 2017, Kish, Iran

Subject Terms: ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.3: Other Architecture Styles/C.1.3.7: Neural nets, ACM: I.: Computing Methodologies/I.5: PATTERN RECOGNITION, [INFO.INFO-NE]Computer Science [cs]/Neural and Evolutionary Computing [cs.NE], [INFO.INFO-CV]Computer Science [cs]/Computer Vision and Pattern Recognition [cs.CV], [INFO.INFO-AI]Computer Science [cs]/Artificial Intelligence [cs.AI]

Subject Geographic: Kish, Iran

Availability: https://hal.science/hal-01633418
https://hal.science/hal-01633418v1/document
https://hal.science/hal-01633418v1/file/Sub61_shahsavari_CADS17.pdf

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7

EdgeMORE: improving resource allocation with multiple options from tenants

Authors: Araldo, Andrea Stefano, Alessandro, Di Di Stefano, Antonella et al.

Contributors: Araldo, Andrea Stefano, Alessandro, Di Di Stefano, Antonella et al.

Source: CCNC 2020: 17th Consumer Communications & Networking Conference ; https://hal.science/hal-02459433 ; CCNC 2020: 17th Consumer Communications & Networking Conference, Jan 2020, Las Vegas, United States. pp.1-6, ⟨10.1109/CCNC46108.2020.9045173⟩

Subject Terms: Cloud-edge offloading, Resource allocation, Edge computing, ACM: C.: Computer Systems Organization/C.2: COMPUTER-COMMUNICATION NETWORKS/C.2.1: Network Architecture and Design/C.2.1.3: Distributed networks, ACM: C.: Computer Systems Organization/C.2: COMPUTER-COMMUNICATION NETWORKS/C.2.4: Distributed Systems, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.4: Parallel Architectures/C.1.4.0: Distributed architectures, [INFO.INFO-NI]Computer Science [cs]/Networking and Internet Architecture [cs.NI]

Subject Geographic: Las Vegas, United States

Availability: https://hal.science/hal-02459433
https://hal.science/hal-02459433v1/document
https://hal.science/hal-02459433v1/file/_CCNC2020__EdgeMore_mproving_resource_allocation_with_multiple_options_from_tenants.pdf
https://doi.org/10.1109/CCNC46108.2020.9045173

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8

Design and Implementation of the CloudMdsQL Multistore System

Authors: Kolev, Boyan Bondiombouy, Carlyna Levchenko, Oleksandra et al.

Contributors: Kolev, Boyan Bondiombouy, Carlyna Levchenko, Oleksandra et al.

Source: 6th International Conference on Cloud Computing and Services Science
CLOSER: Cloud Computing and Services Science
https://hal-lirmm.ccsd.cnrs.fr/lirmm-01341172
CLOSER: Cloud Computing and Services Science, Apr 2016, Roma, Italy. pp.352-359, ⟨10.5220/0005923803520359⟩
http://closer.scitevents.org/DataDiversityConvergence.aspx?y=2016

Subject Terms: SQL and NoSQL Integration, Heterogeneous Data Stores, Multistore System, Cloud, ACM: H.: Information Systems/H.2: DATABASE MANAGEMENT/H.2.5: Heterogeneous Databases, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.4: Parallel Architectures/C.1.4.0: Distributed architectures, [INFO.INFO-DB]Computer Science [cs]/Databases [cs.DB]

Subject Geographic: Roma, Italy

Relation: info:eu-repo/grantAgreement//611068/EU/A Coherent and Rich PaaS with a Common Programming Model/CoherentPaaS

Availability: https://hal-lirmm.ccsd.cnrs.fr/lirmm-01341172
https://hal-lirmm.ccsd.cnrs.fr/lirmm-01341172v1/document
https://hal-lirmm.ccsd.cnrs.fr/lirmm-01341172v1/file/closer2016.pdf
https://doi.org/10.5220/0005923803520359

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9

Embedded Runtime for Reconfigurable Dataflow Graphs on Manycore Architectures

Authors: Miomandre, Hugo Hascoët, Julien Desnos, Karol et al.

Contributors: Miomandre, Hugo Hascoët, Julien Desnos, Karol et al.

Source: PARMA-DITAM ; https://hal.science/hal-01704702 ; PARMA-DITAM, Jan 2018, Manchester, United Kingdom. ⟨10.1145/3183767.3183780⟩

Subject Terms: ACM: C.: Computer Systems Organization, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.4: Parallel Architectures, [INFO.INFO-ES]Computer Science [cs]/Embedded Systems

Subject Geographic: Manchester, United Kingdom

Availability: https://hal.science/hal-01704702
https://hal.science/hal-01704702v1/document
https://hal.science/hal-01704702v1/file/parma-ditam18.pdf
https://doi.org/10.1145/3183767.3183780

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10

Multi-objective scheduling of Scientific Workflows in multisite clouds

Authors: Liu, Ji Pacitti, Esther Valduriez, Patrick et al.

Contributors: Liu, Ji Pacitti, Esther Valduriez, Patrick et al.

Source: Recercat. Dipósit de la Recerca de Catalunya
instname
UPCommons. Portal del coneixement obert de la UPC
Universitat Politècnica de Catalunya (UPC)

Subject Terms: multi-objective scheduling, Multisite cloud, [INFO.INFO-DB]Computer Science [cs]/Databases [cs.DB], Parallel processing (Electronic computers), Processament en paral·lel (Ordinadors), Enginyeria electrònica [Àrees temàtiques de la UPC], Scientific workflow, Workflow computing systems, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.4: Parallel Architectures/C.1.4.0: Distributed architectures, 02 engineering and technology, Cicle de treball, Scientific workflow management system, multisite cloud, Multi-objective scheduling, 0202 electrical engineering, electronic engineering, information engineering, [INFO.INFO-DB] Computer Science [cs]/Databases [cs.DB], Algorismes computacionals, parallel execution, Algorithms and architectures for advanced scientific computing, Àrees temàtiques de la UPC::Enginyeria electrònica, scientific workflow management system, Parallel execution

File Description: application/pdf

Access URL: https://upcommons.upc.edu/bitstream/2117/95941/1/Multi-objective%20scheduling%20of%20scientific%20workflows%20in%20Multisite.pdf
http://hdl.handle.net/2117/95941
https://upcommons.upc.edu/handle/2117/95941
https://core.ac.uk/display/81576844
https://www.sciencedirect.com/science/article/pii/S0167739X16300917
https://dblp.uni-trier.de/db/journals/fgcs/fgcs63.html#LiuPVOM16
https://hal-lirmm.ccsd.cnrs.fr/lirmm-01342203/document
https://hal.archives-ouvertes.fr/lirmm-01342203

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11

Supporting Runtime Reconfigurable VLIWs Cores Through Dynamic Binary Translation

Authors: Rokicki, Simon Rohou, Erven Derrien, Steven et al.

Contributors: Rokicki, Simon Rohou, Erven Derrien, Steven et al.

Source: DATE 2018 - IEEE/ACM Design, Automation & Test in Europe Conference & Exhibition ; https://hal.science/hal-01653110 ; DATE 2018 - IEEE/ACM Design, Automation & Test in Europe Conference & Exhibition, Mar 2018, Dresden, Germany. pp.1009-1014, ⟨10.23919/DATE.2018.8342160⟩ ; https://www.date-conference.com

Subject Terms: ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.3: Other Architecture Styles/C.1.3.5: Heterogeneous (hybrid) systems, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.3: Other Architecture Styles/C.1.3.0: Adaptable architectures, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.2: Multiple Data Stream Architectures (Multiprocessors)/C.1.2.4: Multiple-instruction-stream, multiple-data-stream processors (MIMD), ACM: D.: Software/D.3: PROGRAMMING LANGUAGES/D.3.4: Processors/D.3.4.0: Code generation, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [INFO.INFO-ES]Computer Science [cs]/Embedded Systems

Subject Geographic: Dresden, Germany

Availability: https://hal.science/hal-01653110
https://hal.science/hal-01653110v2/document
https://hal.science/hal-01653110v2/file/rokicki_18_hal.pdf
https://doi.org/10.23919/DATE.2018.8342160

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12

NoC-Based Protection for SoC Time-Driven Attacks

Authors: Sepulveda, Martha Johanna Diguet, Jean-Philippe Strum, Marius et al.

Contributors: Sepulveda, Martha Johanna Diguet, Jean-Philippe Strum, Marius et al.

Source: IEEE Embedded Systems Letters. 7:7-10

Subject Terms: ACM: B.: Hardware/B.7: INTEGRATED CIRCUITS, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], Channel leakage, multiport memory, common bus, ACM: B.: Hardware/B.7: INTEGRATED CIRCUITS/B.7.1: Types and Design Styles/B.7.1.7: VLSI (very large scale integration), 02 engineering and technology, 3. Good health, Network On Chip, crossbar switch), Security, 0202 electrical engineering, electronic engineering, information engineering, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.2: Multiple Data Stream Architectures (Multiprocessors)/C.1.2.3: Interconnection architectures (e.g, [SPI.SIGNAL]Engineering Sciences [physics]/Signal and Image processing, [SPI.SIGNAL] Engineering Sciences [physics]/Signal and Image processing

Access URL: https://hal.archives-ouvertes.fr/hal-01083270
http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6994256
https://hal.inria.fr/hal-01253500
http://ieeexplore.ieee.org/document/6994256
https://ieeexplore.ieee.org/document/6994256
https://dblp.uni-trier.de/db/journals/esl/esl7.html#SepulvedaDSG15

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13

Covariance tracking: architecture optimizations for embedded systems

Authors: Romero, Andrés Lacassagne, Lionel Gouiffès, Michèle et al.

Contributors: Romero, Andrés Lacassagne, Lionel Gouiffès, Michèle et al.

Source: ISSN: 1687-6172.

Availability: https://inria.hal.science/hal-01094903
https://inria.hal.science/hal-01094903v1/document
https://inria.hal.science/hal-01094903v1/file/Eurasip%202014-12.pdf
https://doi.org/10.1186/1687-6180-2014-175

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14

Security and Safety Concerns in Air Taxis: A Systematic Literature Review

Authors: Isadora Garcia Ferrão David Espes Catherine Dezan et al.

Contributors: Isadora Garcia Ferrão David Espes Catherine Dezan et al.

Source: Sensors (Basel)
Sensors, Vol 22, Iss 18, p 6875 (2022)
Sensors; Volume 22; Issue 18; Pages: 6875

Subject Terms: ACM: C.: Computer Systems Organization/C.2: COMPUTER-COMMUNICATION NETWORKS/C.2.4: Distributed Systems, air taxi architecture, Aircraft, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.4: Parallel Architectures/C.1.4.1: Mobile processors, Chemical technology, 05 social sciences, TP1-1185, Article, [INFO.INFO-MC]Computer Science [cs]/Mobile Computing, [INFO.INFO-CR]Computer Science [cs]/Cryptography and Security [cs.CR], air taxi security, air taxi safety, 11. Sustainability, 0502 economics and business, Humans, Safety

File Description: application/pdf

Access URL: https://pubmed.ncbi.nlm.nih.gov/36146224
https://doaj.org/article/6ede3995254045d2ae6cd72c94932ffc

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15

EEA-Aware For Large-Scale Scientific Applications On Heterogeneous Architectures

Authors: Garcia Henao, John Anderson, John Anderson Garcia Henao Hernandez, Esteban Navaux, Philippe, O.A. et al.

Contributors: Garcia Henao, John Anderson, John Anderson Garcia Henao Hernandez, Esteban Navaux, Philippe, O.A. et al.

Source: ACM Student Research Competition at Supercomputing. The International Conference for High Performance Computing, Networking, Storage and Analysis ; https://hal.science/hal-01739585 ; ACM Student Research Competition at Supercomputing. The International Conference for High Performance Computing, Networking, Storage and Analysis, Nov 2016, Salt Lake City, Utah, United States

Subject Terms: Exascale Computing, Energy Aware, Power Capping, Energy Efficiency, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.4: Parallel Architectures, ACM: D.: Software/D.4: OPERATING SYSTEMS/D.4.8: Performance/D.4.8.2: Monitors, ACM: D.: Software/D.4: OPERATING SYSTEMS/D.4.8: Performance/D.4.8.1: Modeling and prediction, [INFO.INFO-DC]Computer Science [cs]/Distributed, Parallel, and Cluster Computing [cs.DC]

Subject Geographic: Salt Lake City, Utah, United States

Availability: https://hal.science/hal-01739585
https://hal.science/hal-01739585v1/document
https://hal.science/hal-01739585v1/file/01_EEAaware-SC16-JAGH-poster.pdf

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16

Classification and Elimination of Conflicts in Hardware Transactional Memory Systems

Authors: Waliullah, Mridha Mohammad Stenstrom, Per Amdahl's Law is Forever (ALF) et al.

Contributors: Waliullah, Mridha Mohammad Stenstrom, Per Amdahl's Law is Forever (ALF) et al.

Source: 23rd International Symposium on Computer Architecture and High Performance Computing - SBAC-PAD'2011
https://inria.hal.science/hal-00640813
23rd International Symposium on Computer Architecture and High Performance Computing - SBAC-PAD'2011, Oct 2011, Vitoria, Brazil

Subject Terms: Transactional Memory, Contamination Misses, Intermediate Checkpointing, Manycore, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.0: General, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

Subject Geographic: Vitoria, Brazil

Time: Vitoria, Brazil

Availability: https://inria.hal.science/hal-00640813
https://inria.hal.science/hal-00640813/document
https://inria.hal.science/hal-00640813/file/sbac-pad_ieee.pdf

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17

Hardware-Accelerated Dynamic Binary Translation

Authors: Rokicki, Simon Rohou, Erven Derrien, Steven et al.

Contributors: Rokicki, Simon Rohou, Erven Derrien, Steven et al.

Source: IEEE/ACM Design, Automation & Test in Europe Conference & Exhibition (DATE) ; https://inria.hal.science/hal-01423639 ; IEEE/ACM Design, Automation & Test in Europe Conference & Exhibition (DATE), Mar 2017, Lausanne, Switzerland ; https://www.date-conference.com/

Subject Terms: ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.3: Other Architecture Styles/C.1.3.5: Heterogeneous (hybrid) systems, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.3: Other Architecture Styles/C.1.3.0: Adaptable architectures, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.2: Multiple Data Stream Architectures (Multiprocessors)/C.1.2.4: Multiple-instruction-stream, multiple-data-stream processors (MIMD), ACM: D.: Software/D.3: PROGRAMMING LANGUAGES/D.3.4: Processors/D.3.4.0: Code generation, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [INFO.INFO-ES]Computer Science [cs]/Embedded Systems

Subject Geographic: Lausanne, Switzerland

Availability: https://inria.hal.science/hal-01423639
https://inria.hal.science/hal-01423639v1/document
https://inria.hal.science/hal-01423639v1/file/rokicki_DATE_cr.pdf

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18

FlinkMan : Anomaly Detection in Manufacturing Equipment with Apache Flink : Grand Challenge

Authors: Busnel, Yann Riveei, Nicolo Gal, Avigdor et al.

Contributors: Busnel, Yann Riveei, Nicolo Gal, Avigdor et al.

Source: DEBS '17 : 11th ACM International Conference on Distributed and Event-based Systems ; https://hal.science/hal-01644417 ; DEBS '17 : 11th ACM International Conference on Distributed and Event-based Systems, Jun 2017, Barcelone, Spain. pp.274-279 ⟨10.1145/3093742.3095099⟩

Subject Terms: Markov Chains, Clustering, Linked-Data, Stream Processing, Anomaly Detection, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.2: Multiple Data Stream Architectures (Multiprocessors), ACM: H.: Information Systems/H.3: INFORMATION STORAGE AND RETRIEVAL/H.3.4: Systems and Software/H.3.4.1: Distributed systems, ACM: I.: Computing Methodologies/I.2: ARTIFICIAL INTELLIGENCE/I.2.6: Learning, [INFO.INFO-DS]Computer Science [cs]/Data Structures and Algorithms [cs.DS], [INFO.INFO-DC]Computer Science [cs]/Distributed, Parallel, and Cluster Computing [cs.DC], [INFO.INFO-IT]Computer Science [cs]/Information Theory [cs.IT]

Subject Geographic: Spain

Time: Barcelone, Spain

Availability: https://hal.science/hal-01644417
https://hal.science/hal-01644417v1/document
https://hal.science/hal-01644417v1/file/main.pdf
https://doi.org/10.1145/3093742.3095099

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19

Simty: generalized SIMT execution on RISC-V

Authors: Collange, Caroline Pushing Architecture and Compilation for Application Performance (PACAP) Inria Rennes – Bretagne Atlantique et al.

Contributors: Collange, Caroline Pushing Architecture and Compilation for Application Performance (PACAP) Inria Rennes – Bretagne Atlantique et al.

Source: CARRV 2017 - 1st Workshop on Computer Architecture Research with RISC-V ; https://inria.hal.science/hal-01622208 ; CARRV 2017 - 1st Workshop on Computer Architecture Research with RISC-V, Oct 2017, Boston, United States. pp.6

Subject Terms: SIMT, SIMD, FPGA, RISC-V, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.2: Multiple Data Stream Architectures (Multiprocessors)/C.1.2.7: Single-instruction-stream, multiple-data-stream processors (SIMD), [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]