Výsledky vyhledávání - acm: b.: hardware/b.7: integrated circuits/b.7.1: types AND design style*

1

Design of a 4th-Order Feed-Forward-Compensated Operational Amplifier for Multi-GHz Sampling Frequency Continuous-Time Bandpass Sigma-Delta Modulators

Autoři: Gebreyohannes, Fikre Tsigabu Louërat, Marie-Minerve Aboushady, Hassan a další

Přispěvatelé: Gebreyohannes, Fikre Tsigabu Louërat, Marie-Minerve Aboushady, Hassan a další

Zdroj: 2019 IEEE International Symposium on Circuits and Systems (ISCAS)
https://hal.sorbonne-universite.fr/hal-02145589
2019 IEEE International Symposium on Circuits and Systems (ISCAS), May 2019, Sapporo, Japan. ⟨10.1109/ISCAS.2019.8702147⟩

Témata: Multi-stage amplifiers, Feed-forward compensation, sigma-delta modulators, bandpass, continuous-time, ACM: B.: Hardware/B.7: INTEGRATED CIRCUITS/B.7.1: Types and Design Styles/B.7.1.7: VLSI (very large scale integration), [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [SPI.TRON]Engineering Sciences [physics]/Electronics

Geografické téma: Sapporo, Japan

Dostupnost: https://hal.sorbonne-universite.fr/hal-02145589
https://hal.sorbonne-universite.fr/hal-02145589v1/document
https://hal.sorbonne-universite.fr/hal-02145589v1/file/ISCAS_2019_Submitted_Version.pdf
https://doi.org/10.1109/ISCAS.2019.8702147

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2

Soft timing closure for soft programmable logic cores: The ARGen approach

Autoři: Bollengier, Théotime Lagadec, Loïc Najem, Mohamad a další

Přispěvatelé: Bollengier, Théotime Lagadec, Loïc Najem, Mohamad a další

Zdroj: ARC 2017 - 13th International Symposium on Applied Reconfigurable Computing ; https://hal.science/hal-01475251 ; ARC 2017 - 13th International Symposium on Applied Reconfigurable Computing, Delft University of Technology Apr 2017, Delft, Netherlands ; http://www.arc2017.tudelft.nl

Témata: Reconfigurable cores, ACM: B.: Hardware, ACM: B.: Hardware/B.5: REGISTER-TRANSFER-LEVEL IMPLEMENTATION/B.5.1: Design, ACM: B.: Hardware/B.7: INTEGRATED CIRCUITS/B.7.1: Types and Design Styles/B.7.1.2: Gate arrays, ACM: B.: Hardware/B.7: INTEGRATED CIRCUITS/B.7.1: Types and Design Styles/B.7.1.7: VLSI (very large scale integration), ACM: D.: Software/D.2: SOFTWARE ENGINEERING/D.2.11: Software Architectures/D.2.11.4: Patterns (e.g., client/server, pipeline, blackboard), [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

Geografické téma: Delft, Netherlands

Dostupnost: https://hal.science/hal-01475251
https://hal.science/hal-01475251v1/document
https://hal.science/hal-01475251v1/file/paper_6-4.pdf

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3

NoC-Based Protection for SoC Time-Driven Attacks

Autoři: Sepulveda, Martha Johanna Diguet, Jean-Philippe Strum, Marius a další

Přispěvatelé: Sepulveda, Martha Johanna Diguet, Jean-Philippe Strum, Marius a další

Zdroj: IEEE Embedded Systems Letters. 7:7-10

Témata: ACM: B.: Hardware/B.7: INTEGRATED CIRCUITS, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], Channel leakage, multiport memory, common bus, ACM: B.: Hardware/B.7: INTEGRATED CIRCUITS/B.7.1: Types and Design Styles/B.7.1.7: VLSI (very large scale integration), 02 engineering and technology, 3. Good health, Network On Chip, crossbar switch), Security, 0202 electrical engineering, electronic engineering, information engineering, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.2: Multiple Data Stream Architectures (Multiprocessors)/C.1.2.3: Interconnection architectures (e.g, [SPI.SIGNAL]Engineering Sciences [physics]/Signal and Image processing, [SPI.SIGNAL] Engineering Sciences [physics]/Signal and Image processing

Přístupová URL adresa: https://hal.archives-ouvertes.fr/hal-01083270
http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6994256
https://hal.inria.fr/hal-01253500
http://ieeexplore.ieee.org/document/6994256
https://ieeexplore.ieee.org/document/6994256
https://dblp.uni-trier.de/db/journals/esl/esl7.html#SepulvedaDSG15

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4

Towards a hardware-assisted information flow tracking ecosystem for ARM processors

Autoři: Abdul Wahab, Muhammad Cotret, Pascal Nasr Allah, Mounir a další

Přispěvatelé: Abdul Wahab, Muhammad Cotret, Pascal Nasr Allah, Mounir a další

Zdroj: 26th International Conference on Field-Programmable Logic and Applications (FPL 2016)
https://hal.science/hal-01337579
26th International Conference on Field-Programmable Logic and Applications (FPL 2016), Aug 2016, Lausanne, Switzerland. ⟨10.1109/fpl.2016.7577396⟩
http://www.fpl2016.org

Témata: Heterogeneous SoC, DIFT, ARM Coresight components, Information Flow Tracking, ACM: B.: Hardware/B.7: INTEGRATED CIRCUITS/B.7.1: Types and Design Styles/B.7.1.7: VLSI (very large scale integration), ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.3: Other Architecture Styles/C.1.3.5: Heterogeneous (hybrid) systems, [SPI.TRON]Engineering Sciences [physics]/Electronics, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [INFO.INFO-CR]Computer Science [cs]/Cryptography and Security [cs.CR]

Geografické téma: Lausanne, Switzerland

Dostupnost: https://hal.science/hal-01337579
https://hal.science/hal-01337579v1/document
https://hal.science/hal-01337579v1/file/fpl2016.pdf
https://doi.org/10.1109/fpl.2016.7577396

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5

Protecting against Cryptographic Trojans in FPGAs

Autoři: Swierczynski, Pawel Fyrbiak, Marc Paar, Christof a další

Přispěvatelé: Swierczynski, Pawel Fyrbiak, Marc Paar, Christof a další

Zdroj: FCCM - 23rd IEEE International Symposium on Field-Programmable Custom Computing Machines ; https://inria.hal.science/hal-01140008 ; FCCM - 23rd IEEE International Symposium on Field-Programmable Custom Computing Machines, May 2015, Vancouver, Canada. ⟨10.1109/FCCM.2015.55⟩ ; http://fccm.org/2015/

Témata: AES algorithm, FPGA, Hardware trojan, ACM: B.: Hardware/B.7: INTEGRATED CIRCUITS/B.7.1: Types and Design Styles/B.7.1.2: Gate arrays, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

Geografické téma: Vancouver

Time: Vancouver, Canada

Dostupnost: https://inria.hal.science/hal-01140008
https://inria.hal.science/hal-01140008v1/document
https://inria.hal.science/hal-01140008v1/file/swierczynski-fccm15.pdf
https://doi.org/10.1109/FCCM.2015.55

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6

RISC-V design using Free Open Source Software

Autoři: Chaput, Jean-Paul Louërat, Marie-Minerve Chotin-Avot, Roselyne a další

Přispěvatelé: Chaput, Jean-Paul Louërat, Marie-Minerve Chotin-Avot, Roselyne a další

Zdroj: the RISC-V Week ; https://hal.sorbonne-universite.fr/hal-02316711 ; the RISC-V Week, Oct 2019, Paris, France

Témata: ACM: B.: Hardware/B.5: REGISTER-TRANSFER-LEVEL IMPLEMENTATION/B.5.2: Design Aids, ACM: B.: Hardware/B.7: INTEGRATED CIRCUITS/B.7.2: Design Aids, ACM: B.: Hardware/B.7: INTEGRATED CIRCUITS/B.7.1: Types and Design Styles/B.7.1.5: Microprocessors and microcomputers, ACM: B.: Hardware/B.7: INTEGRATED CIRCUITS/B.7.2: Design Aids/B.7.2.2: Placement and routing, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [SPI.TRON]Engineering Sciences [physics]/Electronics, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics

Geografické téma: Paris, France

Dostupnost: https://hal.sorbonne-universite.fr/hal-02316711

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7

Low Power Reconfigurable Controllers for Wireless Sensor Network Nodes

Autoři: Tovinakere Dwarakanath, Vivek Sentieys, Olivier Derrien, Steven a další

Přispěvatelé: Tovinakere Dwarakanath, Vivek Sentieys, Olivier Derrien, Steven a další

Zdroj: FCCM - 22nd IEEE International Symposium on Field-Programmable Custom Computing Machines ; https://inria.hal.science/hal-01017185 ; FCCM - 22nd IEEE International Symposium on Field-Programmable Custom Computing Machines, May 2014, Boston, United States. pp.230-233, ⟨10.1109/FCCM.2014.68⟩

Témata: Low power, microcontrollers, power gating, reconfigurable hardware, wireless sensor networks, ACM: B.: Hardware/B.1: CONTROL STRUCTURES AND MICROPROGRAMMING, ACM: B.: Hardware/B.7: INTEGRATED CIRCUITS/B.7.1: Types and Design Styles, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [INFO.INFO-NI]Computer Science [cs]/Networking and Internet Architecture [cs.NI]

Geografické téma: Boston, United States

Time: Boston, United States

Dostupnost: https://inria.hal.science/hal-01017185
https://inria.hal.science/hal-01017185v1/document
https://inria.hal.science/hal-01017185v1/file/tovinakere-fccm14.pdf
https://doi.org/10.1109/FCCM.2014.68

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8

FPGA Architecture Support for Heterogeneous, Relocatable Partial Bitstreams

Autoři: Huriaux, Christophe Sentieys, Olivier Tessier, Russell a další

Přispěvatelé: Huriaux, Christophe Sentieys, Olivier Tessier, Russell a další

Zdroj: FPL - 24th International Conference on Field Programmable Logic and Applications ; https://inria.hal.science/hal-01017184 ; FPL - 24th International Conference on Field Programmable Logic and Applications, Sep 2014, Munich, Germany. ⟨10.1109/FPL.2014.6927494⟩

Témata: Partial reconfiguration, FPGA, heterogeneous fixed-function blocks, ACM: B.: Hardware/B.7: INTEGRATED CIRCUITS/B.7.1: Types and Design Styles/B.7.1.2: Gate arrays, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

Geografické téma: Munich, Germany

Relation: info:eu-repo/grantAgreement/EC/FP7/288248/EU/Self adaptive heterogeneous manycore based on Flexible Tiles/FLEXTILES

Dostupnost: https://inria.hal.science/hal-01017184
https://inria.hal.science/hal-01017184v1/document
https://inria.hal.science/hal-01017184v1/file/huriaux-fpl14.pdf
https://doi.org/10.1109/FPL.2014.6927494

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9

Optimizing DDR-SDRAM Communications at C-level for Automatically-Generated Hardware Accelerators. An Experience with the Altera C2H HLS Tool.

Autoři: Alias, Christophe Darte, Alain Plesco, Alexandru a další

Přispěvatelé: Alias, Christophe Darte, Alain Plesco, Alexandru a další

Zdroj: https://inria.hal.science/inria-00482035 ; [Research Report] RR-7281, INRIA. 2010, pp.19.

Témata: High-level synthesis, hardware accelerators, DDR-SDRAM, optimized communications, program transformation, reconfigurable architectures, FPGA, ACM: B.: Hardware/B.4: INPUT/OUTPUT AND DATA COMMUNICATIONS/B.4.1: Data Communications Devices/B.4.1.0: Processors, ACM: B.: Hardware/B.4: INPUT/OUTPUT AND DATA COMMUNICATIONS/B.4.2: Input/Output Devices/B.4.2.0: Channels and controllers, ACM: B.: Hardware/B.7: INTEGRATED CIRCUITS/B.7.1: Types and Design Styles/B.7.1.1: Algorithms implemented in hardware, ACM: B.: Hardware/B.7: INTEGRATED CIRCUITS/B.7.1: Types and Design Styles/B.7.1.3: Input/output circuits, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.3: Other Architecture Styles/C.1.3.0: Adaptable architectures, [INFO.INFO-ES]Computer Science [cs]/Embedded Systems, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [INFO.INFO-PL]Computer Science [cs]/Programming Languages [cs.PL]

Dostupnost: https://inria.hal.science/inria-00482035
https://inria.hal.science/inria-00482035v1/document
https://inria.hal.science/inria-00482035v1/file/RR-7281.pdf

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10

A semiempirical model for wakeup time estimation in power-gated logic clusters

Autoři: Tovinakere Dwarakanath, Vivek Sentieys, Olivier Derrien, Steven a další

Přispěvatelé: Tovinakere Dwarakanath, Vivek Sentieys, Olivier Derrien, Steven a další

Zdroj: The 49th Annual Design Automation Conference 2012, DAC '12, San Francisco, CA, USA, June 3-7, 2012 ; https://inria.hal.science/hal-00752606 ; The 49th Annual Design Automation Conference 2012, DAC '12, San Francisco, CA, USA, June 3-7, 2012, Jun 2012, San Fransisco, United States. pp.48-55

Témata: ACM: B.: Hardware/B.7: INTEGRATED CIRCUITS/B.7.1: Types and Design Styles/B.7.1.7: VLSI (very large scale integration), ACM: B.: Hardware/B.6: LOGIC DESIGN/B.6.3: Design Aids/B.6.3.2: Optimization, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]