Search Results - acm: b.: hardware/b.6: logic design/b.6.3: design cad/b.6.3.2: optimization

A power-aware algorithm for the design of reconfigurable hardware during high level placement.

Authors: On Fung, Wing Arslan, Tughrul

Source: International Journal of Knowledge Based Intelligent Engineering Systems; Sep2008, Vol. 12 Issue 3, p237-244, 8p, 5 Diagrams, 2 Graphs

Subject Terms: ELECTRIC power conservation, PORTABLE computers, LOGIC devices, CAD/CAM systems, ALGORITHMS, ROUTING (Computer network management)

Active Leakage Power Optimization for FPGAs.

Authors: Anderson, Jason H. Najm, Farid N.

Source: IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems; Mar2006, Vol. 25 Issue 3, p423-437, 15p, 2 Black and White Photographs, 5 Charts, 17 Graphs

Subject Terms: FIELD programmable gate arrays, COMPLEMENTARY metal oxide semiconductors, COMPUTER-aided design, GATE array circuits, LOGIC circuits, ELECTRONIC circuit design, COMPUTER engineering

Towards Machine Learning-Based FPGA Backend Flow: Challenges and Opportunities.

Authors: Taj, Imran Farooq, Umer

Source: Electronics (2079-9292); Feb2023, Vol. 12 Issue 4, p935, 23p

Subject Terms: SYSTEMS on a chip, MACHINE learning, COMPUTER-aided design, LOGIC design, GATE array circuits, CLOUD computing

Optimization of Pattern Matching Circuits for Regular Expression on FPGA.

Authors: Cheng-Hung Lin Chih-Tsun Huang Chang-Ping Jiang et al.

Source: IEEE Transactions on Very Large Scale Integration (VLSI) Systems; Dec2007, Vol. 15 Issue 12, p1303-1310, 8p, 1 Chart

Subject Terms: SEQUENTIAL machine theory, FIELD programmable gate arrays, COMPUTER-aided design, ARCHITECTURE, ALGORITHMS, LOGIC, COMPUTER network architectures, COMPUTER network resources, DESIGN

Technology/System Co-Optimization for FPGA Using Emerging Reconfigurable Logic Device.

Authors: Lu, Sheng Shang, Liuting Jung, Sungyong et al.

Source: ACM Journal on Emerging Technologies in Computing Systems; Jul2025, Vol. 21 Issue 3, p1-21, 21p

Subject Terms: FIELD programmable gate arrays, PROGRAMMABLE logic devices, DESIGN techniques, MATHEMATICAL optimization, INTEGRATED circuits, BENCHMARK testing (Engineering)

SlackHammer: Logic Synthesis for Graceful Errors Under Frequency Scaling.

Authors: Alan, Tanfer Henkel, Jorg

Source: IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems; Nov2018, Vol. 37 Issue 11, p2802-2811, 10p

Subject Terms: LOGIC circuit synthesis (Electronic design), CRITICAL path analysis, ERROR rates, APPROXIMATION theory, CROSS layer optimization, ELECTRONIC design automation, REAL-time computing

Design Time Optimization for Hardware Watermarking Protection of HDL Designs.

Authors: Castillo, E. Morales, D. P. García, A. et al.

Source: Scientific World Journal; 3/15/2015, Vol. 2015, p1-14, 14p

Subject Terms: HARDWARE, DIGITAL watermarking, COMPUTER hardware description languages, INTERNET protocols, DIGITAL signatures

CAD for Delay Optimization of Symmetrical FPGA Architecture through Hybrid LUTs/PLAs.

Authors: Singh, Sunil Kr. Singh, R. K. Bhatia, M. P. S. et al.

Source: Advances in Computing & Information Technology; 2013, p581-591, 11p

EigenCircuit: Divergent Synthetic Benchmark Generation for Hardware Security Using PCA and Linear Programming.

Authors: Amir, Sarah Forte, Domenic

Source: IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems; Dec2022, Vol. 41 Issue 12, p5207-5219, 13p

Subject Terms: LINEAR programming, PRINCIPAL components analysis

A Hardware Realization Framework for Fuzzy Inference System Optimization.

Authors: Gorgin, Saeid Karvandi, Mohammad Sina Moghari, Somaye et al.

Source: Electronics (2079-9292); Feb2024, Vol. 13 Issue 4, p690, 15p

Subject Terms: FUZZY logic, FUZZY systems, MATHEMATICAL optimization, CODE generators, AUTONOMOUS robots

Las Vegas to Host 23rd ACM/IEEE Design Automation Conference.

Source: IEEE Design & Test of Computers; 1986, Vol. 3 Issue 3, p6-13, 8p

Mesh of Trees FPGA Architecture: Exploration and Optimization.

Authors: Bouaziz, Khouloud Chtourou, Sonda Marrakchi, Zied et al.

Source: IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems; Sep2022, Vol. 41 Issue 9, p2943-2956, 14p

Subject Terms: FIELD programmable gate arrays, COMPUTER-aided design, LOGIC design

Reconfigurable Hardware SAT Solvers: A Survey of Systems.

Authors: Skilarova, Iouliia Ferrari, António de Brito

Source: IEEE Transactions on Computers; Nov2004, Vol. 53 Issue 11, p1449-1461, 13p

Subject Terms: PROGRAMMABLE logic devices, NETWORK processors, ELECTRONIC equipment, ALGORITHMS, COMBINATORIAL optimization, COMPUTER programming

Design of hardware RGB to HMMD converter based on reversible logic.

Authors: Touil, Lamjed Ouni, Bouraoui

Source: IET Image Processing (Wiley-Blackwell); Aug2017, Vol. 11 Issue 8, p646-655, 10p

Subject Terms: REVERSIBLE computing, OPTICAL information processing, LOGIC design, QUANTUM information science, CELLULAR automata, DIGITAL electronics

Optimizing FPGA Logic Block Architectures for Arithmetic.

Authors: Murray, Kevin E. Luu, Jason Walker, Matthew J. P. et al.

Source: IEEE Transactions on Very Large Scale Integration (VLSI) Systems; Jun2020, Vol. 28 Issue 6, p1378-1391, 14p

Subject Terms: GATE array circuits, LOGIC design, FIELD programmable gate arrays, ARITHMETIC functions, PROGRAMMABLE controllers

CAD Techniques for Power Optimization in Virtex-5 FPGAs.

Authors: Gupta, S. Anderson, J. Farragher, L. et al.

Source: 2007 IEEE Custom Integrated Circuits Conference; 2007, p85-88, 4p

An integrated high-level hardware/software partitioning methodology.

Authors: Abdelhalim, M. Habib, S.

Source: Design Automation for Embedded Systems; Mar2011, Vol. 15 Issue 1, p19-50, 32p

Subject Terms: EMBEDDED computer system design & construction, PARTICLE swarm optimization, FIELD programmable gate arrays, COMPUTER systems, COMPUTER software, ELECTRONIC systems

Hardware–Software Embedded System for Real-Time Trajectory Planning of Multi-Axis Machine Using B-Spline Curve Interpolation Algorithm.

Authors: Tan, Qitao Mohd Basri, Mohd Ariffanan

Source: Machines; Dec2023, Vol. 11 Issue 12, p1043, 22p

Subject Terms: INTERPOLATION algorithms, LOGIC circuit design, CAD/CAM systems, CURVED surfaces, LOGIC design, AUTOMATION

Low Power (Low Energy) FPGAs: a Survey.

Authors: Hassanzadeh, A.

Source: International Review on Modelling & Simulations; Aug2009, Vol. 2 Issue 4, p395-400, 6p, 5 Diagrams, 1 Chart, 1 Graph

Subject Terms: FIELD programmable gate arrays, LOW voltage integrated circuits, GATE array circuits, PROGRAMMABLE logic devices, ELECTRIC power, POWER resources, ELECTRIC utilities, SURVEYS, ELECTRICAL engineering, ELECTRIC power systems

Parallelizing CAD: A Timely Research Agenda for EDA.

Authors: Catanzaro, Bryan Keutzer, Kurt Bor-Yiing Su

Source: DAC: Annual ACM/IEEE Design Automation Conference; 2008, p12-17, 6p, 2 Diagrams

Subject Terms: COMPUTER-aided design, MICROPROCESSORS, COMPUTER software development, COMPUTER engineering, PARALLEL programs (Computer programs)