Search Results - acm: b.: hardware/b.6: logic design/b.6.3: design cad/b.6.3.0: automatizacii synthesis

Warp Processing: Dynamic Translation of Binarles to FPGA Circuits.

Authors: Vahid, Frank Stitt, Greg Lysecky, Roman

Source: Computer (00189162); Jul2008, Vol. 41 Issue 7, p40-46, 7p

Subject Terms: COMPUTER integrated manufacturing systems, INTEGRATED circuits, CAD/CAM systems, COMPUTER software, FIELD programmable gate arrays, GATE array circuits, PROGRAMMABLE logic devices

Towards Machine Learning-Based FPGA Backend Flow: Challenges and Opportunities.

Authors: Taj, Imran Farooq, Umer

Source: Electronics (2079-9292); Feb2023, Vol. 12 Issue 4, p935, 23p

Subject Terms: SYSTEMS on a chip, MACHINE learning, COMPUTER-aided design, LOGIC design, GATE array circuits, CLOUD computing

Las Vegas to Host 23rd ACM/IEEE Design Automation Conference.

Source: IEEE Design & Test of Computers; 1986, Vol. 3 Issue 3, p6-13, 8p

Cofactor Sharing for Reversible Logic Synthesis.

Authors: SHAFAEI, ALIREZA SAEEDI, MEHDI PEDRAM, MASSOUD

Source: ACM Journal on Emerging Technologies in Computing Systems; Oct2014, Vol. 11 Issue 2, p14-14:21, 21p

Subject Terms: LOGIC circuit synthesis (Electronic design), ALGORITHMS, COMPUTER-aided design, SPARSE graphs, COMPUTER simulation

Teaching Hardware/Software System Codesign Using CAD Tools: A Case Study in Image Synthesis.

Authors: Dubois, Helene Sentieys, Oliver

Source: IEEE Transactions on Education; Aug2000, Vol. 43 Issue 3, p277, 7p, 15 Diagrams, 2 Charts

Subject Terms: COMPUTER science, APPLICATION-specific integrated circuits, COMPUTER-aided design equipment, DESIGN, HIGHER education

Automated Synthesis of Digital Hardware.

Authors: Hafer Parker

Source: IEEE Transactions on Computers; 1982, Vol. C-31 Issue 2, p93-109, 17p

Accelerated and Highly Correlated ASIC Synthesis of AI Hardware Subsystems Using CGP.

Authors: Prashanth, H. C. Rao, Madhav

Source: IET Computers & Digital Techniques (Wiley-Blackwell); 1/29/2024, Vol. 2024, p1-23, 23p

Subject Terms: LOGIC circuits, ARTIFICIAL intelligence, HARDWARE

Evaluating Large Language Models for Automatic Register Transfer Logic Generation for Combinational Circuits via High-Level Synthesis.

Authors: Swaroopa, Sneha Mukherjee, Rijoy Debnath, Anushka et al.

Source: Foundations & Trends in Electronic Design Automation; 2024, Vol. 14 Issue 4, p315-337, 23p

Subject Terms: LANGUAGE models, COMBINATIONAL circuits, INTEGRATED circuit verification, C++, GRAPES

SlackHammer: Logic Synthesis for Graceful Errors Under Frequency Scaling.

Authors: Alan, Tanfer Henkel, Jorg

Source: IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems; Nov2018, Vol. 37 Issue 11, p2802-2811, 10p

Subject Terms: LOGIC circuit synthesis (Electronic design), CRITICAL path analysis, ERROR rates, APPROXIMATION theory, CROSS layer optimization, ELECTRONIC design automation, REAL-time computing

A power-aware algorithm for the design of reconfigurable hardware during high level placement.

Authors: On Fung, Wing Arslan, Tughrul

Source: International Journal of Knowledge Based Intelligent Engineering Systems; Sep2008, Vol. 12 Issue 3, p237-244, 8p, 5 Diagrams, 2 Graphs

Subject Terms: ELECTRIC power conservation, PORTABLE computers, LOGIC devices, CAD/CAM systems, ALGORITHMS, ROUTING (Computer network management)

A Survey of High Level Synthesis Based Hardware Security Approaches for Reusable IP Cores [Feature].

Authors: Anshul, Aditya Sengupta, Anirban

Source: IEEE Circuits & Systems Magazine; 2023 Q4, Vol. 23 Issue 4, p44-62, 19p

Optimized Synthesis Method for Ultra-Low Power Multi-Input Material Implication Logic With Emerging Non-Volatile Memories.

Authors: Puglisi, Francesco Maria Zanotti, Tommaso Pavan, Paolo

Source: IEEE Transactions on Circuits & Systems. Part I: Regular Papers; Nov2021, Vol. 68 Issue 11, p4433-4443, 11p

Subject Terms: IMPLICATION (Logic), LOGIC circuits, COMPUTER-aided design software, HEURISTIC algorithms, BOOLEAN functions, OPERATIONS research

Axilog: Abstractions for Approximate Hardware Design and Reuse.

Authors: Mahajan, Divya Ramkrishnan, Kartik Jariwala, Rudra et al.

Source: IEEE Micro; Sep2015, Vol. 35 Issue 5, p16-30, 15p

Subject Terms: COMPUTER engineering, PROGRAMMING language semantics, VERILOG (Computer hardware description language), APPROXIMATION theory, ANNOTATIONS

Design of hardware RGB to HMMD converter based on reversible logic.

Authors: Touil, Lamjed Ouni, Bouraoui

Source: IET Image Processing (Wiley-Blackwell); Aug2017, Vol. 11 Issue 8, p646-655, 10p

Subject Terms: REVERSIBLE computing, OPTICAL information processing, LOGIC design, QUANTUM information science, CELLULAR automata, DIGITAL electronics

Efficient Metrics and High-Level Synthesis for Dynamically Reconfigurable Logic.

Authors: Meribout, Mahmoud Motomura, Masato

Source: IEEE Transactions on Very Large Scale Integration (VLSI) Systems; Jun2004, Vol. 12 Issue 6, p603-621, 19p, 2 Black and White Photographs, 19 Diagrams, 8 Charts, 1 Graph

Subject Terms: ADAPTIVE computing systems, MULTIPLEXING, SCHEDULING, LOGIC design, ELECTRONIC circuit design, TELECOMMUNICATION

Formation of IP-Core Libraries in the User IC Design Flow for FPGAs and RSoCs.

Authors: Khvatov, V. M. Gavrilov, S. V.

Source: Russian Microelectronics; Dec2022, Vol. 51 Issue 7, p567-572, 6p

Subject Terms: INTEGRATED circuit design, LIBRARY users, SYSTEMS on a chip, LOGIC circuits, INTELLECTUAL property, FIELD programmable gate arrays

CAD synthesis tools for floating-gate SoC FPAAs.

Authors: Kim, Sihwan Shah, Sahil Wunderlich, Richard et al.

Source: Design Automation for Embedded Systems; Sep2021, Vol. 25 Issue 3, p161-176, 16p

Subject Terms: FIELD programmable analog arrays, MIXED signal circuits, TOOLS, MATRIX multiplications

Optimizing FPGA Logic Block Architectures for Arithmetic.

Authors: Murray, Kevin E. Luu, Jason Walker, Matthew J. P. et al.

Source: IEEE Transactions on Very Large Scale Integration (VLSI) Systems; Jun2020, Vol. 28 Issue 6, p1378-1391, 14p

Subject Terms: GATE array circuits, LOGIC design, FIELD programmable gate arrays, ARITHMETIC functions, PROGRAMMABLE controllers

LEARNING HARDWARE USING MULTIPLE-VALUED LOGIC.

Authors: Perkowski, Marek Foote, David Qihong Chen et al.

Source: IEEE Micro; May/Jun2002, Vol. 22 Issue 3, p41, 11p, 1 Diagram

Subject Terms: COMPUTER input-output equipment, ALGORITHMS, COMPUTER architecture

Are Logic Synthesis Tools Robust?

Authors: Puggelli, Alberto Welp, Tobias Kuehlmann, Andreas et al.

Source: DAC: Annual ACM/IEEE Design Automation Conference; Jun2011, p633-638, 6p, 2 Diagrams, 4 Charts, 5 Graphs

Subject Terms: VERILOG (Computer hardware description language), ROBUST control, COMPUTER software correctness, ALGORITHMS, MATHEMATICAL transformations