Suchergebnisse - acm: b.: hardware/b.6: logic design/b.6.3: design cad/b.6.3.0: automatizacia system~

Design of hardware RGB to HMMD converter based on reversible logic.

Autoren: Touil, Lamjed Ouni, Bouraoui

Quelle: IET Image Processing (Wiley-Blackwell); Aug2017, Vol. 11 Issue 8, p646-655, 10p

Schlagwörter: REVERSIBLE computing, OPTICAL information processing, LOGIC design, QUANTUM information science, CELLULAR automata, DIGITAL electronics

A study on the generation of silicon-based hardware Plc by means of the direct conversion of the ladder diagram to circuit design language

Autoren: Du, Daoshan Xu, Xiaodong Yamazaki, Kazuo

Quelle: The International Journal of Advanced Manufacturing Technology. 49(5)

Schlagwörter: Engineering, Computer-Aided Engineering (CAD, CAE) and Design, Mechanical Engineering, Production/Logistics, Industrial and Production Engineering, Programmable logic controller, Ladder diagram, Very high-speed circuit design hard description language, Field programmable gate array, Condensed simultaneity graph, Finite state machine

Dateibeschreibung: application/pdf

Zugangs-URL: https://escholarship.org/uc/item/2v64b6tc
https://escholarship.org/content/qt2v64b6tc/qt2v64b6tc.pdf

Bio-mimicking DNA fingerprint profiling for HLS watermarking to counter hardware IP piracy.

Autoren: Sengupta A Bhui N Anshul A et al.

Quelle: Scientific reports [Sci Rep] 2024 Sep 28; Vol. 14 (1), pp. 22413. Date of Electronic Publication: 2024 Sep 28.

Publikationsart: Journal Article

Info zur Zeitschrift: Publisher: Nature Publishing Group Country of Publication: England NLM ID: 101563288 Publication Model: Electronic Cited Medium: Internet ISSN: 2045-2322 (Electronic) Linking ISSN: 20452322 NLM ISO Abbreviation: Sci Rep Subsets: MEDLINE

MeSH-Schlagworte: Computer Security* , DNA Fingerprinting*/methods , Algorithms*, Humans ; Computers ; DNA

Field Programmable Gate Array Applications—A Scientometric Review.

Autoren: Ruiz-Rosero, Juan Ramirez-Gonzalez, Gustavo Khanna, Rahul

Quelle: Computation; Dec2019, Vol. 7 Issue 4, p63-63, 1p

Schlagwörter: FIELD programmable gate arrays, DIGITAL video, PROGRAMMABLE logic devices, DIGITAL signal processing, MAGNETIC suspension, SYSTEMS on a chip

A Review of Algorithm & Hardware Design for AI-Based Biomedical Applications.

Autoren: Wei, Ying Zhou, Jun Wang, Yin et al.

Quelle: IEEE Transactions on Biomedical Circuits & Systems; Apr2020, Vol. 14 Issue 2, p145-163, 19p

A methodology and algorithms for efficient interprocess communication synthesis from system description in SDL

Autoren: Svantesson, Bengt Kumar, Shashi Hemani, Ahmed

Quelle: VLSI Design, 1998. Proceedings., 1998 Eleventh International Conference on. :78-84

Schlagwörter: SDL, communication block, computation block, data computation functions, dynamic processes, extended FSM, hardware implementation, hardware synthesis, interprocess communication, interprocess communication synthesis, multiple instances, supervisor block, system specification languages, VLSI, circuit CAD, finite state machines, logic CAD, specification languages

Dateibeschreibung: print

Zugangs-URL: https://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-73105

Enhancing the Hardware Pipelining Optimization Technique of the SHA-3 via FPGA.

Autoren: Sideris, Argyrios Dasygenis, Minas

Quelle: Computation; Aug2023, Vol. 11 Issue 8, p152, 15p

Schlagwörter: MATHEMATICAL optimization, ARCHITECTURAL design, COMPUTER architecture, DATA transmission systems, DATA integrity, HARDWARE

A Survey of Memristive Threshold Logic Circuits.

Autoren: Maan, Akshay Kumar Jayadevi, Deepthi Anirudhan James, Alex Pappachen

Quelle: IEEE Transactions on Neural Networks & Learning Systems; Aug2017, Vol. 28 Issue 8, p1734-1746, 13p

Schlagwörter: NEURONS, THRESHOLD logic, NANOELECTROMECHANICAL systems, MATHEMATICAL models

Hardware synthesis of an ATM multiplexer from SDL to VHDL: a case study

Autoren: Horn, Wolfgang Svantesson, Bengt Kumar, Shashi et al.

Quelle: VLSI ’99. Proceedings IEEE Computer Society Workshop On. :100-105

Schlagwörter: 155 Mbit/s, ATM multiplexer, Communicating Sequential Processes, FIFO buffers, SDL, VHDL, dynamic processes, hardware synthesis, infinite FIFO buffer, inter-process communication, system specification, asynchronous transfer mode, communicating sequential processes, hardware description languages, logic CAD, multiplexing equipment, specification languages, telecommunication computing

Dateibeschreibung: print

Zugangs-URL: https://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-73117

Solving sparse finite element problems on neuromorphic hardware.

Autoren: Theilman, Bradley H. Aimone, James B.

Quelle: Nature Machine Intelligence; Nov2025, Vol. 7 Issue 11, p1845-1857, 13p

Recent improvements in the digital design laboratory at the University of Michigan.

Autoren: Wiesmeyer, M. Jenkins, J.M.

Quelle: IEEE Transactions on Education. 1989, Vol. 32 Issue 1, p52-56. 5p.

First-Order Logic Based Situational and Dynamic Interpretation of Natural Language Descriptions in Hardware Design Specifications / ハードウェア設計仕様における自然言語記述の一階論理に基づく状況的・動的解釈

Autoren: Koichi KISE Kunio FUKUNAGA Noriaki IZUMI et al.

Quelle: 人工知能 / Journal of the Japanese Society for Artificial Intelligence. 1995, 10(5):720

Relaxed Fault-Tolerant Hardware Implementation of Neural Networks in the Presence of Multiple Transient Errors.

Autoren: Mahdiani, Hamid Reza Fakhraie, Sied Mehdi Lucas, Caro

Quelle: IEEE Transactions on Neural Networks & Learning Systems; Aug2012, Vol. 23 Issue 8, p1215-1228, 14p

Schlagwörter: ARTIFICIAL neural networks, COMPUTER input-output equipment, INTEGRATED circuit fault tolerance, HUMAN facial recognition software, LOGIC circuits

Virtual Prototyping and Validation of Cpps within a New Software Framework.

Autoren: Neumeyer, Sebastian Exner, Konrad Kind, Simon et al.

Quelle: Computation; 2017, Vol. 5 Issue 1, p10, 14p

Schlagwörter: VIRTUAL prototypes, CYBER physical systems, VIRTUAL design, COMMUNICATION, FLEXIBLE manufacturing systems

Understanding dental CAD/CAM for restorations - the digital workflow from a mechanical engineering viewpoint. (English)

Alternate Title: Dentale CAD/CAM-Systeme zum Zahnersatz verstehen - der digitale Workflow aus Sicht des Maschinenbaus. (German)

Autoren: Tapie, L. Lebon, N. Mawussi, B. et al.

Quelle: International Journal of Computerized Dentistry; 2015, Vol. 18 Issue 1, p21-44, 24p

FPGA implementation of semi-fragile reversible watermarking by histogram bin shifting in real time.

Autoren: Hazra, Sambaran Ghosh, Sudip De, Sayandip et al.

Quelle: Journal of Real-Time Image Processing; Jan2018, Vol. 14 Issue 1, p193-221, 29p

DCDC PUF an enhanced implementation of ring oscillator based PUF.

Autoren: Younes L Abulibdeh E Mohammad B et al.

Quelle: Scientific reports [Sci Rep] 2025 Aug 23; Vol. 15 (1), pp. 31017. Date of Electronic Publication: 2025 Aug 23.

Publikationsart: Journal Article

Info zur Zeitschrift: Publisher: Nature Publishing Group Country of Publication: England NLM ID: 101563288 Publication Model: Electronic Cited Medium: Internet ISSN: 2045-2322 (Electronic) Linking ISSN: 20452322 NLM ISO Abbreviation: Sci Rep Subsets: PubMed not MEDLINE; MEDLINE

Area-efficient parallel adder with faithful approximation for image and signal processing applications.

Autoren: Palanisamy, Gnanambikai Natarajan, Vijeyakumar Krishnasamy Sundaram, Kalaiselvi

Quelle: IET Image Processing (Wiley-Blackwell); 2019, Vol. 13 Issue 13, p2587-2594, 8p

Schlagwörter: SIGNAL processing, IMAGE processing, LOGIC design, METAL oxide semiconductor field-effect transistors, BLOCK designs, TRANSISTORS, DELAY-tolerant networks

Mixed-Signal Design Using Digital CAD

Autoren: Unnikrishnan, Vishnu Vesterbacka, Mark

Quelle: Proceedings IEEE Computer Society Annual Symposium on VLSI ISVLSI 2016 IEEE Computer Society Annual Symposium on VLSI. :6-11

Schlagwörter: CAD, analogue-digital conversion, digital-analogue conversion, electronic engineering computing, integrated circuit design, mixed analogue-digital integrated circuits, signal processing, system-on-chip, time-domain analysis, ADC design, CAD framework, CMOS process, Spectre simulation, analog interfaces, analog-to-digital conversion, corruption mechanisms, data conversion, digital CAD framework, digital circuit synthesis, digital design flow, digital-to-analog conversion, high-performance data conversion circuits, mixed-signal circuit synthesis, mixed-signal design, mixed-signal functions, size 65 nm, system-on-chip design, time-domain signal processing, time-domain signal processing systems, vendor supplied standard cell library, Delays, Digital circuits, Inverters, Logic gates, Signal processing, Standards, Time-domain analysis, ADC, DAC, Mixed-signal, VHDL, Verilog, all-digital, analog, analog-to-digital, comparator, design flow, digital, digital-to-analog, opamp, place-and-route, synthesis, synthesizable, time-domain, time-mode

Dateibeschreibung: print

Zugangs-URL: https://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-132788

Automated theorem proving.

Autoren: Plaisted, David A.

Quelle: WIREs: Cognitive Science; Mar2014, Vol. 5 Issue 2, p115-128, 14p

Schlagwörter: AUTOMATIC theorem proving, COMPUTER systems, COMPUTER input-output equipment, COMPUTER software, NATURAL language processing, PROPOSITION (Logic)