Search Results - acm: b.: hardware/b.6: logic design/b.6.3: design cad/b.6.3.0: automatizacia synthesis*

Design of hardware RGB to HMMD converter based on reversible logic.

Authors: Touil, Lamjed Ouni, Bouraoui

Source: IET Image Processing (Wiley-Blackwell); Aug2017, Vol. 11 Issue 8, p646-655, 10p

Subject Terms: REVERSIBLE computing, OPTICAL information processing, LOGIC design, QUANTUM information science, CELLULAR automata, DIGITAL electronics

A methodology and algorithms for efficient interprocess communication synthesis from system description in SDL

Authors: Svantesson, Bengt Kumar, Shashi Hemani, Ahmed

Source: VLSI Design, 1998. Proceedings., 1998 Eleventh International Conference on. :78-84

Subject Terms: SDL, communication block, computation block, data computation functions, dynamic processes, extended FSM, hardware implementation, hardware synthesis, interprocess communication, interprocess communication synthesis, multiple instances, supervisor block, system specification languages, VLSI, circuit CAD, finite state machines, logic CAD, specification languages

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Access URL: https://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-73105

Bio-mimicking DNA fingerprint profiling for HLS watermarking to counter hardware IP piracy.

Authors: Sengupta A Bhui N Anshul A et al.

Source: Scientific reports [Sci Rep] 2024 Sep 28; Vol. 14 (1), pp. 22413. Date of Electronic Publication: 2024 Sep 28.

Publication Type: Journal Article

Journal Info: Publisher: Nature Publishing Group Country of Publication: England NLM ID: 101563288 Publication Model: Electronic Cited Medium: Internet ISSN: 2045-2322 (Electronic) Linking ISSN: 20452322 NLM ISO Abbreviation: Sci Rep Subsets: MEDLINE

MeSH Terms: Computer Security* , DNA Fingerprinting*/methods , Algorithms*, Humans ; Computers ; DNA

Hardware synthesis of an ATM multiplexer from SDL to VHDL: a case study

Authors: Horn, Wolfgang Svantesson, Bengt Kumar, Shashi et al.

Source: VLSI ’99. Proceedings IEEE Computer Society Workshop On. :100-105

Subject Terms: 155 Mbit/s, ATM multiplexer, Communicating Sequential Processes, FIFO buffers, SDL, VHDL, dynamic processes, hardware synthesis, infinite FIFO buffer, inter-process communication, system specification, asynchronous transfer mode, communicating sequential processes, hardware description languages, logic CAD, multiplexing equipment, specification languages, telecommunication computing

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Access URL: https://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-73117

A study on the generation of silicon-based hardware Plc by means of the direct conversion of the ladder diagram to circuit design language

Authors: Du, Daoshan Xu, Xiaodong Yamazaki, Kazuo

Source: The International Journal of Advanced Manufacturing Technology. 49(5)

Subject Terms: Engineering, Computer-Aided Engineering (CAD, CAE) and Design, Mechanical Engineering, Production/Logistics, Industrial and Production Engineering, Programmable logic controller, Ladder diagram, Very high-speed circuit design hard description language, Field programmable gate array, Condensed simultaneity graph, Finite state machine

File Description: application/pdf

Access URL: https://escholarship.org/uc/item/2v64b6tc
https://escholarship.org/content/qt2v64b6tc/qt2v64b6tc.pdf

Field Programmable Gate Array Applications—A Scientometric Review.

Authors: Ruiz-Rosero, Juan Ramirez-Gonzalez, Gustavo Khanna, Rahul

Source: Computation; Dec2019, Vol. 7 Issue 4, p63-63, 1p

Subject Terms: FIELD programmable gate arrays, DIGITAL video, PROGRAMMABLE logic devices, DIGITAL signal processing, MAGNETIC suspension, SYSTEMS on a chip

Synplicity's Synplify ASIC Adopted by Industry Leaders; Quality of Results and Vendor Endorsements Fuel Growth in ASIC Products

Authors: By:ALEX

Source: Business Wire, February 17, 2004

A Survey of Memristive Threshold Logic Circuits.

Authors: Maan, Akshay Kumar Jayadevi, Deepthi Anirudhan James, Alex Pappachen

Source: IEEE Transactions on Neural Networks & Learning Systems; Aug2017, Vol. 28 Issue 8, p1734-1746, 13p

Subject Terms: NEURONS, THRESHOLD logic, NANOELECTROMECHANICAL systems, MATHEMATICAL models

Logic Design for Custom LSIs / カスタムLSIの論理設計

Authors: Takashi NANYA 南谷 崇

Source: 計測と制御 / Journal of The Society of Instrument and Control Engineers. 1989, 28(10):861

Magma's Rajeev Madhavan to Provide Keynote Address at ISPD; ''The Death of Logic Synthesis''

Source: Business Wire, March 30, 2005

Mixed-Signal Design Using Digital CAD

Authors: Unnikrishnan, Vishnu Vesterbacka, Mark

Source: Proceedings IEEE Computer Society Annual Symposium on VLSI ISVLSI 2016 IEEE Computer Society Annual Symposium on VLSI. :6-11

Subject Terms: CAD, analogue-digital conversion, digital-analogue conversion, electronic engineering computing, integrated circuit design, mixed analogue-digital integrated circuits, signal processing, system-on-chip, time-domain analysis, ADC design, CAD framework, CMOS process, Spectre simulation, analog interfaces, analog-to-digital conversion, corruption mechanisms, data conversion, digital CAD framework, digital circuit synthesis, digital design flow, digital-to-analog conversion, high-performance data conversion circuits, mixed-signal circuit synthesis, mixed-signal design, mixed-signal functions, size 65 nm, system-on-chip design, time-domain signal processing, time-domain signal processing systems, vendor supplied standard cell library, Delays, Digital circuits, Inverters, Logic gates, Signal processing, Standards, Time-domain analysis, ADC, DAC, Mixed-signal, VHDL, Verilog, all-digital, analog, analog-to-digital, comparator, design flow, digital, digital-to-analog, opamp, place-and-route, synthesis, synthesizable, time-domain, time-mode

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Access URL: https://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-132788

First-Order Logic Based Situational and Dynamic Interpretation of Natural Language Descriptions in Hardware Design Specifications / ハードウェア設計仕様における自然言語記述の一階論理に基づく状況的・動的解釈

Authors: Koichi KISE Kunio FUKUNAGA Noriaki IZUMI et al.

Source: 人工知能 / Journal of the Japanese Society for Artificial Intelligence. 1995, 10(5):720

Area-efficient parallel adder with faithful approximation for image and signal processing applications.

Authors: Palanisamy, Gnanambikai Natarajan, Vijeyakumar Krishnasamy Sundaram, Kalaiselvi

Source: IET Image Processing (Wiley-Blackwell); 2019, Vol. 13 Issue 13, p2587-2594, 8p

Subject Terms: SIGNAL processing, IMAGE processing, LOGIC design, METAL oxide semiconductor field-effect transistors, BLOCK designs, TRANSISTORS, DELAY-tolerant networks

High-Level Synthesis for SiLago: Advances in Optimization of High-Level Synthesis Tool and Neural Network Algorithms

Authors: Yang, Yu Hemani, Ahmed Lu, Zhonghai et al.

Contributors: Yang, Yu Hemani, Ahmed Lu, Zhonghai et al.

Source: TRITA-EECS-AVL.

Subject Terms: Electronic Design Automation (EDA), Computer Aided Design (CAD), Algorithm-level Synthesis, SiLago, Optimization Techniques, Neural Network, Informations- och kommunikationsteknik, Information and Communication Technology

File Description: electronic

Access URL: https://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-317555
https://kth.diva-portal.org/smash/get/diva2:1695389/FULLTEXT01.pdf

A 0.13mJ/Prediction CIFAR-100 Fully Synthesizable Raster-Scan-Based Wired-Logic Processor in 16-nm FPGA

Authors: Atsutake Kosuge Dongzhu Li Mototsugu Hamada et al.

Source: IEICE Transactions on Electronics. :2023

Logic Synthesis of Pass-Gate Logic Circuits With Emerging Ambipolar Technologies.

Authors: Tenace, Valerio Calimera, Andrea Macii, Enrico et al.

Source: IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems. Feb2020, Vol. 39 Issue 2, p397-410. 14p.

Subject Terms: *TECHNOLOGICAL innovations, *DATA structures, *PROGRAMMABLE controllers, LOGIC circuits, LOGIC design, METAL oxide semiconductor field-effect transistors, ELECTRIC circuit design & construction

Enhancing the Hardware Pipelining Optimization Technique of the SHA-3 via FPGA.

Authors: Sideris, Argyrios Dasygenis, Minas

Source: Computation; Aug2023, Vol. 11 Issue 8, p152, 15p

Subject Terms: MATHEMATICAL optimization, ARCHITECTURAL design, COMPUTER architecture, DATA transmission systems, DATA integrity, HARDWARE

System exploration and synthesis from SDL of an ATM switch component

Authors: Ykman-Couvreur, Ch. Lambrecht, J. Verkest, D. et al.

Source: ASIC/SOC Conference, 1999. Proceedings. Twelfth Annual IEEE International. :119-124

Subject Terms: ATM switch component, SDL system specification, concurrency management, hardware synthesis, intensive data storage, memory management, object-oriented language, optimization methods, stepwise exploration, system exploration, system synthesis, timing constraints, very high bit-rate data streams, application specific integrated circuits, asynchronous transfer mode, circuit CAD, digital integrated circuits, electronic switching systems, high level synthesis, integrated circuit design, specification languages, storage management, telecommunication computing, timing

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Access URL: https://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-73113

High-Level Synthesis and Test in the MOSCITO-Based Virtual Laboratory

Authors: Schneider, Andre Diener, Karl-Heinz Jervan, Gert et al.

Source: The 8th biennial Baltic Electronics Conference BEC 2002,2002. :287-290

Subject Terms: high-level synthesis, testing, virtual laboratory, MOSCITO, hierarchical test generation, CAD tools, hardware software co-design, TECHNOLOGY, Information technology, Computer science, TEKNIKVETENSKAP, Informationsteknik, Datavetenskap

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Access URL: https://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-23349

FPGA implementation of semi-fragile reversible watermarking by histogram bin shifting in real time.

Authors: Hazra, Sambaran Ghosh, Sudip De, Sayandip et al.

Source: Journal of Real-Time Image Processing; Jan2018, Vol. 14 Issue 1, p193-221, 29p