Search Results - acm: b.: hardware/b.6: logic design/b.6.3: design cad/b.6.3.0: automatizace synthesis

A methodology and algorithms for efficient interprocess communication synthesis from system description in SDL

Authors: Svantesson, Bengt Kumar, Shashi Hemani, Ahmed

Source: VLSI Design, 1998. Proceedings., 1998 Eleventh International Conference on. :78-84

Subject Terms: SDL, communication block, computation block, data computation functions, dynamic processes, extended FSM, hardware implementation, hardware synthesis, interprocess communication, interprocess communication synthesis, multiple instances, supervisor block, system specification languages, VLSI, circuit CAD, finite state machines, logic CAD, specification languages

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Access URL: https://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-73105

Hardware synthesis of an ATM multiplexer from SDL to VHDL: a case study

Authors: Horn, Wolfgang Svantesson, Bengt Kumar, Shashi et al.

Source: VLSI ’99. Proceedings IEEE Computer Society Workshop On. :100-105

Subject Terms: 155 Mbit/s, ATM multiplexer, Communicating Sequential Processes, FIFO buffers, SDL, VHDL, dynamic processes, hardware synthesis, infinite FIFO buffer, inter-process communication, system specification, asynchronous transfer mode, communicating sequential processes, hardware description languages, logic CAD, multiplexing equipment, specification languages, telecommunication computing

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Access URL: https://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-73117

A study on the generation of silicon-based hardware Plc by means of the direct conversion of the ladder diagram to circuit design language

Authors: Du, Daoshan Xu, Xiaodong Yamazaki, Kazuo

Source: The International Journal of Advanced Manufacturing Technology. 49(5)

Subject Terms: Engineering, Computer-Aided Engineering (CAD, CAE) and Design, Mechanical Engineering, Production/Logistics, Industrial and Production Engineering, Programmable logic controller, Ladder diagram, Very high-speed circuit design hard description language, Field programmable gate array, Condensed simultaneity graph, Finite state machine

File Description: application/pdf

Access URL: https://escholarship.org/uc/item/2v64b6tc
https://escholarship.org/content/qt2v64b6tc/qt2v64b6tc.pdf

Synplicity's Synplify ASIC Adopted by Industry Leaders; Quality of Results and Vendor Endorsements Fuel Growth in ASIC Products

Authors: By:ALEX

Source: Business Wire, February 17, 2004

Magma's Rajeev Madhavan to Provide Keynote Address at ISPD; ''The Death of Logic Synthesis''

Source: Business Wire, March 30, 2005

Mixed-Signal Design Using Digital CAD

Authors: Unnikrishnan, Vishnu Vesterbacka, Mark

Source: Proceedings IEEE Computer Society Annual Symposium on VLSI ISVLSI 2016 IEEE Computer Society Annual Symposium on VLSI. :6-11

Subject Terms: CAD, analogue-digital conversion, digital-analogue conversion, electronic engineering computing, integrated circuit design, mixed analogue-digital integrated circuits, signal processing, system-on-chip, time-domain analysis, ADC design, CAD framework, CMOS process, Spectre simulation, analog interfaces, analog-to-digital conversion, corruption mechanisms, data conversion, digital CAD framework, digital circuit synthesis, digital design flow, digital-to-analog conversion, high-performance data conversion circuits, mixed-signal circuit synthesis, mixed-signal design, mixed-signal functions, size 65 nm, system-on-chip design, time-domain signal processing, time-domain signal processing systems, vendor supplied standard cell library, Delays, Digital circuits, Inverters, Logic gates, Signal processing, Standards, Time-domain analysis, ADC, DAC, Mixed-signal, VHDL, Verilog, all-digital, analog, analog-to-digital, comparator, design flow, digital, digital-to-analog, opamp, place-and-route, synthesis, synthesizable, time-domain, time-mode

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Access URL: https://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-132788

High-Level Synthesis for SiLago: Advances in Optimization of High-Level Synthesis Tool and Neural Network Algorithms

Authors: Yang, Yu Hemani, Ahmed Lu, Zhonghai et al.

Contributors: Yang, Yu Hemani, Ahmed Lu, Zhonghai et al.

Source: TRITA-EECS-AVL.

Subject Terms: Electronic Design Automation (EDA), Computer Aided Design (CAD), Algorithm-level Synthesis, SiLago, Optimization Techniques, Neural Network, Informations- och kommunikationsteknik, Information and Communication Technology

File Description: electronic

Access URL: https://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-317555
https://kth.diva-portal.org/smash/get/diva2:1695389/FULLTEXT01.pdf

System exploration and synthesis from SDL of an ATM switch component

Authors: Ykman-Couvreur, Ch. Lambrecht, J. Verkest, D. et al.

Source: ASIC/SOC Conference, 1999. Proceedings. Twelfth Annual IEEE International. :119-124

Subject Terms: ATM switch component, SDL system specification, concurrency management, hardware synthesis, intensive data storage, memory management, object-oriented language, optimization methods, stepwise exploration, system exploration, system synthesis, timing constraints, very high bit-rate data streams, application specific integrated circuits, asynchronous transfer mode, circuit CAD, digital integrated circuits, electronic switching systems, high level synthesis, integrated circuit design, specification languages, storage management, telecommunication computing, timing

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Access URL: https://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-73113

High-Level Synthesis and Test in the MOSCITO-Based Virtual Laboratory

Authors: Schneider, Andre Diener, Karl-Heinz Jervan, Gert et al.

Source: The 8th biennial Baltic Electronics Conference BEC 2002,2002. :287-290

Subject Terms: high-level synthesis, testing, virtual laboratory, MOSCITO, hierarchical test generation, CAD tools, hardware software co-design, TECHNOLOGY, Information technology, Computer science, TEKNIKVETENSKAP, Informationsteknik, Datavetenskap

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Access URL: https://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-23349

Analýza metod digitálního návrhu a softwarového vývoje systémů na čipu ; Analysis of Digital and Embedded Engineering Methods for System on Chip Design

Authors: Emil Jiří Tywoniak Vítek Stanislav Onderka Jan

Contributors: Emil Jiří Tywoniak Vítek Stanislav Onderka Jan

Subject Terms: syntéza logiky, formální verifikace, automatizace fyzického návrhu, placement, routing, EDA, HDL, FPGA, ASIC, Yosys, OpenROAD, logic synthesis, formal verification, physical design automation

File Description: application/pdf; application/octet-stream

Relation: http://hdl.handle.net/10467/107315

Availability: http://hdl.handle.net/10467/107315

IoT-HarPSecA: A Framework for Facilitating the Design and Development of Secure IoT Devices

Authors: Samaila, Musa Gwani Sequeiros, João B. F. Freire, Mario et al.

Contributors: Samaila, Musa Gwani Sequeiros, João B. F. Freire, Mario et al.

Subject Terms: Internet of Things, Security framework, IoT-HarPSecA, Lightweight cryptographic algorithms, Software implementation, Hardware implementation, ACM Reference

File Description: application/pdf

Availability: http://hdl.handle.net/10400.6/9229

Controller Synthesis for Hardware Accelerator Design

Authors: Jiang, Hongtu Öwall, Viktor Lund University, Faculty of Engineering, LTH, Departments at LTH, Department of Electrical and Information Technology, Lunds universitet, Lunds Tekniska Högskola, Institutioner vid LTH, Institutionen för elektro- och informationsteknik, Originator

Contributors: Jiang, Hongtu Öwall, Viktor Lund University, Faculty of Engineering, LTH, Departments at LTH, Department of Electrical and Information Technology, Lunds universitet, Lunds Tekniska Högskola, Institutioner vid LTH, Institutionen för elektro- och informationsteknik, Originator

Source: Swedish System-on-Chip Conference 2002 (SSoCC 02).

Subject Terms: Engineering and Technology, Electrical Engineering, Electronic Engineering, Information Engineering, Teknik, Elektroteknik och elektronik

File Description: electronic

Access URL: https://lucris.lub.lu.se/ws/files/6244911/643747

Lowering power consumption in clock by using globally asynchronous locally synchronous design style

Authors: Hemani, Ahmed Meincke, Thomas Kumar, Shashi et al.

Source: Design Automation Conference, 1999. Proceedings. 36th. :873-878

Subject Terms: GALS, globally asynchronous locally synchronous design style, high performance VLSIs, local clock generation, overheads, partitioning, power consumption, power saving, synchronous blocks, VLSI, application specific integrated circuits, clocks, integrated circuit design, logic CAD, logic partitioning

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Access URL: https://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-73116

Guruprasad Rao of Magma's Silicon Correlation Division to Present on Cell Modeling Requirements for Low-Power Design at 2004 TAU Workshop February 3

Authors: By:LISARU

Source: Business Wire, February 2, 2004

Návrh a implementace řídícího programu pro CNC obráběcí stroj prostřednictvím B&R Automation ; Design and implementation of control program for CNC machine via B&R Automation

Authors: Vavrík, Michal Parák, Roman Lang, Stanislav

Contributors: Vavrík, Michal Parák, Roman Lang, Stanislav

Subject Terms: Robotizace frézky, CNC frézka, B+R Automatizace, Automation Studio, Scene Viewer, mappView, krokové motory, průmyslová vizualizace, digitální dvojče, dekodér G-kódu, interpret G-kódu, Milling machine robotization, CNC milling machine, B&R Automation, stepper motors, industrial visualization, digital twin, G-code decoder, G-code interpreter

File Description: application/pdf; application/zip; text/html

Relation: VAVRÍK, M. Návrh a implementace řídícího programu pro CNC obráběcí stroj prostřednictvím B&R Automation [online]. Brno: Vysoké učení technické v Brně. Fakulta strojního inženýrství. 2020.; 124830; http://hdl.handle.net/11012/191850

Availability: http://hdl.handle.net/11012/191850

On the History of Computer Science, Computer Engineering, and Computer Technology Development in...

Authors: Dujnic, Jozef Fristacky, Norbert

Source: IEEE Annals of the History of Computing; Jul-Sep99, Vol. 21 Issue 3, p38, 11p, 9 Black and White Photographs

Subject Terms: COMPUTERS, TECHNOLOGICAL innovations

Geographic Terms: SLOVAKIA

Free BDD based CAD of compact memristor crossbars for in-memory computing

Authors: Ul Hassen, A. Khokhar, S. A. Butt, Haseeb Aslam et al.

Source: Proceedings of the 14th IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2018. :107-113

Subject Terms: BDD, Binary decision diagrams, Boolean functions, Crossbar, In-Memory computing, Memristor, Synthesis of crossbars, Computer aided design, Leakage currents, Memory architecture, Memristors, Nanotechnology, Computing paradigm, Free binary decision diagrams, Nanoelectronic devices, Quantum tunneling, Reduced ordered binary decision diagram, Synthesis process

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Access URL: https://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-247205

Application of high-level synthesis in an industrial project

Authors: Hemani, Ahmed Karlsson, Borje Fredriksson, Mats et al.

Source: VLSI Design, 1994., Proceedings of the Seventh International Conference on. :5-10

Subject Terms: FPGA, behavioral VHDL, high-level synthesis tool, industrial project, logic synthesis, precise timing constraints, system-level, technology information feedback, circuit CAD, logic CAD, logic arrays, software tools, specification languages

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Access URL: https://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-73081

Návrh a implementace řídícího programu pro CNC obráběcí stroj prostřednictvím B&R Automation

Design and implementation of control program for CNC machine via B&R Automation

Authors: Vavrík, Michal

Thesis Advisors: Lang, Stanislav, Parák, Roman

Subject Terms: dekodér G-kódu, stepper motors, CNC frézka, Robotizace frézky, B+R Automatizace, Milling machine robotization, B&R Automation, digital twin, CNC milling machine, průmyslová vizualizace, interpret G-kódu, G-code decoder, mappView, G-code interpreter, industrial visualization, Automation Studio, krokové motory, Scene Viewer, digitální dvojče

Availability: http://www.nusl.cz/ntk/nusl-416642

Zavedení automatizace přípravy výroby s využitím pokročilých technologií

Authors: Slechan, Martin Videcká, Zdeňka Novotný, Rostislav

Contributors: Slechan, Martin Videcká, Zdeňka Novotný, Rostislav

Subject Terms: automatizace, digitalizace, automatization, tpv, configurator, konfigurátor, cad, digitalization

File Description: application/pdf; text/html

Access URL: http://hdl.handle.net/11012/205119