Výsledky vyhledávání - acm: b.: hardware/b.6: logic design/b.6.3: design cad/b.6.3.0: automatic synthesis

Evaluating Large Language Models for Automatic Register Transfer Logic Generation for Combinational Circuits via High-Level Synthesis.

Autoři: Swaroopa, Sneha Mukherjee, Rijoy Debnath, Anushka a další

Zdroj: Foundations & Trends in Electronic Design Automation; 2024, Vol. 14 Issue 4, p315-337, 23p

Témata: LANGUAGE models, COMBINATIONAL circuits, INTEGRATED circuit verification, C++, GRAPES

6 VTR 7.0: Next Generation Architecture and CAD System

Autoři: For Fpgas The Pennsylvania State University CiteSeerX Archives

Přispěvatelé: For Fpgas The Pennsylvania State University CiteSeerX Archives

Zdroj: http://www.eecg.utoronto.ca/~vaughn/papers/trets2014_vtr.pdf.

Témata: Categories and Subject Descriptors, B.6.3 [Logic Design, Design Aids—Automatic synthesis, B.7.2 [Inte- grated Circuits, Design Aids—Placement and routing, C.1.3 [Processor Architectures, Other Archi- tecture Styles—Adaptable architectures General Terms, Algorithms, Design Additional Key Words and Phrases, FPGA, CAD, architecture modeling ACM Reference Format

Popis souboru: application/pdf

Relation: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.636.4534; http://www.eecg.utoronto.ca/~vaughn/papers/trets2014_vtr.pdf

Dostupnost: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.636.4534
http://www.eecg.utoronto.ca/~vaughn/papers/trets2014_vtr.pdf

Towards Machine Learning-Based FPGA Backend Flow: Challenges and Opportunities.

Autoři: Taj, Imran Farooq, Umer

Zdroj: Electronics (2079-9292); Feb2023, Vol. 12 Issue 4, p935, 23p

Témata: SYSTEMS on a chip, MACHINE learning, COMPUTER-aided design, LOGIC design, GATE array circuits, CLOUD computing

Las Vegas to Host 23rd ACM/IEEE Design Automation Conference.

Zdroj: IEEE Design & Test of Computers; 1986, Vol. 3 Issue 3, p6-13, 8p

FPGA Design Automation: A Survey.

Autoři: Chen, Deming Cong, Jason Pan, Peichen

Zdroj: Foundations & Trends in Electronic Design Automation; 2006, Vol. 1 Issue 3, p195-330, 137p

Témata: COMPUTER-aided design, COMPUTER-aided engineering, ARCHITECTURE & technology, FIELD programmable gate arrays, PROGRAMMABLE logic devices, AUTOMATION, AUTOMATIC identification, CONTROL theory (Engineering)

Automatic synthesis of fuzzy logic controllers. ; Síntesis automática de controladores lógicos difusos.

Autoři: Barriga, Angel Sánchez-Solano, Santiago Jiménez Fernández, Carlos Jesús a další

Témata: Soporte físico-hardware, Sistemas CAD-CAM, Controladores difusos, Simulación, Lenguajes algorítmicos, Circuito integrado gran escala, Sistemas de tiempo real

Relation: http://hdl.handle.net/10261/2239

Dostupnost: http://hdl.handle.net/10261/2239

Cofactor Sharing for Reversible Logic Synthesis.

Autoři: SHAFAEI, ALIREZA SAEEDI, MEHDI PEDRAM, MASSOUD

Zdroj: ACM Journal on Emerging Technologies in Computing Systems; Oct2014, Vol. 11 Issue 2, p14-14:21, 21p

Témata: LOGIC circuit synthesis (Electronic design), ALGORITHMS, COMPUTER-aided design, SPARSE graphs, COMPUTER simulation

Teaching Hardware/Software System Codesign Using CAD Tools: A Case Study in Image Synthesis.

Autoři: Dubois, Helene Sentieys, Oliver

Zdroj: IEEE Transactions on Education; Aug2000, Vol. 43 Issue 3, p277, 7p, 15 Diagrams, 2 Charts

Témata: COMPUTER science, APPLICATION-specific integrated circuits, COMPUTER-aided design equipment, DESIGN, HIGHER education

Formation of IP-Core Libraries in the User IC Design Flow for FPGAs and RSoCs.

Autoři: Khvatov, V. M. Gavrilov, S. V.

Zdroj: Russian Microelectronics; Dec2022, Vol. 51 Issue 7, p567-572, 6p

Témata: INTEGRATED circuit design, LIBRARY users, SYSTEMS on a chip, LOGIC circuits, INTELLECTUAL property, FIELD programmable gate arrays

Automated Synthesis of Digital Hardware.

Autoři: Hafer Parker

Zdroj: IEEE Transactions on Computers; 1982, Vol. C-31 Issue 2, p93-109, 17p

Techniques for the Synthesis of Reversible Toffoli Networks

Autoři: D. Maslov G. W. Dueck D. M. Miller a další

Přispěvatelé: D. Maslov G. W. Dueck D. M. Miller a další

Zdroj: http://www.cs.uvic.ca/~mmiller/publications/a42-maslov.pdf.

Témata: B.6[Logic Design] [B.6.1 Design Styles, B.6.3 Design Aids, Computer-aided design (CAD, Automatic synthesis, Optimization, Switching theory General Terms, Hardware, Theory of Computation Additional Key Words and Phrases, quantum computing, reversible logic synthesis, circuit optimization 42

Popis souboru: application/pdf

Relation: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.216.9857

Dostupnost: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.216.9857
http://www.cs.uvic.ca/~mmiller/publications/a42-maslov.pdf

Optimized Synthesis Method for Ultra-Low Power Multi-Input Material Implication Logic With Emerging Non-Volatile Memories.

Autoři: Puglisi, Francesco Maria Zanotti, Tommaso Pavan, Paolo

Zdroj: IEEE Transactions on Circuits & Systems. Part I: Regular Papers; Nov2021, Vol. 68 Issue 11, p4433-4443, 11p

Témata: IMPLICATION (Logic), LOGIC circuits, COMPUTER-aided design software, HEURISTIC algorithms, BOOLEAN functions, OPERATIONS research

Dependence Graph Based Verification and Synthesis of Hardware/Software Co-Designs with SAT Related Formulation.

Autoři: Masahiro Fujita Kenshu Seto Thanyapat Sakunkonchak

Zdroj: Journal on Satisfiability, Boolean Modeling & Computation; 2009, Vol. 5, p57-82, 26p, 15 Diagrams, 5 Charts

Témata: SAT (Educational test), COMPUTER input-output equipment, PARALLEL computers, LEARNING, COMPUTER software

Automatic Design of Area-Efficient Configurable ASIC Cores.

Autoři: Compton, Katherine Hauck, Scott

Zdroj: IEEE Transactions on Computers; May2007, Vol. 56 Issue 5, p662-672, 11p, 2 Black and White Photographs, 8 Diagrams, 4 Charts, 1 Graph

Témata: COMPUTER input-output equipment, COMPUTER software, STANDARD cells, LOGIC design, INTEGRATED circuits, PROGRAM transformation, ROUTING (Computer network management), HEURISTIC programming

Warp Processing: Dynamic Translation of Binarles to FPGA Circuits.

Autoři: Vahid, Frank Stitt, Greg Lysecky, Roman

Zdroj: Computer (00189162); Jul2008, Vol. 41 Issue 7, p40-46, 7p

Témata: COMPUTER integrated manufacturing systems, INTEGRATED circuits, CAD/CAM systems, COMPUTER software, FIELD programmable gate arrays, GATE array circuits, PROGRAMMABLE logic devices

A Module for Automatic Assessment and Verification of Students' Work in Digital Logic Design.

Autoři: Stanisavljevic, Zarko Nikolic, Bosko Djordjevic, Jovan

Zdroj: 2012 IEEE 19th International Conference & Workshops on Engineering of Computer-Based Systems; 1/ 1/2012, p275-282, 8p

LEARNING HARDWARE USING MULTIPLE-VALUED LOGIC.

Autoři: Perkowski, Marek Foote, David Qihong Chen a další

Zdroj: IEEE Micro; May/Jun2002, Vol. 22 Issue 3, p41, 11p, 1 Diagram

Témata: COMPUTER input-output equipment, ALGORITHMS, COMPUTER architecture

Are Logic Synthesis Tools Robust?

Autoři: Puggelli, Alberto Welp, Tobias Kuehlmann, Andreas a další

Zdroj: DAC: Annual ACM/IEEE Design Automation Conference; Jun2011, p633-638, 6p, 2 Diagrams, 4 Charts, 5 Graphs

Témata: VERILOG (Computer hardware description language), ROBUST control, COMPUTER software correctness, ALGORITHMS, MATHEMATICAL transformations

A CAD suite for high-performance FPGA design.

Autoři: Hutchings, B. Bellows, P. Hawkins, J. a další

Zdroj: Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines (Cat NoPR00375); 1999, p12-24, 13p

CAD tools for ASIC design.

Autoři: Newton, A.R. Sangiovanni-Vincentelli, A.L.

Zdroj: Proceedings of the IEEE; 1987, Vol. 75 Issue 6, p765-776, 12p