Výsledky vyhľadávania - acm: b.: hardware/b.6: logic design/b.6.3: design art/b.6.3.2: optimization

Contributions to Program Optimization and High-Level Synthesis ; Contributions à l'optimisation de programmes et à la synthèse de circuits haut-niveau

Autori: Alias, Christophe CASH - Compilation and Analysis, Software and Hardware (CASH) Centre Inria de l'Université Grenoble Alpes a ďalší

Prispievatelia: Alias, Christophe CASH - Compilation and Analysis, Software and Hardware (CASH) Centre Inria de l'Université Grenoble Alpes a ďalší

Zdroj: https://inria.hal.science/tel-02151877 ; Hardware Architecture [cs.AR]. ENS de Lyon, 2019.

Predmety: High-Level Synthesis, Compilation Techniques, Automatic Parallelization, Compilation, Parallélisation automatique, Synthèse haut-niveau, FPGA, ACM: B.: Hardware, ACM: B.: Hardware/B.6: LOGIC DESIGN/B.6.3: Design Aids/B.6.3.0: Automatic synthesis, ACM: B.: Hardware/B.6: LOGIC DESIGN/B.6.3: Design Aids/B.6.3.2: Optimization, ACM: D.: Software/D.3: PROGRAMMING LANGUAGES/D.3.4: Processors/D.3.4.1: Compilers, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.4: Parallel Architectures, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [INFO.INFO-DC]Computer Science [cs]/Distributed, Parallel, and Cluster Computing [cs.DC], [INFO.INFO-PL]Computer Science [cs]/Programming Languages [cs.PL]

Dostupnosť: https://inria.hal.science/tel-02151877
https://inria.hal.science/tel-02151877v2/document
https://inria.hal.science/tel-02151877v2/file/hdr-alias.pdf

A semiempirical model for wakeup time estimation in power-gated logic clusters

Autori: Tovinakere Dwarakanath, Vivek Sentieys, Olivier Derrien, Steven a ďalší

Prispievatelia: Tovinakere Dwarakanath, Vivek Sentieys, Olivier Derrien, Steven a ďalší

Zdroj: The 49th Annual Design Automation Conference 2012, DAC '12, San Francisco, CA, USA, June 3-7, 2012 ; https://inria.hal.science/hal-00752606 ; The 49th Annual Design Automation Conference 2012, DAC '12, San Francisco, CA, USA, June 3-7, 2012, Jun 2012, San Fransisco, United States. pp.48-55

Predmety: ACM: B.: Hardware/B.7: INTEGRATED CIRCUITS/B.7.1: Types and Design Styles/B.7.1.7: VLSI (very large scale integration), ACM: B.: Hardware/B.6: LOGIC DESIGN/B.6.3: Design Aids/B.6.3.2: Optimization, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

Geografické téma: San Fransisco, United States

Dostupnosť: https://inria.hal.science/hal-00752606

Active Leakage Power Optimization for FPGAs.

Autori: Anderson, Jason H. Najm, Farid N.

Zdroj: IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems; Mar2006, Vol. 25 Issue 3, p423-437, 15p, 2 Black and White Photographs, 5 Charts, 17 Graphs

Predmety: FIELD programmable gate arrays, COMPLEMENTARY metal oxide semiconductors, COMPUTER-aided design, GATE array circuits, LOGIC circuits, ELECTRONIC circuit design, COMPUTER engineering

Leveraging HLS to Design a Versatile & High-Performance Classic McEliece Accelerator.

Autori: Kostalabros, Ioannis-Vatistas Ribes, Jordi Carril, Xavier a ďalší

Zdroj: ACM Transactions on Embedded Computing Systems; Sep2025, Vol. 24 Issue 5, p1-27, 27p

Predmety: CRYPTOGRAPHY, FIELD programmable gate arrays, QUANTUM computing, COMPUTER hardware description languages, BANDWIDTHS, LOGIC design, HIGH performance computing

Reconfigurable Hardware SAT Solvers: A Survey of Systems.

Autori: Skilarova, Iouliia Ferrari, António de Brito

Zdroj: IEEE Transactions on Computers; Nov2004, Vol. 53 Issue 11, p1449-1461, 13p

Predmety: PROGRAMMABLE logic devices, NETWORK processors, ELECTRONIC equipment, ALGORITHMS, COMBINATORIAL optimization, COMPUTER programming

SHIFT: Selective Hardware Information Flow Tracking Driven by Deterministic Constraints.

Autori: Sun, Haodong Yang, Zhi Jin, Shuyuan a ďalší

Zdroj: ACM Journal on Emerging Technologies in Computing Systems; Oct2025, Vol. 21 Issue 4, p1-16, 16p

Predmety: HARDWARE design & construction, CONSTRAINED optimization, MATHEMATICAL optimization, SCIENTIFIC apparatus & instruments, RISK assessment

GALU: A Genetic Algorithm Framework for Logic Unlocking.

Autori: Chen, Huili Fu, Cheng Zhao, Jishen a ďalší

Zdroj: Digital Threats: Research & Practice; Jun2023, Vol. 4 Issue 2, p1-30, 30p

Predmety: LOGIC circuits, LOGIC, COMBINATORIAL optimization, INTERNET piracy, GENETIC algorithms

Hardware–Software Co-Optimization of Long-Latency Stochastic Computing.

Autori: Aygun, Sercan Kouhalvandi, Lida Najafi, M. Hassan a ďalší

Zdroj: IEEE Embedded Systems Letters; Dec2023, Vol. 15 Issue 4, p190-193, 4p

On compiling Boolean circuits optimized for secure multi-party computation.

Autori: Büscher, Niklas Franz, Martin Holzer, Andreas a ďalší

Zdroj: Formal Methods in System Design; Nov2017, Vol. 51 Issue 2, p308-331, 24p

Predmety: LOGIC circuits, PRIVATE sector, CRYPTOGRAPHY, COMBINATORIAL optimization, COMPUTATIONAL complexity

Throughput and FIFO Sizing: an Application to Latency-Insensitive Design

Autori: Boucaron, Julien Coadou, Anthony de Simone, Robert a ďalší

Prispievatelia: Boucaron, Julien Coadou, Anthony de Simone, Robert a ďalší

Zdroj: https://inria.hal.science/inria-00381644 ; [Research Report] RR-6919, INRIA. 2009, pp.19.

Predmety: FIFO sizing, Buffer sizing, Throughput, Latency-Insensitive Design, Marked Graphs, ACM: F.: Theory of Computation/F.1: COMPUTATION BY ABSTRACT DEVICES/F.1.1: Models of Computation, ACM: B.: Hardware/B.6: LOGIC DESIGN, ACM: B.: Hardware/B.7: INTEGRATED CIRCUITS, [INFO.INFO-MO]Computer Science [cs]/Modeling and Simulation, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

Dostupnosť: https://inria.hal.science/inria-00381644
https://inria.hal.science/inria-00381644v1/document
https://inria.hal.science/inria-00381644v1/file/RR-6919.pdf

Polynomial inversion hardware accelerator for post quantum algorithm.

Autori: Divya, B Raja Sekar, K David Selvakumar, A a ďalší

Zdroj: Sādhanā: Academy Proceedings in Engineering Sciences; Dec2025, Vol. 50 Issue 4, p1-14, 14p

Predmety: CRYPTOGRAPHY, POLYNOMIALS, ALGORITHMS, PROGRAMMABLE logic devices, COMPUTATIONAL complexity, OPTIMIZATION algorithms

Boltzmann Machine Using Superconducting Circuits.

Autori: Miyake, Kohei Yamanashi, Yuki Yoshikawa, Nobuyuki

Zdroj: IEEE Transactions on Applied Superconductivity; Jun2022, Vol. 32 Issue 4, p1-5, 5p

Predmety: BOLTZMANN machine, ARTIFICIAL neural networks, MAXIMUM likelihood statistics, LOGIC circuits, MACHINE learning, SUPERCONDUCTING circuits, ENERGY function

Designing an Asynchronous Microcontroller Using Pipefitter.

Autori: Blunno, Ivan Lavagno, Luciano

Zdroj: IEEE Transactions on Very Large Scale Integration (VLSI) Systems; Jul2004, Vol. 12 Issue 7, p696-700, 5p, 3 Charts

Predmety: ASYNCHRONOUS circuits, COMPUTER hardware description languages, DIGITAL electronics, VERILOG (Computer hardware description language), INTEGRATED circuits, ELECTRONIC circuits

Don't-Care-Based Node Minimization for Threshold Logic Networks.

Autori: Yung-Chih Chen Hao-Ju Chang Li-Cheng Zheng

Zdroj: DAC: Annual ACM/IEEE Design Automation Conference; 2020, Issue 57, p1100-1105, 6p

Predmety: THRESHOLD logic, LINEAR programming, AUTOMATION, DEEP learning, MATHEMATICAL optimization

HMSA: High-Performance Heterogeneous Mixed-Precision CNN Systolic Array Accelerator on FPGA.

Autori: Cao, Yongxiang Jiang, Hongxu Li, Huiyong a ďalší

Zdroj: ACM Transactions on Embedded Computing Systems; 2025 Suppl 5, Vol. 24, p1-27, 27p

Predmety: FIELD programmable gate arrays, CONVOLUTIONAL neural networks, SIGNAL quantization, ARTIFICIAL neural networks, ARRAY processors, PARALLEL processing, COPROCESSORS

TRIGGERING DETECTION TECHNIQUE OF THE HARDWARE TROJANS IN THE COMBINATIONAL LOGIC SYSTEMS.

Autori: Timis, Grigore Mihai Valachi, Alexandru

Zdroj: Annals of the University Dunarea de Jos of Galati Fascicle III: Electrotechnics, Electronics, Automatic Control & Informatics; 2021, Vol. 44 Issue 1, p23-28, 6p

Predmety: HAZARD Analysis & Critical Control Point (Food safety system), INTEGRATED circuits, HARDWARE, LOGIC, LEAKS (Disclosure of information)

Multi-Objective Local-Search Optimization using Reliability Importance Measuring.

Autori: Khosravi, Faramarz Reimann, Felix Glaß, Michael a ďalší

Zdroj: DAC: Annual ACM/IEEE Design Automation Conference; 2014, p77-82, 6p

Predmety: EMBEDDED computer system design & construction, REDUNDANCY in engineering, COMPUTER software, COMPUTER input-output equipment, LOGIC circuits, MATHEMATICAL optimization

Dynamic Profiling and Fuzzy-Logic-Based Optimization of Sensor Network Platforms.

Autori: LIZARRAGA, ADRIAN LYSECKY, ROMAN LYSECKY, SUSAN a ďalší

Zdroj: ACM Transactions on Embedded Computing Systems; Dec2013, Vol. 13 Issue 3, p51:1-51:29, 29p

Predmety: DYNAMICAL systems, FUZZY logic, MATHEMATICAL optimization, SENSOR networks, APPLICATION software, COMPUTER engineering

COSMOS: Coordination of High-Level Synthesis and Memory Optimization for Hardware Accelerators.

Autori: PICCOLBONI, LUCA MANTOVANI, PAOLO DI GUGLIELMO, GIUSEPPE a ďalší

Zdroj: ACM Transactions on Embedded Computing Systems; 2017 Special Issue, Vol. 16 Issue 5s, p1-22, 22p

Predmety: SYSTEMS on a chip, EMBEDDED computer systems, COMPUTER architecture, PROGRAM transformation, HIGH level synthesis (Electronic design)

Evaluating Large Language Models for Automatic Register Transfer Logic Generation for Combinational Circuits via High-Level Synthesis.

Autori: Swaroopa, Sneha Mukherjee, Rijoy Debnath, Anushka a ďalší

Zdroj: Foundations & Trends in Electronic Design Automation; 2024, Vol. 14 Issue 4, p315-337, 23p

Predmety: LANGUAGE models, COMBINATIONAL circuits, INTEGRATED circuit verification, C++, GRAPES