Výsledky vyhledávání - acm: b.: hardware/b.6: logic design/b.6.3: design art/b.6.3.0: automatizacia synthesis

Design of hardware RGB to HMMD converter based on reversible logic.

Autoři: Touil, Lamjed Ouni, Bouraoui

Zdroj: IET Image Processing (Wiley-Blackwell); Aug2017, Vol. 11 Issue 8, p646-655, 10p

Témata: REVERSIBLE computing, OPTICAL information processing, LOGIC design, QUANTUM information science, CELLULAR automata, DIGITAL electronics

A 0.13mJ/Prediction CIFAR-100 Fully Synthesizable Raster-Scan-Based Wired-Logic Processor in 16-nm FPGA

Autoři: Atsutake Kosuge Dongzhu Li Mototsugu Hamada a další

Zdroj: IEICE Transactions on Electronics. :2023

Area-efficient parallel adder with faithful approximation for image and signal processing applications.

Autoři: Palanisamy, Gnanambikai Natarajan, Vijeyakumar Krishnasamy Sundaram, Kalaiselvi

Zdroj: IET Image Processing (Wiley-Blackwell); 2019, Vol. 13 Issue 13, p2587-2594, 8p

Témata: SIGNAL processing, IMAGE processing, LOGIC design, METAL oxide semiconductor field-effect transistors, BLOCK designs, TRANSISTORS, DELAY-tolerant networks

Magma's Rajeev Madhavan to Provide Keynote Address at ISPD; ''The Death of Logic Synthesis''

Zdroj: Business Wire, March 30, 2005

RELIEF TEXTURE MAPPING ON FIELD PROGRAMMABLE GATE ARRAY.

Autoři: LI, XIAOYING WU, ENHUA

Zdroj: International Journal of Image & Graphics; Oct2006, Vol. 6 Issue 4, p641-655, 15p, 4 Black and White Photographs, 6 Diagrams, 2 Charts

Témata: RENDERING works, RELIEF (Art), IMAGE stabilization, WEAVING, FIELD programmable gate arrays, COMPUTER graphics, COMPUTER-generated imagery

Hardware acceleration of YOLOv7-tiny using high-level synthesis tools.

Autoři: Hosseiny, Adib Jahanirad, Hadi

Zdroj: Journal of Real-Time Image Processing; Aug2023, Vol. 20 Issue 4, p1-10, 10p

Field Programmable Gate Array Applications—A Scientometric Review.

Autoři: Ruiz-Rosero, Juan Ramirez-Gonzalez, Gustavo Khanna, Rahul

Zdroj: Computation; Dec2019, Vol. 7 Issue 4, p63-63, 1p

Témata: FIELD programmable gate arrays, DIGITAL video, PROGRAMMABLE logic devices, DIGITAL signal processing, MAGNETIC suspension, SYSTEMS on a chip

GenSeq+: A Scalable High-Performance Accelerator for Genome Sequencing.

Autoři: Wang, Chao Gong, Lei Lei, Shiming a další

Zdroj: IEEE/ACM Transactions on Computational Biology & Bioinformatics; Jul/Aug2021, Vol. 18 Issue 4, p1512-1523, 12p

Logic Design for Custom LSIs / カスタムLSIの論理設計

Autoři: Takashi NANYA 南谷 崇

Zdroj: 計測と制御 / Journal of The Society of Instrument and Control Engineers. 1989, 28(10):861

Custom Hardware Architectures for Deep Learning on Portable Devices: A Review.

Autoři: Zaman, Kh Shahriya Reaz, Mamun Bin Ibne Md Ali, Sawal Hamid a další

Zdroj: IEEE Transactions on Neural Networks & Learning Systems; Nov2022, Vol. 33 Issue 11, p6068-6088, 21p

Témata: DEEP learning, APPLICATION-specific integrated circuits, OBJECT recognition (Computer vision), ARTIFICIAL neural networks, GATE array circuits, IMAGE recognition (Computer vision)

A Survey of Memristive Threshold Logic Circuits.

Autoři: Maan, Akshay Kumar Jayadevi, Deepthi Anirudhan James, Alex Pappachen

Zdroj: IEEE Transactions on Neural Networks & Learning Systems; Aug2017, Vol. 28 Issue 8, p1734-1746, 13p

Témata: NEURONS, THRESHOLD logic, NANOELECTROMECHANICAL systems, MATHEMATICAL models

Synchoricity and NOCs could make Billion Gate custom hardware centric SOCs affordable

Autoři: Hemani, Ahmed Jafri, Syed Masoumian, S.

Zdroj: 2017 11th IEEE/ACM International Symposium on Networks-on-Chip, NOCS 2017.

Témata: ASICs, Coarse Grain Reconfiguration, ESL, High-level Synthesis, NOCs, SOCs, Synchoricity, VLSI Design

Popis souboru: print

Přístupová URL adresa: https://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-219649

Design of a pseudo-log image transform hardware accelerator in a high-level synthesis-based memory management framework.

Autoři: Butt, Shahzad Ahmad Mancini, Stéphane Rousseau, Frédéric a další

Zdroj: Journal of Electronic Imaging; Sep/Oct2014, Vol. 23 Issue 5, p1-13, 13p

Témata: TRANSFORM coding, IMAGE processing, KERNEL functions, COMPUTER memory management, LOOP tiling (Computer science)

All-Passive Hardware Implementation of Multilayer Perceptron Classifiers.

Autoři: Ananthakrishnan, Akshay Allen, Mark G.

Zdroj: IEEE Transactions on Neural Networks & Learning Systems; Sep2021, Vol. 32 Issue 9, p4086-4095, 10p

Témata: PASSIVE components, MULTILAYER perceptrons, HARDWARE, ANALOG circuits

Recursive Threshold Logic—A Bioinspired Reconfigurable Dynamic Logic System With Crossbar Arrays.

Autoři: James, Alex Krestinskaya, Olga Maan, Akshay

Zdroj: IEEE Transactions on Biomedical Circuits & Systems; Dec2020, Vol. 14 Issue 6, p1311-1322, 12p

Hardware architecture for projective model calculation and false match refining using random sample consensus algorithm.

Autoři: Azimi, Ehsan Behrad, Alireza Ghaznavi-Ghoushchi, Mohammad Bagher a další

Zdroj: Journal of Electronic Imaging; Nov/Dec2016, Vol. 25 Issue 6, p1-15, 15p

Témata: ALGORITHMS, IMAGING systems, IMAGE reconstruction, IMAGE registration, THREE-dimensional imaging

First-Order Logic Based Situational and Dynamic Interpretation of Natural Language Descriptions in Hardware Design Specifications / ハードウェア設計仕様における自然言語記述の一階論理に基づく状況的・動的解釈

Autoři: Koichi KISE Kunio FUKUNAGA Noriaki IZUMI a další

Zdroj: 人工知能 / Journal of the Japanese Society for Artificial Intelligence. 1995, 10(5):720

Relaxed Fault-Tolerant Hardware Implementation of Neural Networks in the Presence of Multiple Transient Errors.

Autoři: Mahdiani, Hamid Reza Fakhraie, Sied Mehdi Lucas, Caro

Zdroj: IEEE Transactions on Neural Networks & Learning Systems; Aug2012, Vol. 23 Issue 8, p1215-1228, 14p

Témata: ARTIFICIAL neural networks, COMPUTER input-output equipment, INTEGRATED circuit fault tolerance, HUMAN facial recognition software, LOGIC circuits

Toward Full-Stack Acceleration of Deep Convolutional Neural Networks on FPGAs.

Autoři: Liu, Shuanglong Fan, Hongxiang Ferianc, Martin a další

Zdroj: IEEE Transactions on Neural Networks & Learning Systems; Aug2022, Vol. 33 Issue 8, p3974-3987, 14p

Témata: CONVOLUTIONAL neural networks, ARTIFICIAL neural networks, DEEP learning, DIGITAL signal processing, GATE array circuits, FIELD programmable gate arrays

Korporace: INTEL Corp.

Bio-mimicking DNA fingerprint profiling for HLS watermarking to counter hardware IP piracy.

Autoři: Sengupta A Bhui N Anshul A a další

Zdroj: Scientific reports [Sci Rep] 2024 Sep 28; Vol. 14 (1), pp. 22413. Date of Electronic Publication: 2024 Sep 28.

Způsob vydávání: Journal Article

Informace o časopise: Publisher: Nature Publishing Group Country of Publication: England NLM ID: 101563288 Publication Model: Electronic Cited Medium: Internet ISSN: 2045-2322 (Electronic) Linking ISSN: 20452322 NLM ISO Abbreviation: Sci Rep Subsets: MEDLINE

Výrazy ze slovníku MeSH: Computer Security* , DNA Fingerprinting*/methods , Algorithms*, Humans ; Computers ; DNA