Search Results - acm: b.: hardware/b.6: logic design/b.6.3: design art/b.6.3.0: automatic synthesis*

Contributions to Program Optimization and High-Level Synthesis ; Contributions à l'optimisation de programmes et à la synthèse de circuits haut-niveau

Authors: Alias, Christophe CASH - Compilation and Analysis, Software and Hardware (CASH) Centre Inria de l'Université Grenoble Alpes et al.

Contributors: Alias, Christophe CASH - Compilation and Analysis, Software and Hardware (CASH) Centre Inria de l'Université Grenoble Alpes et al.

Source: https://inria.hal.science/tel-02151877 ; Hardware Architecture [cs.AR]. ENS de Lyon, 2019.

Subject Terms: High-Level Synthesis, Compilation Techniques, Automatic Parallelization, Compilation, Parallélisation automatique, Synthèse haut-niveau, FPGA, ACM: B.: Hardware, ACM: B.: Hardware/B.6: LOGIC DESIGN/B.6.3: Design Aids/B.6.3.0: Automatic synthesis, ACM: B.: Hardware/B.6: LOGIC DESIGN/B.6.3: Design Aids/B.6.3.2: Optimization, ACM: D.: Software/D.3: PROGRAMMING LANGUAGES/D.3.4: Processors/D.3.4.1: Compilers, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.4: Parallel Architectures, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [INFO.INFO-DC]Computer Science [cs]/Distributed, Parallel, and Cluster Computing [cs.DC], [INFO.INFO-PL]Computer Science [cs]/Programming Languages [cs.PL]

Availability: https://inria.hal.science/tel-02151877
https://inria.hal.science/tel-02151877v2/document
https://inria.hal.science/tel-02151877v2/file/hdr-alias.pdf

Model Driven Engineering Benefits for High Level Synthesis

Authors: Le Beux, Sébastien Marquet, Philippe Dekeyser, Jean-Luc et al.

Contributors: Le Beux, Sébastien Marquet, Philippe Dekeyser, Jean-Luc et al.

Source: https://inria.hal.science/inria-00311300 ; [Research Report] RR-6615, INRIA. 2008, pp.46.

Subject Terms: ACM: B.: Hardware/B.6: LOGIC DESIGN/B.6.3: Design Aids/B.6.3.0: Automatic synthesis, ACM: B.: Hardware/B.6: LOGIC DESIGN/B.6.1: Design Styles/B.6.1.5: Parallel circuits, ACM: B.: Hardware/B.8: PERFORMANCE AND RELIABILITY/B.8.2: Performance Analysis and Design Aids, ACM: I.: Computing Methodologies/I.6: SIMULATION AND MODELING/I.6.5: Model Development/I.6.5.0: Modeling methodologies, ACM: C.: Computer Systems Organization/C.3: SPECIAL-PURPOSE AND APPLICATION-BASED SYSTEMS/C.3.2: Real-time and embedded systems, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

Availability: https://inria.hal.science/inria-00311300
https://inria.hal.science/inria-00311300/document
https://inria.hal.science/inria-00311300/file/RR-6615.pdf

Evaluating Large Language Models for Automatic Register Transfer Logic Generation for Combinational Circuits via High-Level Synthesis.

Authors: Swaroopa, Sneha Mukherjee, Rijoy Debnath, Anushka et al.

Source: Foundations & Trends in Electronic Design Automation; 2024, Vol. 14 Issue 4, p315-337, 23p

Subject Terms: LANGUAGE models, COMBINATIONAL circuits, INTEGRATED circuit verification, C++, GRAPES

Time-redundancy transformations for adaptive fault-tolerant circuits

Authors: Burlyaev, Dmitry Fradet, Pascal Girault, Alain et al.

Contributors: Burlyaev, Dmitry Fradet, Pascal Girault, Alain et al.

Source: 2015 NASA/ESA Conference on Adaptive Hardware and Systems (AHS)
https://inria.hal.science/hal-01253111
2015 NASA/ESA Conference on Adaptive Hardware and Systems (AHS), Jun 2015, Montreal, Canada. ⟨10.1109/AHS.2015.7231164⟩

Subject Terms: digital circuits, fault tolerance, time redundancy, circuit transformation, ACM: B.: Hardware/B.5: REGISTER-TRANSFER-LEVEL IMPLEMENTATION/B.5.3: Reliability and Testing/B.5.3.2: Redundant design, ACM: B.: Hardware/B.5: REGISTER-TRANSFER-LEVEL IMPLEMENTATION/B.5.2: Design Aids/B.5.2.0: Automatic synthesis, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [INFO.INFO-PF]Computer Science [cs]/Performance [cs.PF]

Subject Geographic: Montreal

Time: Montreal, Canada

Availability: https://inria.hal.science/hal-01253111
https://doi.org/10.1109/AHS.2015.7231164

FPGA-Specific Synthesis of Loop-Nests with Pipelined Computational Cores

Authors: Alias, Christophe Pasca, Bogdan Plesco, Alexandru et al.

Contributors: Alias, Christophe Pasca, Bogdan Plesco, Alexandru et al.

Source: https://inria.hal.science/inria-00606977 ; [Research Report] RR-7674, INRIA. 2011, pp.33.

Subject Terms: High-Level Synthesis, Compiler, ACM: B.: Hardware/B.2: ARITHMETIC AND LOGIC STRUCTURES/B.2.4: High-Speed Arithmetic, ACM: B.: Hardware/B.6: LOGIC DESIGN/B.6.3: Design Aids, ACM: C.: Computer Systems Organization/C.3: SPECIAL-PURPOSE AND APPLICATION-BASED SYSTEMS/C.3.3: Signal processing systems, [INFO.INFO-AO]Computer Science [cs]/Computer Arithmetic, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [INFO.INFO-DC]Computer Science [cs]/Distributed, Parallel, and Cluster Computing [cs.DC], [INFO.INFO-PL]Computer Science [cs]/Programming Languages [cs.PL], [INFO.INFO-IA]Computer Science [cs]/Computer Aided Engineering, [INFO.INFO-ES]Computer Science [cs]/Embedded Systems

Availability: https://inria.hal.science/inria-00606977
https://inria.hal.science/inria-00606977v1/document
https://inria.hal.science/inria-00606977v1/file/RR-7674.pdf

The Ubimus Plugging Framework: Deploying FPGA-Based Prototypes for Ubiquitous Music Hardware Design.

Authors: Keller, Damián Jagwani, Aman Lazzarini, Victor

Source: Computers (2073-431X); Apr2025, Vol. 14 Issue 4, p155, 24p

Subject Terms: COMPUTER hardware description languages, LEARNING curve, GATE array circuits, LOGIC circuits, INTEGRATED circuits

Automated Synthesis of Digital Hardware.

Authors: Hafer Parker

Source: IEEE Transactions on Computers; 1982, Vol. C-31 Issue 2, p93-109, 17p

Dependence Graph Based Verification and Synthesis of Hardware/Software Co-Designs with SAT Related Formulation.

Authors: Masahiro Fujita Kenshu Seto Thanyapat Sakunkonchak

Source: Journal on Satisfiability, Boolean Modeling & Computation; 2009, Vol. 5, p57-82, 26p, 15 Diagrams, 5 Charts

Subject Terms: SAT (Educational test), COMPUTER input-output equipment, PARALLEL computers, LEARNING, COMPUTER software

COSMOS: Coordination of High-Level Synthesis and Memory Optimization for Hardware Accelerators.

Authors: PICCOLBONI, LUCA MANTOVANI, PAOLO DI GUGLIELMO, GIUSEPPE et al.

Source: ACM Transactions on Embedded Computing Systems; 2017 Special Issue, Vol. 16 Issue 5s, p1-22, 22p

Subject Terms: SYSTEMS on a chip, EMBEDDED computer systems, COMPUTER architecture, PROGRAM transformation, HIGH level synthesis (Electronic design)

SCOPE: Synthesis-Based Constant Propagation Attack on Logic Locking.

Authors: Alaql, Abdulrahman Rahman, Md Moshiur Bhunia, Swarup

Source: IEEE Transactions on Very Large Scale Integration (VLSI) Systems; Aug2021, Vol. 29 Issue 8, p1529-1542, 14p

Subject Terms: LOGIC, SEMICONDUCTOR industry, INTELLECTUAL property, SCIENTIFIC community, IP networks

Automatic Time-Redundancy Transformation for Fault-Tolerant Circuits

Authors: Burlyaev, Dmitry Fradet, Pascal Girault, Alain et al.

Contributors: Burlyaev, Dmitry Fradet, Pascal Girault, Alain et al.

Source: 23rd ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, FPGA'15
https://inria.hal.science/hal-01095747
23rd ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, FPGA'15, Feb 2015, Monterey, United States. ⟨10.1145/2684746.2689058⟩

Subject Terms: ACM: B.: Hardware/B.5: REGISTER-TRANSFER-LEVEL IMPLEMENTATION/B.5.3: Reliability and Testing, ACM: B.: Hardware/B.5: REGISTER-TRANSFER-LEVEL IMPLEMENTATION/B.5.2: Design Aids/B.5.2.0: Automatic synthesis, ACM: B.: Hardware/B.5: REGISTER-TRANSFER-LEVEL IMPLEMENTATION/B.5.2: Design Aids/B.5.2.4: Verification, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [INFO.INFO-PF]Computer Science [cs]/Performance [cs.PF]

Subject Geographic: Monterey, United States

Availability: https://inria.hal.science/hal-01095747
https://doi.org/10.1145/2684746.2689058

Smart Vision Chip for colon exploration ; Smart Vision Chip pour l’exploration du colon

Authors: Chuquimia, Orlando Systèmes Electroniques (SYEL) LIP6 et al.

Contributors: Chuquimia, Orlando Systèmes Electroniques (SYEL) LIP6 et al.

Source: https://tel.archives-ouvertes.fr/tel-02494557 ; Imagerie médicale. Sorbonne Université, 2019. Français.

Subject Terms: Automatic polyp detection, intelligent endoscopic capsule, Hough transform, fuzzy trees, fuzzy forest, artificial vision and hardware accelerator, vision artificielle et accélérateur matériel, Détection automatique des polypes, capsule endoscopique intelligente, transformée d’Hough, arbres flous, forets floues, ACM: B.: Hardware/B.6: LOGIC DESIGN/B.6.3: Design Aids, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES, ACM: C.: Computer Systems Organization/C.5: COMPUTER SYSTEM IMPLEMENTATION, ACM: I.: Computing Methodologies/I.2: ARTIFICIAL INTELLIGENCE/I.2.6: Learning, ACM: I.: Computing Methodologies/I.2: ARTIFICIAL INTELLIGENCE/I.2.9: Robotics, ACM: I.: Computing Methodologies/I.2: ARTIFICIAL INTELLIGENCE/I.2.10: Vision and Scene Understanding, ACM: I.: Computing Methodologies/I.4: IMAGE PROCESSING AND COMPUTER VISION/I.4.7: Feature Measurement/I.4.7.5: Texture, ACM: I.: Computing Methodologies/I.4: IMAGE PROCESSING AND COMPUTER VISION/I.4.0: General/I.4.0.1: Image processing software, [INFO.INFO-IM]Computer Science [cs]/Medical Imaging, [INFO.INFO-CV]Computer Science [cs]/Computer Vision and Pattern Recognition [cs.CV], [INFO.INFO-ES]Computer Science [cs]/Embedded Systems, [INFO.INFO-AI]Computer Science [cs]/Artificial Intelligence [cs.AI], [INFO.INFO-RB]Computer Science [cs]/Robotics [cs.RO]

Relation: tel-02494557; https://tel.archives-ouvertes.fr/tel-02494557; https://tel.archives-ouvertes.fr/tel-02494557/document; https://tel.archives-ouvertes.fr/tel-02494557/file/thhese_archivage__N%C2%B0dossier.pdf

Availability: https://tel.archives-ouvertes.fr/tel-02494557
https://tel.archives-ouvertes.fr/tel-02494557/document
https://tel.archives-ouvertes.fr/tel-02494557/file/thhese_archivage__N%C2%B0dossier.pdf

Improving Netlist Transformation-Based Approximate Logic Synthesis Through Resynthesis.

Authors: Morales-Monge, Roger Castro-Godinez, Jorge Paim, Guilherme

Source: IEEE Embedded Systems Letters; Sep2024, Vol. 16 Issue 3, p279-282, 4p

R-Accelerator: An RRAM-Based CGRA Accelerator With Logic Contraction.

Authors: Chen, Zhengyu Zhou, Hai Gu, Jie

Source: IEEE Transactions on Very Large Scale Integration (VLSI) Systems; Nov2019, Vol. 27 Issue 11, p2655-2667, 13p

Subject Terms: MULTICASTING (Computer networks), INTEGRATED circuit interconnections, INTEGRATED circuits, LOGIC, COMMERCIAL art

A Survey on Assertion-based Hardware Verification.

Authors: WITHARANA, HASINI YANGDI LYU CHARLES, SUBODHA et al.

Source: ACM Computing Surveys; 2022 Suppl 11, Vol. 54, p1-33, 33p

Subject Terms: INTEGRATED circuit verification, DEBUGGING, ELECTRONIC systems

Custom-Instruction Synthesis for Extensible-Processor Platforms.

Authors: Sun, Fei Ravi, Srivaths Raghunathan, Anand et al.

Source: IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems; Feb2004, Vol. 23 Issue 2, p216-228, 13p

Subject Terms: SYSTEMS design, COMPUTER-aided design, CUSTOMIZATION, MACRO processors, INTEGRATED circuits, COMMERCIAL art

Behavioral Synthesis of Asynchronous Circuits Using Syntax Directed Translation as Backend.

Authors: Nielsen, Sune Fallgaard Spars∅, Jens Madsen, Jan

Source: IEEE Transactions on Very Large Scale Integration (VLSI) Systems; Feb2009, Vol. 17 Issue 2, p248-261, 14p, 3 Black and White Photographs, 6 Charts

Subject Terms: ASYNCHRONOUS circuits, SYNCHRONOUS circuits, DESIGN templates, COMPUTER hardware description languages, CONSTRAINT satisfaction, COMPUTER scheduling, DATA flow computing, CODE generators

TRIGGERING DETECTION TECHNIQUE OF THE HARDWARE TROJANS IN THE COMBINATIONAL LOGIC SYSTEMS.

Authors: Timis, Grigore Mihai Valachi, Alexandru

Source: Annals of the University Dunarea de Jos of Galati Fascicle III: Electrotechnics, Electronics, Automatic Control & Informatics; 2021, Vol. 44 Issue 1, p23-28, 6p

Subject Terms: HAZARD Analysis & Critical Control Point (Food safety system), INTEGRATED circuits, HARDWARE, LOGIC, LEAKS (Disclosure of information)

Are Logic Synthesis Tools Robust?

Authors: Puggelli, Alberto Welp, Tobias Kuehlmann, Andreas et al.

Source: DAC: Annual ACM/IEEE Design Automation Conference; Jun2011, p633-638, 6p, 2 Diagrams, 4 Charts, 5 Graphs

Subject Terms: VERILOG (Computer hardware description language), ROBUST control, COMPUTER software correctness, ALGORITHMS, MATHEMATICAL transformations

StitchUp: Automatic Control Flow Protection for High Level Synthesis Circuits.

Authors: Fleming, Shane T. Thomas, David B.

Source: DAC: Annual ACM/IEEE Design Automation Conference; Jun2016, p815-820, 6p

Subject Terms: ERROR detection (Information theory), LOGIC circuit synthesis (Electronic design), FIELD programmable gate arrays, DATA flow computing, DATA transmission systems, MATHEMATICAL models