Suchergebnisse - acm: b.: hardware/b.6: logic design/b.6.3: design aids/b.6.3.0: automatizacia synthesis*

Design of hardware RGB to HMMD converter based on reversible logic.

Autoren: Touil, Lamjed Ouni, Bouraoui

Quelle: IET Image Processing (Wiley-Blackwell); Aug2017, Vol. 11 Issue 8, p646-655, 10p

Schlagwörter: REVERSIBLE computing, OPTICAL information processing, LOGIC design, QUANTUM information science, CELLULAR automata, DIGITAL electronics

Constrained least square nonuniform dynamic filter bank for delay and Hardware efficient digital hearing aids.

Autoren: Mahesh, V. V. Shahana, T. K.

Quelle: Health & Technology; May2019, Vol. 9 Issue 3, p355-363, 9p

Magma's Rajeev Madhavan to Provide Keynote Address at ISPD; ''The Death of Logic Synthesis''

Quelle: Business Wire, March 30, 2005

Bio-mimicking DNA fingerprint profiling for HLS watermarking to counter hardware IP piracy.

Autoren: Sengupta A Bhui N Anshul A et al.

Quelle: Scientific reports [Sci Rep] 2024 Sep 28; Vol. 14 (1), pp. 22413. Date of Electronic Publication: 2024 Sep 28.

Publikationsart: Journal Article

Info zur Zeitschrift: Publisher: Nature Publishing Group Country of Publication: England NLM ID: 101563288 Publication Model: Electronic Cited Medium: Internet ISSN: 2045-2322 (Electronic) Linking ISSN: 20452322 NLM ISO Abbreviation: Sci Rep Subsets: MEDLINE

MeSH-Schlagworte: Computer Security* , DNA Fingerprinting*/methods , Algorithms*, Humans ; Computers ; DNA

Area-efficient parallel adder with faithful approximation for image and signal processing applications.

Autoren: Palanisamy, Gnanambikai Natarajan, Vijeyakumar Krishnasamy Sundaram, Kalaiselvi

Quelle: IET Image Processing (Wiley-Blackwell); 2019, Vol. 13 Issue 13, p2587-2594, 8p

Schlagwörter: SIGNAL processing, IMAGE processing, LOGIC design, METAL oxide semiconductor field-effect transistors, BLOCK designs, TRANSISTORS, DELAY-tolerant networks

Logic Design for Custom LSIs / カスタムLSIの論理設計

Autoren: Takashi NANYA 南谷 崇

Quelle: 計測と制御 / Journal of The Society of Instrument and Control Engineers. 1989, 28(10):861

Design and synthesis of filter bank structures based on low order constrained least square and minimum phase methods for audiogram matching in digital hearing aids.

Autoren: Mahesh, V. V. Shahana, T. K.

Quelle: Health & Technology; 2021, Vol. 11 Issue 1, p153-168, 16p

First-Order Logic Based Situational and Dynamic Interpretation of Natural Language Descriptions in Hardware Design Specifications / ハードウェア設計仕様における自然言語記述の一階論理に基づく状況的・動的解釈

Autoren: Koichi KISE Kunio FUKUNAGA Noriaki IZUMI et al.

Quelle: 人工知能 / Journal of the Japanese Society for Artificial Intelligence. 1995, 10(5):720

Relaxed Fault-Tolerant Hardware Implementation of Neural Networks in the Presence of Multiple Transient Errors.

Autoren: Mahdiani, Hamid Reza Fakhraie, Sied Mehdi Lucas, Caro

Quelle: IEEE Transactions on Neural Networks & Learning Systems; Aug2012, Vol. 23 Issue 8, p1215-1228, 14p

Schlagwörter: ARTIFICIAL neural networks, COMPUTER input-output equipment, INTEGRATED circuit fault tolerance, HUMAN facial recognition software, LOGIC circuits

A 0.13mJ/Prediction CIFAR-100 Fully Synthesizable Raster-Scan-Based Wired-Logic Processor in 16-nm FPGA

Autoren: Atsutake Kosuge Dongzhu Li Mototsugu Hamada et al.

Quelle: IEICE Transactions on Electronics. :2023

Synplicity's Synplify ASIC Adopted by Industry Leaders; Quality of Results and Vendor Endorsements Fuel Growth in ASIC Products

Autoren: By:ALEX

Quelle: Business Wire, February 17, 2004

ECG Authentication Hardware Design With Low-Power Signal Processing and Neural Network Optimization With Low Precision and Structured Compression.

Autoren: Cherupally, Sai Kiran Yin, Shihui Kadetotad, Deepak et al.

Quelle: IEEE Transactions on Biomedical Circuits & Systems; Apr2020, Vol. 14 Issue 2, p198-208, 11p

FPGA implementation of semi-fragile reversible watermarking by histogram bin shifting in real time.

Autoren: Hazra, Sambaran Ghosh, Sudip De, Sayandip et al.

Quelle: Journal of Real-Time Image Processing; Jan2018, Vol. 14 Issue 1, p193-221, 29p

Case study of an HEVC decoder application using high-level synthesis: intraprediction, dequantization, and inverse transform blocks.

Autoren: Kammoun, Manel Atitallah, Ahmed Ben Ali, Karim M. A. et al.

Quelle: Journal of Electronic Imaging; May/Jun2019, Vol. 28 Issue 3, p33010-33010, 1p

Schlagwörter: VIDEO coding, CASE studies, ALGORITHMS

Hardware acceleration of YOLOv7-tiny using high-level synthesis tools.

Autoren: Hosseiny, Adib Jahanirad, Hadi

Quelle: Journal of Real-Time Image Processing; Aug2023, Vol. 20 Issue 4, p1-10, 10p

Compiler-assisted code generation for quantum computing: leveraging the unique properties of quantum architectures.

Autoren: James, G. G. Ekong, A. P. Unyime, A. U. et al.

Quelle: Journal of Nigerian Society of Physical Sciences; May2025, Vol. 7 Issue 2, p1-12, 12p

Schlagwörter: QUANTUM computing, QUBITS, COMPUTER software development, MATHEMATICAL optimization, COMPARATIVE studies

ON THE SYNTHESIS OF DECISION TABLES.

Autoren: Srinivasan, B.

Quelle: Communications of the ACM. Feb1983, Vol. 26 Issue 2, p135-136. 2p.

Schlagwörter: *DECISION logic tables, *SYSTEMS design, *DECISION making

Exploring subthreshold processing for next-generation TinyAI.

Autoren: Nakhle, Farid Harfouche, Antoine H. Karam, Hani et al.

Quelle: Frontiers in Computational Neuroscience; 2025, p1-12, 12p

Schlagwörter: ENERGY consumption, BIOLOGICAL neural networks, BIOLOGICALLY inspired computing, ARTIFICIAL intelligence, ARTIFICIAL neural networks

A Review of Algorithm & Hardware Design for AI-Based Biomedical Applications.

Autoren: Wei, Ying Zhou, Jun Wang, Yin et al.

Quelle: IEEE Transactions on Biomedical Circuits & Systems; Apr2020, Vol. 14 Issue 2, p145-163, 19p

Guruprasad Rao of Magma's Silicon Correlation Division to Present on Cell Modeling Requirements for Low-Power Design at 2004 TAU Workshop February 3

Autoren: By:LISARU

Quelle: Business Wire, February 2, 2004