Search Results - acm: b.: hardware/b.6: logic design/b.6.3: design aids/b.6.3.0: automation synthesis

Model Driven Engineering Benefits for High Level Synthesis

Authors: Le Beux, Sébastien Marquet, Philippe Dekeyser, Jean-Luc et al.

Contributors: Le Beux, Sébastien Marquet, Philippe Dekeyser, Jean-Luc et al.

Source: https://inria.hal.science/inria-00311300 ; [Research Report] RR-6615, INRIA. 2008, pp.46.

Subject Terms: ACM: B.: Hardware/B.6: LOGIC DESIGN/B.6.3: Design Aids/B.6.3.0: Automatic synthesis, ACM: B.: Hardware/B.6: LOGIC DESIGN/B.6.1: Design Styles/B.6.1.5: Parallel circuits, ACM: B.: Hardware/B.8: PERFORMANCE AND RELIABILITY/B.8.2: Performance Analysis and Design Aids, ACM: I.: Computing Methodologies/I.6: SIMULATION AND MODELING/I.6.5: Model Development/I.6.5.0: Modeling methodologies, ACM: C.: Computer Systems Organization/C.3: SPECIAL-PURPOSE AND APPLICATION-BASED SYSTEMS/C.3.2: Real-time and embedded systems, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

Availability: https://inria.hal.science/inria-00311300
https://inria.hal.science/inria-00311300/document
https://inria.hal.science/inria-00311300/file/RR-6615.pdf

FPGA-Specific Synthesis of Loop-Nests with Pipelined Computational Cores

Authors: Alias, Christophe Pasca, Bogdan Plesco, Alexandru et al.

Contributors: Alias, Christophe Pasca, Bogdan Plesco, Alexandru et al.

Source: https://inria.hal.science/inria-00606977 ; [Research Report] RR-7674, INRIA. 2011, pp.33.

Subject Terms: High-Level Synthesis, Compiler, ACM: B.: Hardware/B.2: ARITHMETIC AND LOGIC STRUCTURES/B.2.4: High-Speed Arithmetic, ACM: B.: Hardware/B.6: LOGIC DESIGN/B.6.3: Design Aids, ACM: C.: Computer Systems Organization/C.3: SPECIAL-PURPOSE AND APPLICATION-BASED SYSTEMS/C.3.3: Signal processing systems, [INFO.INFO-AO]Computer Science [cs]/Computer Arithmetic, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [INFO.INFO-DC]Computer Science [cs]/Distributed, Parallel, and Cluster Computing [cs.DC], [INFO.INFO-PL]Computer Science [cs]/Programming Languages [cs.PL], [INFO.INFO-IA]Computer Science [cs]/Computer Aided Engineering, [INFO.INFO-ES]Computer Science [cs]/Embedded Systems

Availability: https://inria.hal.science/inria-00606977
https://inria.hal.science/inria-00606977v1/document
https://inria.hal.science/inria-00606977v1/file/RR-7674.pdf

Automated Synthesis of Digital Hardware.

Authors: Hafer Parker

Source: IEEE Transactions on Computers; 1982, Vol. C-31 Issue 2, p93-109, 17p

Accelerated and Highly Correlated ASIC Synthesis of AI Hardware Subsystems Using CGP.

Authors: Prashanth, H. C. Rao, Madhav

Source: IET Computers & Digital Techniques (Wiley-Blackwell); 1/29/2024, Vol. 2024, p1-23, 23p

Subject Terms: LOGIC circuits, ARTIFICIAL intelligence, HARDWARE

SlackHammer: Logic Synthesis for Graceful Errors Under Frequency Scaling.

Authors: Alan, Tanfer Henkel, Jorg

Source: IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems; Nov2018, Vol. 37 Issue 11, p2802-2811, 10p

Subject Terms: LOGIC circuit synthesis (Electronic design), CRITICAL path analysis, ERROR rates, APPROXIMATION theory, CROSS layer optimization, ELECTRONIC design automation, REAL-time computing

25th ACM/IEEE Design Automation Conference ®.

Source: Computer (00189162); 1987, Vol. 20 Issue 10, p103-103, 1p

A Polynomial Based Approach to Wakeup Time and Energy Estimation in Power-Gated Logic Clusters

Authors: D. Tovinakere, Vivek Sentieys, Olivier Derrien, Steven et al.

Contributors: D. Tovinakere, Vivek Sentieys, Olivier Derrien, Steven et al.

Source: ISSN: 1546-1998 ; Journal of Low Power Electronics ; https://inria.hal.science/hal-00747721 ; Journal of Low Power Electronics, 2011, 7 (4), pp.482-489. ⟨10.1166/jolpe.2011.1159⟩.

Subject Terms: ACM: B.: Hardware/B.7: INTEGRATED CIRCUITS/B.7.2: Design Aids, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

Availability: https://inria.hal.science/hal-00747721
https://doi.org/10.1166/jolpe.2011.1159

Las Vegas to Host 23rd ACM/IEEE Design Automation Conference.

Source: IEEE Design & Test of Computers; 1986, Vol. 3 Issue 3, p6-13, 8p

Specification and Synthesis of Hardware Checkpointing and Rollback Mechanisms.

Authors: Carven Chan Schwartz-Narbonne, Daniel Sethi, Divjyot et al.

Source: DAC: Annual ACM/IEEE Design Automation Conference; Jun2012, p1226-1232, 7p

Subject Terms: ROLLBACK recovery (Computer science), RTL (Computer program language), COMPUTER hardware description languages, NETWORK routers, INTEGRATED circuit interconnections, NETWORK performance, SYSTEMS design

Toward Understanding FPGA Synthesis Tool Bugs.

Authors: Zhang, Yi Jiang, He Guo, Shikai et al.

Source: ACM Transactions on Software Engineering & Methodology; Sep2025, Vol. 34 Issue 7, p1-37, 37p

Subject Terms: FIELD programmable gate arrays, RELIABILITY in engineering, SOFTWARE validation, EMPIRICAL research, MATHEMATICAL optimization, SOFTWARE development tools

SMatch: Structural Matching for Fast Resynthesis in FPGAs.

Authors: Trapani Possignolo, Rafael Renau, Jose

Source: DAC: Annual ACM/IEEE Design Automation Conference; 2019, Issue 56, p1027-1032, 6p

Subject Terms: FIELD programmable gate arrays, ELECTRONIC design automation, LOGIC circuit synthesis (Electronic design), AGILE software development, SOFTWARE engineering

A semiempirical model for wakeup time estimation in power-gated logic clusters

Authors: Tovinakere Dwarakanath, Vivek Sentieys, Olivier Derrien, Steven et al.

Contributors: Tovinakere Dwarakanath, Vivek Sentieys, Olivier Derrien, Steven et al.

Source: The 49th Annual Design Automation Conference 2012, DAC '12, San Francisco, CA, USA, June 3-7, 2012 ; https://inria.hal.science/hal-00752606 ; The 49th Annual Design Automation Conference 2012, DAC '12, San Francisco, CA, USA, June 3-7, 2012, Jun 2012, San Fransisco, United States. pp.48-55

Subject Terms: ACM: B.: Hardware/B.7: INTEGRATED CIRCUITS/B.7.1: Types and Design Styles/B.7.1.7: VLSI (very large scale integration), ACM: B.: Hardware/B.6: LOGIC DESIGN/B.6.3: Design Aids/B.6.3.2: Optimization, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

Subject Geographic: San Fransisco, United States

Availability: https://inria.hal.science/hal-00752606

The First EDA MOOC: Teaching Design Automation to Planet Earth.

Authors: Rutenbar, Rob A.

Source: DAC: Annual ACM/IEEE Design Automation Conference; 2014, p1247-1254, 8p

Subject Terms: MASSIVE open online courses, ELECTRONIC design automation, VERY large scale circuit integration, INTEGRATED circuit layout, COMPUTER-aided design of integrated circuits

Are Logic Synthesis Tools Robust?

Authors: Puggelli, Alberto Welp, Tobias Kuehlmann, Andreas et al.

Source: DAC: Annual ACM/IEEE Design Automation Conference; Jun2011, p633-638, 6p, 2 Diagrams, 4 Charts, 5 Graphs

Subject Terms: VERILOG (Computer hardware description language), ROBUST control, COMPUTER software correctness, ALGORITHMS, MATHEMATICAL transformations

SALSA: Systematic Logic Synthesis of Approximate Circuits.

Authors: Venkataramani, Swagath Sabne, Amit Kozhikkottu, Vivek et al.

Source: DAC: Annual ACM/IEEE Design Automation Conference; Jun2012, p796-801, 6p

Subject Terms: ELECTRONIC design automation, ALGORITHMS, ALGEBRAIC logic, EUCLIDEAN algorithm, SCALABILITY

Flexible Implementation of Genetic Algorithms on FPGAs

Authors: Tatsuhiro Tachibana Yoshihiro Murata Naoki Shibata et al.

Contributors: Tatsuhiro Tachibana Yoshihiro Murata Naoki Shibata et al.

Source: http://ito-lab.naist.jp/themes/pdffiles/060220.tatsu-ta.fpga2006.pdf.

Subject Terms: Categories and Subject Descriptors B6.3 [Logic Design, Design Aids- Automatic synthesis General Terms Design, Experimentation Keywords genetic algorithm, FPGA, hardware design automation, Knapsack Problem, Traveling Salesman Problem

File Description: application/pdf

Relation: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.114.2588

Availability: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.114.2588
http://ito-lab.naist.jp/themes/pdffiles/060220.tatsu-ta.fpga2006.pdf

Magma's Rajeev Madhavan to Provide Keynote Address at ISPD; ''The Death of Logic Synthesis''

Source: Business Wire, March 30, 2005

Smart Vision Chip for colon exploration ; Smart Vision Chip pour l’exploration du colon

Authors: Chuquimia, Orlando Systèmes Electroniques (SYEL) LIP6 et al.

Contributors: Chuquimia, Orlando Systèmes Electroniques (SYEL) LIP6 et al.

Source: https://tel.archives-ouvertes.fr/tel-02494557 ; Imagerie médicale. Sorbonne Université, 2019. Français.

Subject Terms: Automatic polyp detection, intelligent endoscopic capsule, Hough transform, fuzzy trees, fuzzy forest, artificial vision and hardware accelerator, vision artificielle et accélérateur matériel, Détection automatique des polypes, capsule endoscopique intelligente, transformée d’Hough, arbres flous, forets floues, ACM: B.: Hardware/B.6: LOGIC DESIGN/B.6.3: Design Aids, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES, ACM: C.: Computer Systems Organization/C.5: COMPUTER SYSTEM IMPLEMENTATION, ACM: I.: Computing Methodologies/I.2: ARTIFICIAL INTELLIGENCE/I.2.6: Learning, ACM: I.: Computing Methodologies/I.2: ARTIFICIAL INTELLIGENCE/I.2.9: Robotics, ACM: I.: Computing Methodologies/I.2: ARTIFICIAL INTELLIGENCE/I.2.10: Vision and Scene Understanding, ACM: I.: Computing Methodologies/I.4: IMAGE PROCESSING AND COMPUTER VISION/I.4.7: Feature Measurement/I.4.7.5: Texture, ACM: I.: Computing Methodologies/I.4: IMAGE PROCESSING AND COMPUTER VISION/I.4.0: General/I.4.0.1: Image processing software, [INFO.INFO-IM]Computer Science [cs]/Medical Imaging, [INFO.INFO-CV]Computer Science [cs]/Computer Vision and Pattern Recognition [cs.CV], [INFO.INFO-ES]Computer Science [cs]/Embedded Systems, [INFO.INFO-AI]Computer Science [cs]/Artificial Intelligence [cs.AI], [INFO.INFO-RB]Computer Science [cs]/Robotics [cs.RO]

Relation: tel-02494557; https://tel.archives-ouvertes.fr/tel-02494557; https://tel.archives-ouvertes.fr/tel-02494557/document; https://tel.archives-ouvertes.fr/tel-02494557/file/thhese_archivage__N%C2%B0dossier.pdf

Availability: https://tel.archives-ouvertes.fr/tel-02494557
https://tel.archives-ouvertes.fr/tel-02494557/document
https://tel.archives-ouvertes.fr/tel-02494557/file/thhese_archivage__N%C2%B0dossier.pdf

Cofactor Sharing for Reversible Logic Synthesis.

Authors: SHAFAEI, ALIREZA SAEEDI, MEHDI PEDRAM, MASSOUD

Source: ACM Journal on Emerging Technologies in Computing Systems; Oct2014, Vol. 11 Issue 2, p14-14:21, 21p

Subject Terms: LOGIC circuit synthesis (Electronic design), ALGORITHMS, COMPUTER-aided design, SPARSE graphs, COMPUTER simulation

High-level synthesis: current status and future prospects.

Authors: Cheng, H. Xia, C.

Source: Circuits, Systems & Signal Processing; May1995, Vol. 14 Issue 3, p351-400, 50p